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I HC NNG

TRNG I HC BCH KHOA


KHOA IN T - VIN THNG
-------------

--------------

BO CO LAB

CU TRC MY TNH
LAB 2: MIPS 32-bit ALU

SVTH

TRN VN DNG
TRNH NGC T
H TH PHC M

NHM
LP

:
:

14A
08DT1

Nng, thng 11 nm 2011.

Lab 2 Cu trc my tnh

MIPS ALU

Contents
1. Yu cu thit k: ............................................................................................................. 2
2. Gii thiu MIPS ALU: .................................................................................................... 2
3. Thit k: .............................................................................................................................. 3
3.1. Thit k b cng 32 bit ............................................................................................... 3
3.1.1. B cng 1 bit ............................................................................................................ 3
3.1.2. B cng 32 bit.......................................................................................................... 4
3.2. Thit k b tr 32 bit: ................................................................................................. 5
3.2.1. B tr 1 bit: .............................................................................................................. 5
3.2.2. B tr 32 bit............................................................................................................. 6
3.3. Thit k b XOR 32 bit: ............................................................................................... 7
3.4. Thit k SLT: ................................................................................................................... 8
3.5. Xt cc c:......................................................................................................................... 9
3.5.1. C zero: ...................................................................................................................... 9
3.5.2. C negative: ............................................................................................................. 9
3.5.3. C carryout: ............................................................................................................. 9
3.5.4. C overflow: .......................................................................................................... 10
3.6. Xc nh ng ra: .......................................................................................................... 11
3.7. ALU 32 bit...................................................................................................................... 13
4. Kim tra bng chng trnh Testbench......................................................... 16

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

LAB 2 : MIPS 32 BIT ALU


1. Yu cu thit k:
- Thit k 1 b MIPS ALU 32 bit n gin.
- C|c php to|n yu cu: ADD, SUB, XOR, SLT
- Yu cu chung:
+ Dng cu trc lnh structural
+ C|c cng logic khng c qu| 4 ng vo
+ Delay 50ps
2. Gii thiu MIPS ALU:
- S khi

Cu to MIPS ALU:
+ 2 ng vo BusA v BusB 32 bit
+ 1 ng ra Output 32 bit
+ C|c c ng ra: zero, overflow, carryout, negative
C zero: c set khi kt qu bng 0
C overflow (tr{n khi thc hin cng tr vi s c du): c set khi xy ra
trn
C carryout (tr{n khi thc hin cng tr vi s khng du): xy ra khi c
nh (mn) t MSB

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

C negative: c set nu kt qu }m
+ Ng v{o iu khin ALUcontrol gm 2 bit x|c nh php to|n m{ ALU cn thc
hin:

3. Thit k:
- Hng thit k:
+ 2 u v{o A,B 32 bit, u ra cng l{ 32 bit
=> Chia ra th{nh 32 khi nh, mi khi x l 2 bit d liu v{o (ly t A,B) a
ra 1 bit ca ng ra
3.1. Thit k b cng 32 bit
3.1.1. B cng 1 bit
- thit k b cng 32 bit, ta thit k b cng 1 bit
- S khi b cng to{n phn:

Thit lp bng gi| tr:

a
0
0
0
0
1
1
1
1

Nhm 14A 08DT1

Input
Output
b cAddIn Sum cAddOut
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
0
1
1
1
1
1

Lab 2 Cu trc my tnh


-

Ti thiu ha bng bng Karnaugh:

Phng trnh trng th|i:


sum= a xor b xor cAddIn
cAddOut = ab + cAddIn(a+b)

Code verilog:

MIPS ALU

/**************** Add for 1 bit ****************/


module add1bit(sum,cAddOut,A,B,cAddIn);
output sum,cAddOut;
input A,B,cAddIn;
wire tem1,tem2,tem3;
and #50 and1(tem1,A,B);
or #50 or1(tem2,A,B);
and #50 and2(tem3,tem2,cAddIn);
or #50 or2(cAddOut,tem3,tem1);
xor #50 xor1(sum,A,B,cAddIn);
endmodule

3.1.2. B cng 32 bit


- Gi 32 ln b cng 1 bit theo th t t 0 n 31 ta c b cng 32 bit:
- Code Verilog:
/************** Adder 32 bit *****************/
module add32bit(sum,cAddOut,A,B,overflow);
output [31:0]sum;
output cAddOut,overflow;
input [31:0]A,B;
wire [30:0]Co;
add1bit
add1bit
add1bit
add1bit
add1bit
add1bit
add1bit
add1bit
add1bit
add1bit

add0(sum[0],Co[0],A[0],B[0],1'b0);
add1(sum[1],Co[1],A[1],B[1],Co[0]);
add2(sum[2],Co[2],A[2],B[2],Co[1]);
add3(sum[3],Co[3],A[3],B[3],Co[2]);
add4(sum[4],Co[4],A[4],B[4],Co[3]);
add5(sum[5],Co[5],A[5],B[5],Co[4]);
add6(sum[6],Co[6],A[6],B[6],Co[5]);
add7(sum[7],Co[7],A[7],B[7],Co[6]);
add8(sum[8],Co[8],A[8],B[8],Co[7]);
add9(sum[9],Co[9],A[9],B[9],Co[8]);

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

add1bit add10(sum[10],Co[10],A[10],B[10],Co[9]);
add1bit add11(sum[11],Co[11],A[11],B[11],Co[10]);
add1bit add12(sum[12],Co[12],A[12],B[12],Co[11]);
add1bit add13(sum[13],Co[13],A[13],B[13],Co[12]);
add1bit add14(sum[14],Co[14],A[14],B[14],Co[13]);
add1bit add15(sum[15],Co[15],A[15],B[15],Co[14]);
add1bit add16(sum[16],Co[16],A[16],B[16],Co[15]);
add1bit add17(sum[17],Co[17],A[17],B[17],Co[16]);
add1bit add18(sum[18],Co[18],A[18],B[18],Co[17]);
add1bit add19(sum[19],Co[19],A[19],B[19],Co[18]);
add1bit add20(sum[20],Co[20],A[20],B[20],Co[19]);
add1bit add21(sum[21],Co[21],A[21],B[21],Co[20]);
add1bit add22(sum[22],Co[22],A[22],B[22],Co[21]);
add1bit add23(sum[23],Co[23],A[23],B[23],Co[22]);
add1bit add24(sum[24],Co[24],A[24],B[24],Co[23]);
add1bit add25(sum[25],Co[25],A[25],B[25],Co[24]);
add1bit add26(sum[26],Co[26],A[26],B[26],Co[25]);
add1bit add27(sum[27],Co[27],A[27],B[27],Co[26]);
add1bit add28(sum[28],Co[28],A[28],B[28],Co[27]);
add1bit add29(sum[29],Co[29],A[29],B[29],Co[28]);
add1bit add30(sum[30],Co[30],A[30],B[30],Co[29]);
add1bit add31(sum[31],cAddOut,A[31],B[31],Co[30]);
xor (overflow,cAddOut,Co[30]);
endmodule

3.2. Thit k b tr 32 bit:


3.2.1. B tr 1 bit:
- Tng t b cng, thit k b tr 1 bit, ta c bng gi| tr:

a
0
0
0
0
1
1
1
1
-

Input
Output
b cSubIn Sub cSubOut
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1

Tng t, ta cng c phng trnh trng th|i:


Sub= a xor b xor cSubIn
cSubOut = nota.b + cSubIn(nota + b)
Code Verilog:
/*************** Sub for 1 bit ****************/
module sub1bit(sub,cSubOut,A,B,cSubIn);

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

output sub,cSubOut;
input A,B,cSubIn;
wire tem1,tem2,tem3;
and #50 and1(tem1,(~A),B);
or #50 or1(tem2,(~A),B);
and #50 and2(tem3,tem2,cSubIn);
or #50 or2(cSubOut,tem3,tem1);
xor #50 xor1(sub,A,B,cSubIn);
endmodule

3.2.2. B tr 32 bit
- Gi 32 ln b tr 1 bit theo th t bit 0 n bit 31, ta c b tr 32 bit:
/********************Subtractor for 32 bit******************/
module sub32bit(sub,cSubOut,A,B,overflow);
output [31:0]sub;
output cSubOut,overflow;
input [31:0]A,B;
wire [30:0]Co;
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit
sub1bit

sub0(sub[0],Co[0],A[0],B[0],1'b0);
sub1(sub[1],Co[1],A[1],B[1],Co[0]);
sub2(sub[2],Co[2],A[2],B[2],Co[1]);
sub3(sub[3],Co[3],A[3],B[3],Co[2]);
sub4(sub[4],Co[4],A[4],B[4],Co[3]);
sub5(sub[5],Co[5],A[5],B[5],Co[4]);
sub6(sub[6],Co[6],A[6],B[6],Co[5]);
sub7(sub[7],Co[7],A[7],B[7],Co[6]);
sub8(sub[8],Co[8],A[8],B[8],Co[7]);
sub9(sub[9],Co[9],A[9],B[9],Co[8]);
sub10(sub[10],Co[10],A[10],B[10],Co[9]);
sub11(sub[11],Co[11],A[11],B[11],Co[10]);
sub12(sub[12],Co[12],A[12],B[12],Co[11]);
sub13(sub[13],Co[13],A[13],B[13],Co[12]);
sub14(sub[14],Co[14],A[14],B[14],Co[13]);
sub15(sub[15],Co[15],A[15],B[15],Co[14]);
sub16(sub[16],Co[16],A[16],B[16],Co[15]);
sub17(sub[17],Co[17],A[17],B[17],Co[16]);
sub18(sub[18],Co[18],A[18],B[18],Co[17]);
sub19(sub[19],Co[19],A[19],B[19],Co[18]);
sub20(sub[20],Co[20],A[20],B[20],Co[19]);
sub21(sub[21],Co[21],A[21],B[21],Co[20]);
sub22(sub[22],Co[22],A[22],B[22],Co[21]);
sub23(sub[23],Co[23],A[23],B[23],Co[22]);
sub24(sub[24],Co[24],A[24],B[24],Co[23]);
sub25(sub[25],Co[25],A[25],B[25],Co[24]);
sub26(sub[26],Co[26],A[26],B[26],Co[25]);
sub27(sub[27],Co[27],A[27],B[27],Co[26]);

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

sub1bit sub28(sub[28],Co[28],A[28],B[28],Co[27]);
sub1bit sub29(sub[29],Co[29],A[29],B[29],Co[28]);
sub1bit sub30(sub[30],Co[30],A[30],B[30],Co[29]);
sub1bit sub31(sub[31],cSubOut,A[31],B[31],Co[30]);
xor (overflow,cSubOut,Co[30]);
endmodule

3.3. Thit k b XOR 32 bit:


- thit k b xor 32 ta thit k t 32 b xor 1 bit
- Bng trng th|i:
a b a xor b
0 0
0
0 1
1
1 0
1
1 1
0
-

Code Verilog:
/****************** XOR 32 bit *****************/
module xor32bit(xor32,A,B);
output [31:0]xor32;
input [31:0]A,B;
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor
xor

#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50
#50

xor0(xor32[0],A[0],B[0]);
xor1(xor32[1],A[1],B[1]);
xor2(xor32[2],A[2],B[2]);
xor3(xor32[3],A[3],B[3]);
xor4(xor32[4],A[4],B[4]);
xor5(xor32[5],A[5],B[5]);
xor6(xor32[6],A[6],B[6]);
xor7(xor32[7],A[7],B[7]);
xor8(xor32[8],A[8],B[8]);
xor9(xor32[9],A[9],B[9]);
xor10(xor32[10],A[10],B[10]);
xor11(xor32[11],A[11],B[11]);
xor12(xor32[12],A[12],B[12]);
xor13(xor32[13],A[13],B[13]);
xor14(xor32[14],A[14],B[14]);
xor15(xor32[15],A[15],B[15]);
xor16(xor32[16],A[16],B[16]);
xor17(xor32[17],A[17],B[17]);
xor18(xor32[18],A[18],B[18]);
xor19(xor32[19],A[19],B[19]);
xor20(xor32[20],A[20],B[20]);
xor21(xor32[21],A[21],B[21]);
xor22(xor32[22],A[22],B[22]);

Nhm 14A 08DT1

Lab 2 Cu trc my tnh


xor
xor
xor
xor
xor
xor
xor
xor
xor

#50
#50
#50
#50
#50
#50
#50
#50
#50

MIPS ALU

xor23(xor32[23],A[23],B[23]);
xor24(xor32[24],A[24],B[24]);
xor25(xor32[25],A[25],B[25]);
xor26(xor32[26],A[26],B[26]);
xor27(xor32[27],A[27],B[27]);
xor28(xor32[28],A[28],B[28]);
xor29(xor32[29],A[29],B[29]);
xor30(xor32[30],A[30],B[30]);
xor31(xor32[31],A[31],B[31]);

endmodule

3.4. Thit k SLT:


- Cho kt qu bng 1 nu A < B
- Quan t}m ti bit LSB, c|c bit cn li = 0
- A< B AB<0
=> LSB bng bit du thc s ca kt qu php tr. Tuy nhin bit du thc s
khng phi l{ MSB (most signification bit) ca Output, do c th xy ra tr{n s
(Overflow)

slt[31:1] = 31b0
slt[0] = sub[31] xor overflow
-

Code verilog:
/********************SLT 32 bit******************/
//if A<B set = 1
module SLT32bit(slt,A,B);
output [31:0]slt;
input [31:0]A,B;
wire overflow;
wire[31:0]sub;
wire cOut;

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

sub32bit sub32(sub,cOut,A,B,overflow);
xor #50 xor1(slt[0],sub[31],overflow);
assign slt[31:1] = 31'b0;
endmodule

3.5. Xt cc c:
3.5.1. C zero:
- Khi kt qu bng 0 th c zero c set ln 1
- Dng lnh nor tt c c|c bit t 0 n 31 ca kt qu kim tra c Zero.
- Code verilog:
//Determine zero flag
or #50 or01(term01, Out[0], Out[1], Out[2], Out[3]);
or #50 or02(term02, Out[4], Out[5], Out[6], Out[7]);
or #50 or03(term03, Out[8], Out[9], Out[10], Out[11]);
or #50 or04(term04, Out[12], Out[13], Out[14], Out[15]);
or
or
or
or

#50
#50
#50
#50

or05(term05,
or06(term06,
or07(term07,
or08(term08,

Out[16],
Out[20],
Out[24],
Out[28],

Out[17],
Out[21],
Out[25],
Out[29],

Out[18],
Out[22],
Out[26],
Out[30],

Out[19]);
Out[23]);
Out[27]);
Out[31]);

or #50 or11(term11, term01, term02, term03, term04);


or #50 or12(term12, term05, term06, term07, term08);
nor
#50 nor0(zero, term11, term12);

3.5.2. C negative:
- C Negative: g|n c Negative bng bit th 31 ca kt qu.
+ Bit th 31 = 1 (kt qu }m): c c set
+ Bit th 31 = 0 (kt qu dng): c khng c set
- Code Verilog:
// Determine negative flag
assign negative = Out[31];

3.5.3. C carryout:
- Ch xt i vi php cng tr.
- C carry chnh l{ cAddOut hoc cSubOut ca php cng hoc php tr.
- Code verilog:
//Determine carry flag, it just turns on when ALU does subtract
or add
wire [1:0]f;
and #50 and3(f[0],(~ALUcontrol[1]),carryout1);
and #50 and4(f[1],ALUcontrol[1],carryout2);

Nhm 14A 08DT1

Lab 2 Cu trc my tnh

MIPS ALU

or #50 or1(carry,f[0],f[1]);
and
#50 and5(CarryOut, carry, (~ALUcontrol[0]));
endmodule

3.5.4. C overflow:
- Overflow (tr{n c du xy ra khi kt qu php to|n vt qu| di gii hn tnh
ton).
- A, B khc du th khng xy ra Overflow
=> Overflow ch xy ra khi cng 2 s cng du
-

Nhn bit:

i vi php cng: 2 s hng ca php cng cng du nhng kt qu kh|c du


vi 2 s hng .
+ Cng 2 s dng:
Khng xy ra overflow: bit 31 bng 0 (s dng), carryin ca bit 31 bng 0
Xy ra overflow: bit 31 bng 1 (s }m), kt qu sai du, carry in ca bit 31
bng 1
Carry out ca bit 31 lun bng 0
+ Cng 2 s }m:
Khng xy ra overflow: bit 31 bng 1 (s }m), carryin ca bit 31 bng 1
Xy ra overflow: bit 31 bng 0 (s dng), kt qu sai du, carryin ca bit 31
phi bng 0
Carryout ca bit 31 lun bng 1
+ Cng hai s tr|i du khng th vt qu| gii hn php tnh nn khng xy ra
coverflow
- i vi php tr: s b tr l{ s dng v{ s tr l{ s }m, kt qu l{ s }m hoc
s b tr l{ s }m v{ s tr l{ s dng, kt qu l{ s dng.
+ S b tr l{ s dng v{ s tr l{ s }m:
Khng xy ra overflow: bit 31 bng 0 (s dng), carryin ca bit 31 bng 1
Xy ra overflow: bit 31 bng 1 (s }m), kt qu sai du, carryin ca bit 31
bng 0
-

Nhm 14A 08DT1

10

Lab 2 Cu trc my tnh

MIPS ALU

Carryout ca bit 31 lun bng 1


+ S b tr l{ s }m, s tr l{ s dng:
Khng xy ra overflow: bit 31 bng 1 (s }m), carryin ca bit 31 bng 0
Xy ra overflow: bit 31 bng 0 (s dng), kt qu sai du, carryin ca bit 31
phi bng 1
Carryout ca bit 31 lun bng 0
+ Trng hp s b tr v{ s tr cng du khng th vt qu| gii hn php tnh
nn khng xy ra overflow
- V vy, ta c th ph|t hin overflow bng c|ch so s|nh carryin v{ carryout ca
bit th 31, nu tr|i du th xy ra overflow.
- Xt bng sau:

Vy:
Carryin Carryout Overflow
0
0
0
0
1
1
1
0
1
1
1
0

Overflow = CAddOut[31] xor CAddOut[30] (php cng)


Overflow = CSubOut[31] xor CSubOut[30] (php tr)
Code Verilog:
// Determine overflow, it just turns on when ALU does subtract or
add
wire [1:0]a;
and #50 and0(a[0],(~ALUcontrol[1]),ovflow1);
and #50 and1(a[1],ALUcontrol[1],ovflow2);
or #50 or0(ovflow,a[0],a[1]);
and
#50 and2(overflow, ovflow, (~ALUcontrol[0]))

3.6. Xc nh ng ra:

Nhm 14A 08DT1

11

Lab 2 Cu trc my tnh

MIPS ALU

Sau khi c c 4 kt qu ca ADD,SUB,XOR,SLT cn c v{o 2bit iu khin ca


ALUControl x|c nh d liu n{o c a ra port ng ra.
S dng b mux 4x32 to 32 c x}y dng t 32 b mux 4 to 1

Code verilog:

/***************mux4to1**********************/
module mux4to1(f, f1, f2, f3, f4, sel);
output f;
input f1, f2, f3, f4;
input [1:0]sel;
wire [3:0]f0;
and #50 and0(f0[0],f1,(~sel[1]),(~sel[0]));
and #50 and1(f0[1],f2,(~sel[1]),sel[0]);
and #50 and2(f0[2],f3,sel[1],(~sel[0]));
and #50 and3(f0[3],f4,sel[1],sel[0]);
or #50 or0(f,f0[0],f0[1],f0[2],f0[3]);
endmodule
/*****************mux4to1 for 32 bit********************/
//f1 = Add (00) , f2 = Xor (01), f3 = Sub (10), f4 = SLT(11)
module mux4to1_32(f, f1, f2, f3, f4, sel);
output [31:0]f;
input
[31:0]f1, f2, f3, f4;
input
[1:0]sel;
mux4to1
mux4to1
mux4to1
mux4to1

mux0(f[0],
mux1(f[1],
mux2(f[2],
mux3(f[3],

f1[0],
f1[1],
f1[2],
f1[3],

f2[0],
f2[1],
f2[2],
f2[3],

f3[0],
f3[1],
f3[2],
f3[3],

f4[0],
f4[1],
f4[2],
f4[3],

sel);
sel);
sel);
sel);

mux4to1
mux4to1
mux4to1
mux4to1

mux4(f[4],
mux5(f[5],
mux6(f[6],
mux7(f[7],

f1[4],
f1[5],
f1[6],
f1[7],

f2[4],
f2[5],
f2[6],
f2[7],

f3[4],
f3[5],
f3[6],
f3[7],

f4[4],
f4[5],
f4[6],
f4[7],

sel);
sel);
sel);
sel);

Nhm 14A 08DT1

12

Lab 2 Cu trc my tnh

MIPS ALU

mux4to1
mux4to1
mux4to1
mux4to1

mux8(f[8], f1[8], f2[8], f3[8], f4[8], sel);


mux9(f[9], f1[9], f2[9], f3[9], f4[9], sel);
mux10(f[10], f1[10], f2[10], f3[10], f4[10], sel);
mux11(f[11], f1[11], f2[11], f3[11], f4[11], sel);

mux4to1
mux4to1
mux4to1
mux4to1

mux12(f[12],
mux13(f[13],
mux14(f[14],
mux15(f[15],

f1[12],
f1[13],
f1[14],
f1[15],

f2[12],
f2[13],
f2[14],
f2[15],

f3[12],
f3[13],
f3[14],
f3[15],

f4[12],
f4[13],
f4[14],
f4[15],

sel);
sel);
sel);
sel);

mux4to1
mux4to1
mux4to1
mux4to1

mux16(f[16],
mux17(f[17],
mux18(f[18],
mux19(f[19],

f1[16],
f1[17],
f1[18],
f1[19],

f2[16],
f2[17],
f2[18],
f2[19],

f3[16],
f3[17],
f3[18],
f3[19],

f4[16],
f4[17],
f4[18],
f4[19],

sel);
sel);
sel);
sel);

mux4to1
mux4to1
mux4to1
mux4to1

mux20(f[20],
mux21(f[21],
mux22(f[22],
mux23(f[23],

f1[20],
f1[21],
f1[22],
f1[23],

f2[20],
f2[21],
f2[22],
f2[23],

f3[20],
f3[21],
f3[22],
f3[23],

f4[20],
f4[21],
f4[22],
f4[23],

sel);
sel);
sel);
sel);

mux4to1
mux4to1
mux4to1
mux4to1

mux24(f[24],
mux25(f[25],
mux26(f[26],
mux27(f[27],

f1[24],
f1[25],
f1[26],
f1[27],

f2[24],
f2[25],
f2[26],
f2[27],

f3[24],
f3[25],
f3[26],
f3[27],

f4[24],
f4[25],
f4[26],
f4[27],

sel);
sel);
sel);
sel);

mux4to1 mux28(f[28],
mux4to1 mux29(f[29],
mux4to1 mux30(f[30],
mux4to1 mux31(f[31],
endmodule

f1[28],
f1[29],
f1[30],
f1[31],

f2[28],
f2[29],
f2[30],
f2[31],

f3[28],
f3[29],
f3[30],
f3[31],

f4[28],
f4[29],
f4[30],
f4[31],

sel);
sel);
sel);
sel);

3.7. ALU 32 bit


- Kt hp c|c module ~ vit c|c phn trc li, ta x}y dng c 1 b MIPS
ALU vi cu trc, chc nng nh ~ gii thiu:
//======================== ALU for 32 bit =======================//
module
alu(Output, zero, negative, overflow, CarryOut, BussA,
BussB, ALUcontrol);
output
[31:0]Output;
output
zero, negative, overflow, CarryOut;
input [31:0]BussA, BussB;
input [1:0] ALUcontrol;
wire
wire
wire
wire
wire

[31:0]sum,sub;
ovflow1,ovflow,ovflow2;
[31:0]SLT;
[31:0]Xor;
carryout1,carryout2;

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add32bit
sub32bit
SLT32bit
xor32bit

MIPS ALU

add0(sum,carryout1,BussA,BussB,ovflow1);
sub0(sub,carryout2,BussA,BussB,ovflow2);
slt0(SLT,BussA,BussB);
xor32(Xor,BussA,BussB);

// Determine overflow, it just turns on when ALU does subtract or add


wire [1:0]a;
and #50 and0(a[0],(~ALUcontrol[1]),ovflow1);
and #50
and1(a[1],ALUcontrol[1],ovflow2);
or #50 or0(ovflow,a[0],a[1]);
and #50 and2(overflow, ovflow, (~ALUcontrol[0]));
//Determine Out
//f1 = Add (00) , f2 = XOR (01), f3 = SUB ( 10), f4 = SLT(11)
mux4to1_32 mymux(Output,sum,Xor,sub,SLT, ALUcontrol);
// Determine negative flag
assign negative = Output[31];
//Determine zero flag
wire
term01,term02,term03,term04,term05,term06,term07,term08,term11,term12
;
or
#50 or01(term01, Output[0], Output[1], Output[2], Output[3]);
or
#50 or02(term02, Output[4], Output[5], Output[6], Output[7]);
or
#50 or03(term03, Output[8], Output[9], Output[10], Output[11]);
or
#50 or04(term04, Output[12], Output[13], Output[14],
Output[15]);
or
#50 or05(term05,
Output[19]);
or
#50 or06(term06,
Output[23]);
or
#50 or07(term07,
Output[27]);
or
#50 or08(term08,
Output[31]);
or
or
nor

Output[16], Output[17], Output[18],


Output[20], Output[21], Output[22],
Output[24], Output[25], Output[26],
Output[28], Output[29], Output[30],

#50 or11(term11, term01, term02, term03, term04);


#50 or12(term12, term05, term06, term07, term08);
#50 nor0(zero, term11, term12);

//Determine carry flag, it just turns on when ALU does subtract or


add
wire [1:0]f;
and #50 and3(f[0],(~ALUcontrol[1]),carryout1);
and #50
and4(f[1],ALUcontrol[1],carryout2);
or #50 or1(carry,f[0],f[1]);
and #50 and5(CarryOut, carry, (~ALUcontrol[0]));
endmodule

KT QU M PHNG

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MIPS ALU

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Lab 2 Cu trc my tnh

MIPS ALU

4. Kim tra bng chng trnh Testbench


`timescale 1 ps / 100 fs
// If the verilog file containing your register file is
// not named "alu.v" then you will have to change
// to next line as appropriate.

module ALUStimulus();
parameter ClockDelay = 100000;
reg [31:0] BussA, BussB;
reg [1:0] ALUControl;
wire [31:0] Output;
wire zero, overflow, CarryOut, negative;
integer i;
// If your register file module is not named "alu" then you will
// have to change the following line in order to create an instance
of
// your register file. Also you must make sure that the port
declarations
// match up with the module instance in this stimulus file.
alu alu1(Output, CarryOut, zero, overflow, negative, BussA, BussB,
ALUControl);
initial
begin
$dumpfile("alustim.vcd");
$dumpvars(2,alu1);
end
initial
begin
$monitor($time, " Output=%h, CarryOut=%b, BussA=%h,
BussB=%h, ALUControl=%b, Zero=%b, Overflow=%b, Negative=%b",
Output, CarryOut, BussA, BussB, ALUControl, zero,
overflow, negative);
/* Addition unit testing */
ALUControl=00;
BussA=32'h00000DEF; BussB=32'h00000ABC; // Should output 000018AB
#(ClockDelay);
BussA=32'h00001234; BussB=32'h00000105; // Should output 00001339

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MIPS ALU

#(ClockDelay);
BussA=32'h7FFFFFFF; BussB=32'h00000001; // Should output 80000000,
overflow, negative
#(ClockDelay);
BussA=32'h8FFFFFFF; BussB=32'h80000001; // Should output
10000000,overflow,carryout
#(ClockDelay);
/* Xor unit testing */
ALUControl=01;
BussA=32'h00000DEF; BussB=32'h00000ABC; //Should output 00000753
#(ClockDelay);
BussA=32'h00001234; BussB=32'h00000105; //Should output 00001331
#(ClockDelay);
BussA=32'h80000000; BussB=32'h00000001; //Should output 80000001
#(ClockDelay);
/* Subtraction unit testing */
ALUControl=10;
BussA=32'h00000DEF; BussB=32'h00000ABC;
#(ClockDelay);
BussA=32'h00001234; BussB=32'h00000105;
#(ClockDelay);
BussA=32'h80000000; BussB=32'h00000001;
overflow
#(ClockDelay);
BussA=32'h00001234; BussB=32'h00001234;
00000000,zero
#(ClockDelay);
BussA=32'h00001234; BussB=32'h80001234;
#(ClockDelay);

// Should output 00000333


// Should output 0000112F
// Should output 7FFFFFFF,

// Should output

// Should output 80000000

/* slt unit testing */


ALUControl=11;
BussA=32'h00000DEF; BussB=32'h00000ABC; //Should output 00000000
#(ClockDelay);
BussA=32'h00001234; BussB=32'h00000105; //Should output 00000000
#(ClockDelay);
BussA=32'h8EEEEEEE; BussB=32'h12345678; //Should output 00000001
#(ClockDelay);
end
endmodule

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MIPS ALU

KT QU HIN TH TRN GTKWAVE

Nhn xt: Vi chng trnh kim tra trn th MIPS 32bits-ALU hot ng ng
vi yu cu thit k.

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