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INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

ISSN 0976 6464(Print) ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), pp. 258-264 IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2012): 3.5930 (Calculated by GISI)
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

IJECET
IAEME

LOW POWER DESIGN OF WALLANCE TREE MULTIPLIER


B.K.V.Prasad1, P.SatishKumar2, B.StephenCharles3, T.Prasad4 (ECE,KLUniversity,Vijayawada,India,Email:kali_1976@kluniversity.in) (ECE, MLRIT, Hyderabad, India, Email: satishkumar_1968@rediffmail.com) 3 (ECE,SSCET,Kurnool,Vijayawada,India,Email:bstephen_charles@rediffmail.com) 4 (ECE,KLUniversity,Vijayawada,India,Email:prasadtgp@kluniversity.in)
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ABSTRACT Multipliers play a key role in the high performance digital systems. Design considerations of multipliers include the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them, making them suitable for various compact high speed, low power VLSI implementations. However area and speed are two conflicting constraints and improving speed results always in larger areas. The parallel multipliers does the computations using lesser iterative steps and hence use lesser adders resulting in lesser space as compared to the serial multipliers. A Wallace tree multiplier is a parallel multiplier and uses the carry save addition algorithm to reduce the latency. This work aims at further reduction of latency and power consumption by using the 4:2 & 5:2 compressors. Keywords: Compressors, Low power Design,Latency,Power Consumption,Wallance Tree.
1.

INTRODUCTION

Multipliers are key components of many high performance systems such as FIR filters, Microprocessors, Digital Signal Processors, etc. A systems performance is generally determined by the performance of the multiplier as the multiplier is generally the slowest element in the system and generally consumes more area and power and long latency. Therefore low-power multiplier design has been an important part in the low- power VLSI system design. In digital CMOS design, the well-known power-delay product is commonly used to assess the merits of designs. In a sense, this can be shown as power delay = (energy/delay) delay = energy, which implies delay is irrelevant. Multiplication consists of three steps: generation of partial products (PPG), reduction of partial products (PPR) and finally carry-propagate addition (CPA). In general there are sequential and
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

combinational multiplier implementations. Different multiplication algorithms vary in the approaches of PPG, PPR, and CPA. For PPG, AND gates are used. For PPR, two alternatives exist: reduction by rows , performed by an array of adders, and reduction by columns, performed by an array of counters. The final CPA requires a fast adder scheme because it is on the critical path. In some cases, final CPA is postponed if it is advantageous to keep redundant results from PPG for further arithmetic operations. The rapid growth in technology led to more and more sophisticated signal processing systems being implemented on a VLSI chip. These signal processing applications not only demand great computational capacity but also consume considerable amount of energy. While performance and Area remain to be the two major design tools, power consumption has become a critical concern in todays VLSI system design. The need for low-power VLSI system arises from two main reasons Firstly, with the steady growth of operating frequency and processing capacity per chip, large currents have to be delivered and the heat generated must be removed by proper cooling techniques. Secondly, battery life in portable electronic devices is limited and low power design directly leads to prolonged operation time. Extensive work is being carried out on lowpower multipliers at technological, physical, circuit and logic levels and as a result, several parallel multipliers are designed with different area-speed constraints. The basic motive of this project is to study and develop an Efficient, Fast and Low Power Multiplier with main focus on ADDERS. The Wallance Tree multiplier is taken as a case study and efforts are made to reduce the power consumption by using 4:2 & 5:2 compressors.
2.

DESIGN METHODOLOGY

The complexity of VLSIs being designed and used today is very high and requires efficient design automation. The steady reduction in feature size and hence increase in the speed of operation as well as gate or transistor density are determining the success rate of the designed VLSI Chip. Steady improvement in the predictability of circuit behavior, increase in the variety and size of software tools for VLSI design have resulted in the proliferation of approaches to VLSI design. The aim is more to bring out the role of EDA Tools ie Tanner Tools and T spice simulator in the design process. An abstraction based model is the basis of the automated design.
3.

MULTIPLIER Conventional Wallace Tree Logic

3.1

Figure 1: Dot Diagram of Conventional Wallace Multiplier


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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

It involves several stages of reduction of partial products by using Full adders and half adders as shown in Fig.1. .For example consider 8*8 multiplier, firstly 8 partial products are generated and these are reduced by conventional logic as described below.Step1: The first three lines and the second three lines of 8 partial product lines is given to full adders which will generate two bits each, of which one is of same weight (sum) and the other is of higher weight (carry).Step2: Arrange the positions of bits basing on their weights which will generate six intermediate partial product lines, out of them upper three are given to full adders and lower three are given to another full adder.Step3: Arrange the bits according to their weights which will generate four intermediate lines and upper three are given to full adder which will give two lines.Step4: Remaining three lines are given to full adder which will produce two lines which will be given to a final carry look ahead adder to generate final product output. The implementation of conventional wallance tree multiplier architecture using S-EDIT is shown in Fig.2.

Figure 2: Schematic Diagram of Conventional Wallace Tree Multiplier 3.2 Novel Logic of wallance tree multiplier Instead of using only the full adders and half adders, the Novel logic uses the compressors which will speed up the summation in general and multiplication in particular. The number of stages required for multiplication can be reduced and hence Novel logic will be faster compared to the conventional logic.The dot diagram representation of the Novel logic is shown in Fig.3 which involves only two stages of reduction to generate final two lines of partial product stages which will be given to a final adder to generate the final product output.

Figure .3: Dot Diagram of Novel Wallace Multiplier


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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

The implementation of Novel wallance tree multiplier architecture using S-EDIT is shown in figure .4

Figure .4: Schematic Diagram of novel Wallace Tree Multiplier 3:2 Compressors The 3:2 Compressor sums three one-bit inputs, and returns the result as a single two-bit number. It maps 8 input values to 4 output values. Thus, for example, a binary input of 101 results in an output of 1+0+1=10 (decimal number '2'). The carry-out represents bit one of the results, while the sum represents bit zero. Fig.5 shows the block diagram of 3:2 compressor. 3.3

Figure 5: High Level View of the 3:2 Compressor The design of 3:2 Compressor is simple and its truth table is shown in Table .1. Table .1: Truth table for the 3:2 Compressor
A 0 0 0 0 1 1 1 1 Inputs B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 261 Sum 0 1 1 0 1 0 0 1 Carry 0 0 0 1 0 1 1 1

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

The use of two full adders in a chain would involve a latency of 4. On the other hand, the use of 4:2 compressor reduces the latency to 3. Hence, two full adders as shown in Fig 6(a) can be replaced by a single 4:2 compressor as shown in Fig.6(b).

Figure .6(a) Addition of five bits using Full adders

Figure. 6 (b) Architecture of 4:2 compressor

The equations governing the outputs of the 4:2 compressor architecture is shown below.

4.

RESULTS AND DISCUSSION

In this section, the novel and conventional architectures are compared. The number of devices, counts and total nodes are shown in figure 5.4. Figure 5.5 shows the comparison of time taken for different multiplications. In case of 8*8 multiplication, the conventional logic takes a delay of 10.64 seconds while the novel logic takes only 8.35 seconds. A 21.5% reduction in the delay has been achieved through the novel logic. Figure 5.6 shows the power consumption for different multiplications at a constant voltage of 5V. The power consumption of the Novel Wallace tree multiplier circuit is found to be 31.44% less compared to conventional Wallace multiplier in case of 8*8 multiplication 4.1 Simulation Results sThe simulation results of the conventional and Novel 8*8wallance tree multipliers gives the same functionality as shown in Fig.7 & Fig.8.The Fig.9,Fig.10,Fig.11 shows the comparison of area,delay and power.
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

Figure .7: output of wallance tree multiplier

Figure.8: output of Novel wallance tree multiplier

Figure.9: Comparison of nodes and devices

Figure.10 Comparison of delays

Figure.11: Comparison of power consumption

5.

CONCLUSION

The results show that parallel multipliers consume less power and area when compared to serial multipliers and hence the system performance increases by using these multipliers. The novel Wallace tree multiplier consumes less power and time delay when compared to the conventional Wallace tree multiplier. The novel architecture requires less hardware circuitry compared to that of conventional Wallace tree multiplier and hence it costs less and easily realizable.This multiplier can be extended for higher bits of multiplication and the computation time and power can be studied by implementing the novel architecture using CMOS transmission gate logic or pass transistor logic.

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

REFERENCES [1] A Novel Low Power and High Speed Wallace Tree Multiplier for RISC Processor C.Vinoth, V. S. Kanchana Bhaaskaran, B. Brindha, S. Sakthikumaran, V. Kavinilavu, B. Bhaskar, M.Kanagasabapathy and B.Sharath published in Electronics Computer Technology (ICECT), 2011 3rd International Conference on 8-10 April 2011 pp 330 334. [2]List I. Abdellatif, E. Mohamed, Low-Power Digital VLSI Design,Circuits and Systems, Kluwer Academic Publishers, 1995. [3] H. Neil. Weste and Kamran Eshraghian, Principles of CMOS VLSI design-A Systems Perspective, Pearson Edition Pvt Ltd. 3rd edition, 2005. [4]Sreehari Veeramachaneni, Kirthi M, Krishna Lingamneni Avinash Sreekanth Reddy Puppala M.B. Srinivas, Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors, 20th International Conference on VLSI Design, Jan 2007, Pp. 324-329. [5]K. Prasad and K. K. Parhi, Low-power 4-2 and 5-2 compressors, in Proc. of the 35th Asilomar Conf. on Signals, Systems and Computers, 2001, Vol. 1, pp. 129133. [6]Perneti Balasreekanth Reddy and V. S. Kanchana Bhaaskaran,Design of Adiabatic Tree Adder Structures for Low Power, International Conference on Embedded Systems (ICES 2010) organized by CIT, Coimbatore and Oklohoma State University, 14-16 July 2010

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