INTERNATIONAL JOURNAL OF ELECTRONICS AND International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976

6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 6464(Print) ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), pp. 147-152 IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2012): 3.5930 (Calculated by GISI) www.jifactor.com

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IAEME

DESIGN AND SIMULATION OF HIGH SPEED CMOS DIFFERENTIAL CURRENT SENSING COMPARATOR IN 0.35m AND 0.25m TECHNOLOGIES
1

Dhanisha N. Kapadia1, Priyesh P. Gandhi2 (E.C.Dept, L.C. Institute of Technology, Bhandu, INDIA,dhally_007@yahoo.co.in) 2 (E.C.Dept, L.C. Institute of Technology, Bhandu, INDIA,priyesh.gandhi@lcit.org)

ABSTRACT
This paper presents various analysis of different characteristics of Differential current sensing comparator along with the buffer stage. Different characteristics of comparator such as propagation delay, speed, power dissipation, input common mode range, offset has been carried out in two different technologies 0.35um and 0.25um . The supply voltage is kept at 3v, 2.5v for 0.35um and 0.25um respectively.

Keywords: ADC, Buffer, Latch comparator, Current sensing comparator.

I. INTRODUCTION

A comparator can be defined as the circuit that compares one analog signal with another analog signal or reference signal and gives the output in binary form as either logic0 or logic1 based on the comparison. The application of the comparator lies in ADC, memory sensing elements etc. Mostly, it is widely used in analog to digital converters. It is also known as 1bit ADC. For designing any comparators various specifications needs to be considered such as propagation delay, speed, power dissipation, offset voltage, input common mode range. The main advantage of using dynamic latch comparator is the reduction of silicon are on the chip by replacing traditional preamplifiers [1][2].Another advantage of dynamic latch comparator lies in less power dissipation as compared to preamplifiers stage based comparators. This paper is focused on Differential current sensing comparator which is a dynamic latch comparator. II. DIFFERENTIAL CURRENT SENSING COMPARATOR AND BUFFER STAGE

2.1 Differential Current Sensing Comparator The schematic of the differential current sensing comparator is as shown in fig.1. Whenever the Clk signal goes low, the circuit enters in regenerative mode. Transistor M12 is on and M7 is off. When values of both the outputs Out+ and Out- increases above threshold voltage of
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

nMOS M5 and M6, both will start conducting which will connect the outputs with comparing circuit at the input side. It consumes more power because unless and until final state is reached both the outputs have to drive common mode currents. The comparing circuit used at the input side consisting of transistors M1, M2, M3 and M4 are used to transfer the difference of the input voltage into differential currents. During reset interval, a pass transistor M7 is used to connect both the outputs together

Fig. 1. Differential current sensing comparator[3] 2.2 The Buffer Stage

Fig.2 The Output Buffer Circuit [4] The schematic of output buffer circuit used in the comparator is shown in figure 2[4]. The output buffer stage is also known as post amplifier. This circuit is self biasing differential amplifier which has differential inputs as Vout+ & Vout- and does not have any slew rate limitations. It is also useful in giving the output in proper shape.
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

III.

DESIGNING OF COMPARATOR

Fig.3 Design of Comparator The circuit diagram of Differential current sensing comparator along with the buffer stage is as shown in fig.3. The two outputs Out+ and Out- of differential current sensing comparator are being converted into single output with the output buffer circuit so that various analysis can be carried out. Table I given below shows different widths of the transistor to be used according to the chosen technology. The length for the transistor is 0.35um and 0.25um respectively for 0.35u and 0.25um technology. Table 1. CMOS Transistor widths for different technologies
Transistor M1,M2,M3,M4,M9 M5,M6,M7,M8,M14,M16,M18 M10,M11,M13,M15,M17 M12 Technology 0.35um 0.25um 5.5 5 4.5 4 9 8 11 10

IV.

SIMULATED RESULTS

The simulated results are obtained for two different technologies 0.35um and 0.25um . In table II, different voltage values are given for supply voltage VDD and VSS, reference voltage Vref+ and Vref-, input voltage Vin+ and Vin-.

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

Table2. CMOS Transistor widths for different technologies Voltage Terminals Technology

0.35um Vdd Vss Clkb Vin+ VinVref+ Vref3v -3v -3v 3v -3v 1.5v -1.5v

0.25um 2.5v -2.5v -2.5v 2.5v -2.5v 1.25v -1.25

4.1 Simulated Results in 0.35um Technology

Fig.4 Input as sine wave

Fig. 5 Transient Response

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

Fig.6 Offset Voltage 4.2 Simulated Waveforms in 0.25um Technology

Fig. 7 Input Common Mode Range

Fig.8 Input as sine wave

Fig. 9 Transient Response

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print), ISSN 0976 6472(Online) Volume 3, Issue 3, October- December (2012), IAEME

Fig. 10 Offset Voltage

Fig. 11 Input Common Mode Range

V. CONCLUSION In this paper, simulated results are presented for the comparator for two different technologies, 0.35um and 0.25unm. The summary of the comparison for the Differential current sensing comparator in both the technologies is given in the table III. TABLE III Different measured parameter values for different Technologies
Parameters Propagation Delay(ns) Speed(GHz) Offset(v) ICMR(v) Power Dissipation(mV) Technology 0.35um 0.25um 0.184 0.15 5.43 6.67 1.55 1.59 -2.6 to 1.11 -2.26 to 0.09 20.6 12.6

REFERENCES [1] P. Uthaichana and E. Leelarasmee, "Low Power CMOS Dynamic Latch Comparators," IEEE, pp. 605-608, 2003. [2] Z. Huang and P. Zhong, "An Adaptive Analog-to-Digital Converter Based on Low-Power Dynamic Latch Comparator," IEEE conference, p. 6pp, 2005. [3] Christopher J. Lindsley A Nano-Power Wake-Up Circuit for RF Energy Harvesting Wireless Sensor Networks , M.S. thesis, Dept. Electrical & computer. Eng., Oregon State University 2008. [4] Priyesh P. Gandhi Design & Simulation of Low Power High Speed CMOS Comparator in Deep Sub-micron Technology, M.Tech thesis, Dept. of electronics & communication Eng. Nirma University, 2010.

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