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Cc bi tp VHDL

Hiut_HY ^_^
Bi 1: mch so snh 4 bit:
+m t:
-mch gm c 2 u vo l a,b v 3 u ra l y1,y2,y3. vi mi
u vo cha 4bit. mch s thc hin so snh gi tr ca 2 u vo
a v b v s hin th ra ti cc u ra y. u ra y hin th gi tr
logic 1 v logic 0.
+chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity sosanh is
Port (a,b: in std_logic_vector (3 downto 0);
Y1: out std_logic;
Y2:out std_logic;
Y3: out std_logic);
End sosanh;
Architecture Behavioral of sosanh is
Begin
Process(a,b)
Begin
If (a>b) then y1<=1;
Elsif (y1=0);
End if;
If (a<b) then y2=1;
Elsif (y2=0);
End if;
If (a=b) then y3=1;
Elsif (y3=0);
End if;
End process;
End Behavioral;

Bi 2: Mch chia tn 16:


+m t hot ng:
-mch chia tn 16 gm c u vo clock & reset,v 1 u ra out.
-Nhng thc cht ca mch chia tn 16 th n c cu to gm c
mch chia tn 2,4,8,16 v vy ta cn khai bo thm cc tn hiu:
div2.div4,div8 & div16.
-tn hiu vo ca b div2 l clock & reset; ca div4 l u ra ca b
div2 & reset; ca div8 l u ra ca b div4 & reset; cui cng l b
div16 l u ra ca b div8 & reset. T ly tn hiu ra l t b div16.
+ch ng trnh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity Div16 is
Port (ck: in std_logic;
Reset: in std_logic;
Y: out std_logic);
End div16;
Architecture Behavioral of Div16 is
Signal div2,div4,div8,div16: std_logic;
Begin
Process(ck,reset,div2,div4,div8)
Begin
If (reset=1) then div2<=0;
Elsif (ckevent and ck=1) then div2<= not div2;
End if;
If (reset=1) then div4=0;
Elsif (div2event and div2=1) then div4= not div4;
End if;
If (reset=1) then div8=0;
Elsif (div4event and div4=1) then div8= not div8;
End if;
If (reset=1) then div16=0;
Elsif (div8event and div8=1) then div16= not div16;
End if;
If (reset=1) then y<=0;
Elsif (ckevent and ck=1) then y<=div16;
End if;
End process;
End Behavioral;

Bi 3: B m ko ng b,thit k b m li s dng trig T:


+m t hot ng:
-mch m ko ng b gm c 2 u vo l clock & reset v c 4 u ra
t count(0) n count(3).
-khi cha c tn hiu vo th ck=0 v khi count(0)=0; v khi c tn
hiu vo th ck s thay i t 0 ln 1 v lc ny count(0) cng s thay i
v count(0)= not count(0). Tng t vi cc b count(1),count(2) v
count(3).
-nhng u vo ca count(0) l clock & reset,ca count(1) l u ra ca
count(0) & reset,ca count(2) l u ra ca count(1) & reset,ca count(3)
l u ra ca count(2) v reset.
+chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity dem_dongbo is
Port (ck:in std_logic;
Reset:in std_logic;
Count: inout std_logic_vector(3 downto 0));
End dem_dongbo;
Architecture Behavioral of dem_dongbo is
Begin
Process (ck,reset.count)
Begin
If (reset=1) then count<=0000;
Elsif (ckevent and ck=1) then count(0)<= not count(0);
End if;
If (count(0)event and count(0)=1) then count(1)= not count(1);
End if;
If (count(1)event and count(1)=1) then count(2)= not count(2);
End if;
If (count(2)event and count(2)=1) then count(3)= not count(3);
End if;
End if;
End process;
End Behavioral;

Bi 4: B cht 4bit(hay thanh ghi 4 bit):


+m t hot ng:
-b cht 4 bit :gn c u vo Din,reset v clock v 1 u ra
Dout. u v Din & u ra Dout u cha 4 bit.
-khi reset=1 th u ra s k c tn hiu. Sau khi ta thay i
gi tr ca xung clock th u ra bt u c tn hiu v
Dout=Din.
+chng trnh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity bochot_4bit is
Port (Din:in std_logic_vector (3 downto 0);
Ck,R: in std_logic;
Dout: out std_logic_vector(3 downto 0));
End bochot_4bit;
Architecture behavioral of bochot_4bit is
Begin
Process(ck,R)
Begin
If (R=1) then Dout <=0000;
Elsif (ckevent and ck=1) then Dout<= Din;
End if;
End process;
End Behavioral;

Bi 5: Mch gii m BCD 4bit sang led 7 thanh k chung:


+m t hot ng:
-mch gm c 3 u vo l Din,ck 7 reset v 1 u ra
Dout. u vo Din cha 4 bit v u ra Dout cha 7
bit. Khi reset=1 th u ra s ko c tn hiu,kh thay
i gi tr ca reset v ck th c tn hiu ti u ra.
+chng trnh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity BCD_led7 is
Port (Din: in std_logic_vector(3 downto 0);
Ck: in std_logic;
Reset: in std_logic;
Dout: out std_logic_vector(6 downto 0));
End BCD_led7;
Architecture Behavioral of BCD_led7 is
Begin
Process (ck,reset,Din)
Begin
If reset=1 then Dout<=0000000;
Elsif (ckevent and ck=1) then
Case Din is
when "0000" => Dout <= "1111110"; --0
when "0001" => Dout <= "0110000"; --1
when "0010" => Dout <= "1101101"; --2
when "0011" => Dout <= "1111001"; --3
when "0100" => Dout <= "0111011"; --4
when "0101" => Dout <= "1011011"; --5
when "0110" => Dout <= "1011111"; --6
when "0111" => Dout <= "1110000"; --7
when "1000" => Dout <= "1111111"; --8
when "1001" => Dout <= "1111011"; --9
when others => Dout <= null;
End case;
End if;
End process;
End Behavioral;

s
0
1
2
3
4
5
6
7
8
9
10->15

Led 7
1111110
0110000
1101101
1111001
0111011
1011011
1011111
1110000
1111111
1111011
0000000

Bi 6: Mch m ho 8:3 s dng case:


+m t hot ng:
-mch gm c u vo input cha 8 bit v u ra output
cha 3 bit.
Khi ta thay i gi tr ti u vo ca mch th mch s
m ho cho ta cc ra gi tr ra tng ng ti u ra.
+chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity mahoa_83 is
Port(input:in std_logic_vector(7 downto 0);
Output : out std_logic_vector(2 downto 0));
End mahoa_83;
Architecture Behavioral of mahoa_83 is
Begin
Process(input)
Begin
Case input is
When 00000001 => output<=000;
When 00000010 => output<=001;
When 00000100 => output<=010;
When 00001000 => output<=011;
When 00010000 => output<=100;
When 00100000 => output<=101;
When 01000000 => output<=110;
When 10000000 => output<=111;
When others => output<=null;
End case;
End process;
End behavioral;

A
7
0
0
0
0
0
0
0
1

A
6
0
0
0
0
0
0
1
0

A
5
0
0
0
0
0
1
0
0

A
4
0
0
0
0
1
0
0
0

A
3
0
0
0
1
0
0
0
0

A
2
0
0
1
0
0
0
0
0

A
1
0
1
0
0
0
0
0
0

A
0
1
0
0
0
0
0
0
0

Y
2
0
0
0
0
1
1
1
1

Y
1
0
0
1
1
0
0
1
1

Y
0
0
1
0
1
0
1
0
1

Bi 7: B ghp knh 8:1:


+m t hot ng:
b ghp knh 8 li vo 1 li ra gm c 8 li vo t x0 n
x7,vi mi li vo l 8 bt x0(7:0) n x7(7:0),1 li ra y(7:0).
S(2:0) l cc u vo iu khin, thay i ln lt t
x0(7:0) n x7(7:0)nphi c u vo iu khin. Vy i vi
mch ghp knh 8 li vo 1 li ra cn u vo iu khin l s.
+ cc Chng trnh:
1.s dng if:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_81 is
Port (s : in std_logic_vector(2 downto 0);
X0,x1,x2,x3.x4.x5,x6,x7: in std_logic_vector (7 downto
0);
y : out std_logic_vector (7 downto 0));
end Mux_81;
architecture Behavioral of Mux_81 is
Begin
Process(s)
If (s=000) then y<= x0;
Elsif (s=001) then y<=x1;
Elsif (s=010) then y<=x2;
Elsif (s=011) then y<=x3;
Elsif (s=100) then y<=x4;
Elsif (s=101) then y<=x5;
Elsif (s=110) then y<=x6;
Else y<=x7;
End if;
End process;
End Behavioral;

bng chn l:
s
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

y
X0
X1
X2
X3
X4
X5
X6
X7

2. s dng case
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_81 is
Port (s : in std_logic_vector(2 downto 0);
X0,x1,x2,x3.x4.x5,x6,x7: in std_logic_vector (7 downto
0);
y : out std_logic_vector (7 downto 0));
end Mux_81;
architecture Behavioral of Mux_81 is
Begin
Process(s)
Case input is
When 000 => y<=x0;
When 001 => y<=x1;
When 010 => y<=x2;
When 011 => y<=x3;
When 100 => y<=x4;
When 101 => y<=x5;
When 110 => y<=x6;
When 111 => y<=x7;
End case;
End process;
End behavioral;

Bi 8: thit k mch m ho 4 ng sang 2 ng vi ng vo tch hp


mc cao, s dng pht biu case.
+m t:
-mch gm c 4 u vo t I0 n I3 v c 2 u ra l Q0 &
Q1. vi mi gi ti u vo th mch s m ho cho ta 1 gi tr
ti u ra ca mch.
+chng trnh:
library IEEE;
bng chn l
use IEEE.STD_LOGIC_1164.ALL;
entity mahoa_42 is
Ng vo
Port (I : in std_logic_vector(3 downto 0);
I3 I2 I1 I0
Q : out std_logic_vector (1 downto 0));
0 0 0 1
end mahoa_42;
0 0 1 0
architecture Behavioral of mahoa_42 is
0 1 0 0
Begin
1 0 0 0
Process(I)
Begin
Case I is
When 0001 => Q<=00;
When 0010 => Q<=01;
When 0100 => Q<=10;
When 1000 => Q<=11;
When others => null;
End case;
End process;
End behavioral;

Ng ra
Q1 Q0
0 0
0 1
1 0
1 1

Bi 9: Mch m ho 8:3
+m t hot ng:
Mch m ho dng bin i d liu ri rc
thnh dng nh phn. Mch m ho c 2n hoc t
hn ng vo s m ho d liu ng vo cung
cp n ng ra c m ho. Cn gi nh ch c 1
ng vo tch cc (1) 1 thi im cho trc,
nu ko ng ra s ko c gi tr xc nh no &
mch tr nn v ngha.
+Cc chng trnh:
1.s dng if:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mahoa_83 is
Port (A : in std_logic_vector(7 downto 0);
y : out std_logic_vector (2 downto 0));
end mahoa_83;
architecture Behavioral of mahoa_83 is
Begin
Process(A)
Begin
If (A=00000001) then y<=000;
elsIf (A=00000010) then y<=001;
elsIf (A=00000100) then y<=010;
elsIf (A=00001000) then y<=011;
elsIf (A=00010000) then y<=100;
elsIf (A=00100000) then y<=101;
elsIf (A=01000000) then y<=110;
elsIf (A=10000000) then y<=111;
else y<=xxx;
End if;
End process;
End behavioral;
2.s dng pht biu case:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mahoa_83 is
Port (A : in std_logic_vector(7 downto 0);
y : out std_logic_vector (2 downto 0));

A A AA A AA A Y Y Y
7 6 5 4 3 2 1 0 2 1 0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
end mahoa_83;
architecture Behavioral of mahoa_83 is
Begin
Case A is
When 00000001 => y<=000;
When 00000010 => y<=001;
When 00000100 => y<=010;
When 00001000 => y<=011;
When 00010000 => y<=100;
When 00100000 => y<=101;
When 01000000 => y<=110;
When 10000000 => y<=111;
When others =>y<=null;
End case;
End process;
End behavioral;

Bi 10: Mch m ho u tin:


+M t hot ng:
nu c 2 hay nhiu ng vo mc logic tch cc
(1),ng vo c mc u tin cao nht s c u
tin hn v gi tr m ho c th ca ng vo ny
s xut hin cc ng ra.
+ Cc chng trnh:
1.s dng pht biu if:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity 83_uutien is
A A A A A A A A Y Y Y valid
Port (A : in std_logic_vector(7 downto 0);
7 6 5 4 3 2 1 0 2 1 0
y : out std_logic_vector (2 downto 0));
0 0 0 0 0 0 0 1 0 0 0 1
end 83_uutien;
0 0 0 0 0 0 1 X 0 0 1 1
architecture logic of 83_uutien is
0 0 0 0 0 1 X X 0 1 0 1
Begin
0 0 0 0 1 XX X 0 1 1 1
Process(A)
0 0 0 1 X XX X 1 0 0 1
Begin
0 0 1 X X XX X 1 0 1 1
If (A(7)=1) then y<=111;
0 1 XX X XX X 1 1 0 1
elsIf (A(6)=1) then y<=110;
1 X XX X XX X 1 1 1 1
elsIf (A(5)=1) then y<=101;
0 0 0 0 0 0 0 0 X Xx 0
elsIf (A(4)=1)then y<=110;
Begin
elsIf (A(3)=1) then y<=100;
Process(A)
elsIf (A(2)=1) then y<=011;
Begin
elsIf (A(1)=1) then y<=001;
A_int:=to_integer (A); Valid <=1;
elsIf (A(0)=1) then y<=000;
Case (A) is
else valid<=0;
When 128 to 255 => y<=111;
y<=xxx;
When 64 to 127 => y<=110;
End if;
When 32 to 63 => y<=101;
End process;
When 16 to 31 => y<=100;
End logic;
When 8 to 15 => y<=011;
2.Pht biu case:
When 4 to 7 => y<=010;
library IEEE;
When 2 to 3 => y<=001;
use IEEE.STD_LOGIC_1164.ALL;
When 1 => y<=000;
entity 83_uutien is
When others =>y<=valid; Y<=xxx;
Port (A : in std_logic_vector(7 downto 0);
End case;
y : out std_logic_vector (2 downto 0));
End process;
end 83_uutien;
End logic;
architecture logic of 83_uutien is

Bi 11: Mch gii m 3:8:


+m t hot ng:
Cc mch gii m c s dng gii m d
s :
liu,d liu ny c m ho trc y bng cch dng
dng m ho nh phn hoc c th 1 dng m ho
khc. 1 m n bit c th biu din n 2n bit phn bit
ca thng tin m ho, do vy 1 mch gii m vi n
ng vo c th gii m n 2n ng ra.
+ Cc phng trnh:
1.s dng if:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
bng chn l:
entity giaima_38 is
A A AY Y YY Y Y Y Y
Port (A : in std_logic_vector(2 downto 0);
2 1 0 7 6 5 4 3 2 1 0
y : out std_logic_vector (7 downto 0));
0 0 0 0 0 0 0 0 0 0 1
end giaima_38;
0 0 1 0 0 0 0 0 0 1 0
architecture logic of giaima_38 is
0 1 0 0 0 0 0 0 1 0 0
Begin
0 1 1 0 0 0 0 1 0 0 0
Process(A)
1 0 0 0 0 0 1 0 0 0 0
Begin
1 0 1 0 0 1 0 0 0 0 0
If (A=000) then y<=00000001;
1 1 0 0 1 0 0 0 0 0 0
elsIf (A=001) then y<=00000010;
1 1 1 1 0 0 0 0 0 0 0
elsIf (A=010) then y<=00000100;
Begin
elsIf (A=011) then y<=00001000;
Case (A) is
elsIf (A=100) then y<=00010000;
When 000 => y<=00000001;
elsIf (A=101) then y<=00100000;
When 001 => y<=00000010;
elsIf (A=110) then y<=01000000;
When 010 => y<=00000100;
else y<=10000000;
When 011 => y<=00001000;
End if;
When 100 => y<=00010000;
End process;
When 101 => y<=00100000;
End logic;
When 110 => y<=01000000;
2.s dng case:
When 111 => y<=10000000;
library IEEE;
When others => y<=null;
use IEEE.STD_LOGIC_1164.ALL;
End case;
entity giaima_38 is
End process;
Port (A : in std_logic_vector(2 downto 0);
End logic;
y : out std_logic_vector (7 downto 0));
end giaima_38;
architecture logic of giaima_38 is

Bi 12: Thit k mch a hp 4 ng vo,1 ng ra,2 ng la chn:


+m t hot ng:
-mch gm c 4 u vo t I0 n I3 v 1 u ra Q.s0,s1 l
cc u vo iu khin. thay i ln lt t I0 n I3 th
phi c iu khin,vic c thc hin bi 2 u vo iu
khin s0 & s1.
+ch ng trnh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_41 is
Port (I : in std_logic_vector(3 downto 0);
S: in std_logic_vector (1 downto 0);
Q : out std_logic);
end mux_41;
architecture Behavioral of mux_41 is
Begin
Process(I,s)
Begin
Case s is
When 00 => Q<=I0;
When 10 => Q<=I1;
When 10 => Q<=I2;
When 11 => Q<=I3;
When others => Q <=null;
End case;
End process;
End Behavioral;

S1 S0 I3
0 0 X
0 1 X
1 0 X
1 1 I3
Bng chn l

s mch

I2
X
X
I2
X

I1
X
I1
X
X

I0
I0
X
X
X

Q
I0
I1
I2
I3

Bi 13: Cc cch m t mch ghp knh 4:1, 1 bit:


+m t hot ng:
b ghp knh 4 li vo 1 li ra gm c 4 li vo
A,B,C,D,vi mi li vo l 1 bit v 1 li ra y. S1,s2
l cc u vo iu khin, thay i ln lt cc
u vo t A n D phi c iu khin, vy i vi
mch ny th cn c u vo iu khin l s1,s2.
+ cc chng trnh:
1.s dng pht biu if:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41 is
Port (A,B,C,D,s1,s2: in std_logic;
Y: out std_logic);
end Mux_41;
architecture Behavioral of Mux_41 is
Begin
Process(A,B,C,D,s1,s2)
If (s1s2=00) then y<= A;
Elsif (s1s2=01) then y<=B;
Elsif (s=10) then y<=C;
Else y<=D;
End if;
End process;
End Behavioral;
2.s dng php gn tn hiu c iu kin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41 is
Port (A,B,C,D,s1,s2: in std_logic;
Y: out std_logic);
end Mux_41;
architecture Behavioral of Mux_41 is
Begin
Y<=A When s1s2=00 else
B When s1s2=10 else
C When s1s2=10 else
Y<=D;
End behavioral;

Bng chn l:
S1
0
0
1
1

S2
0
1
0
1

A
1
0
0
0

B
0
1
0
0

C
0
0
1
0

D
0
0
0
1

Y
1
1
1
1

2.s dng pht biu case:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux_41 is
Port (A,B,C,D,s1,s2: in std_logic;
Y: out std_logic);
end Mux_41;
architecture Behavioral of Mux_41 is
Begin
Process(A,B,C,D,s1,s2)
Begin
Case s1 s2 is
When 00 => y<=A;
When 10 => y<=B;
When 10 => y<=C;
When 11 => y<=D;
End case;
End process;
End behavioral;

Bi 14: Mch cng ko y 1bit:


+m t:
-mch gm c 2 u vo l A,B v 2 u ra l Cout, sum. vi sum l tng
ca 2 u vo v Cout l bit nh.
+chng trnh
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HALF_ADD is
Port ( A,B : in STD_LOGIC;
Sum, Cout : out STD_LOGIC);
end HALF_ADD;
architecture Behavioral of HALF_ADD is
begin
Sum <= A xor B;
Cout <= A and B;
end Behavioral;

S :

bng chn l:
A B Cout Sum
0 0
0
0
0 1
0
1
1 0
0
1
1 1
1
0

Bi 11: Mch cng y 1bit:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FULL_ADD is
Port ( A,B,Cin : in STD_LOGIC;
Cout,Sum : out STD_LOGIC);
end FULL_ADD;
architecture Behavioral of FULL_ADD is
COMPONENT HALF_ADD
PORT(A : IN std_logic;
B : IN std_logic;
Sum : OUT std_logic;
Cout : OUT std_logic);
END COMPONENT;
signal AplusB,CoutHA1,CoutHA2: STD_LOGIC;
begin
HA1: HALF_ADD PORT MAP (
A => A,
B => B,
Sum => APlusB,
Cout => CoutHA1);
HA2: HALF_ADD PORT MAP(
A => AplusB,
B => Cin,
Sum => Sum,
Cout => CoutHA2);
Cout <= CoutHA1 or CoutHA2;
end Behavioral;

+m t:
-mch gm c 3 u vo A,B,Cin v 2 u
ra Cout,sum.
-vi sum l tng ca 3 u vo v Cout l
bit nh
+Bng chn l:
A B Cin Sum Cout
0 0
0
0
0
0 0
1
1
0
0 1
0
1
0
0 1
1
0
1
1 0
0
1
0
1 0
1
0
1
1 1
0
0
1
1 1
1
1
1

Bi 15: Mch ghp knh 2:1, rng 1 bit:


+ m t hot ng:
mch ghp knh c la chn 1,2 hoc nhiu tn hiu ng vo
n ng ra. Mt or nhiu tn hiu iu khin s iu khin
gi tr ca tn hiu ng vo no c truyn n ng ra. Mi
tn hiu ng vo v tn hiu ng ra c th l 1 bt n or bus
nhiu bit. Cc ng vo la chn thng c m ho nh
phn sap cho n ng vo la chn c th chn t 1 n 2n ng
vo.
+ chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity mux_21 is
Port (A,B:in std_logic;
s: in std_logic;
y: out std_logic);
End mux_21;
Architecture behavioral of mux_21 is
Begin
Process(A,B)
Begin
If (s=0) then y<=A;
Else y<=B;
End if;
End process;
End Behavioral;

bng chn l:
S
0
0
1
1

A
0
1
X
X

B
X
X
0
1

Y
0
1
0
1

Bi 16: mch gii m a ch 4bit:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity giaima_4bit is
Port (x:in integer range 0 to 15;
A,C,D: out std_logic;
B: out std_logic_vector(3 downto 0));
End giaima_4bit;
Architecture logic of giaima_4bit is
Begin
Process(x)
Begin
A<=0;
B<=(others=>0);
C<=0;
D<=0;
Case (x) is
When 0 to 3 => A<=1;
When 4 => B(0)<=1;
When 5 => B(1)<=1;
When 6 => B(2)<=1;
When 7 => B(3)<=1;
When 8 to 11 => C<=1;
When 12 to 15 => D<=1;
End case;
End process;
End logic;

Bi 17: Cng 3 trng thi:


Loi 1: s dng when:
+m t hot ng:
cng 3 trng thi c u ra output=input khi ena=0 v c
bng tr khng cao khi ena=1.
+chng trnh:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity 3trangthai is
Port (ena:in std_logic;
input:in std_logic;
output: out std_logic);
End 3trangthai;
Architecture Behavioral of 3trangthai is
Begin
Output<=input when (ena=0)
Else (others => z);
End Behavioral;
Loi 2: s dng if:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity 3trangthai is
Port (A,E: out std_logic;
y: out std_logic);
End 3trangthai;
Architecture Behavioral of 3trangthai is
Begin
If (E=0) then y=A;
Else y=z;
End Behavioral;

s :

bng chn l:
Ena In Out
0
1 1
1
Z z

S :

bng chn l:
E
0
1

A y
1 1
Z z