+ = +
=
L
T n d n v
L
T n v
n i
s o s in
L
] [ ' ] [ ] [
] [ +
(12)
=
L
T n d n v
L
T n v
L
T n v
n i
s o s o s in
L
] [ ' ] [ ] [ ] [
] [ + +
For the control objective to be achieved the
condition I
L
[n +1]= Ic has to be satised.
] [ ] [ ] [ ] [ ]) [ ( n d n v n v n v n i i
T
L
o o in L c
s
+ =
(13)
This gives:
] [
] [
1 ]) [ (
] [
] [
n v
n v
n i i
T n v
L
n d
o
in
L c
s o
+ =
(14)
If the inductor current peak at the start of nth
switching cycle is greater than i
c
then, from the
9
above d[n] equation the duty ratio is decreased
by a factor proportional to the current error i =
I
L
[n]I
c
. When this error is reduced to zero (i.e
I
L
= I
c
), d[n] simplies to (1 v
in
)/v
o
, which is
the steady state duty ratio of a boost converter.
Thus any given reference current peak can be
tracked directly using this method.
Current at the end of the nth switching cycle is
given by
L
n d T n v
L
T V
i i n i
s o s in
c L
]) [ 1 ( ] [
] 1 [
+ + A + = +
(15)
Which yields
i
L
D T n v
L
T n v
L
T n V
i i n i n i
s o s o s in
c L
A + + A = + = + A
] [ ] [ ] [
] 1 [ ] 1 [
= )) 1 ]( [ ] [ ( D n v n v
L
T
o in
s
= ]) [ ] [ ( n v n v
L
T
in in
s
(16)
Thus we obtain, 0 ] 1 [ = + A n i
Thus it is proved that the perturbation in current
dies down within one switching period thereby
achieving a deadbeat operation. Hence, the
predictive peak CPM using leading edge
modulation is stable for all values of D.
Current Control Law for Buck Mode
Derivation of the control law for the buck mode
is similar to that of the boost mode. The duty
ratio for the nth switching cycle is computed
based on the sensed inductor current
i
L
[n], output voltage v
o
[n] and the input voltage
v
in
[n] at the beginning of the nth switching
cycle. Substituting the slopes for buck converter
from Table.1 in Eqn. a) we obtain
L
T n d n v n v
L
T n d v
n i n i
s o in s o
L L
] [ ]) [ ] [ ( ] [ '
] [ ] 1 [
+ = +
(17)
Since i [n +1]= i we have,
L
T n v n d
L
T n d n v
L
T n v n d
L
T n v
n i i
s o s in s o s o
L c
] [ ] [ ] 1 [ ] [ ] [ ] [ ] [ '
] [
+
+ +
=
=
L
T n v
L
n v T n d
s o in s
] [ ] [ ] [
(18)
simplifying the above equation, we obtain the
expression for the predicted value of duty ratio
for the buck mode:
] [
] [
]] [ [
] [
] 1 [
n v
n v
n i i
T n v
L
n d
in
o
L c
s in
+ = +
(19)
A similar procedure shown for the boost
converter case can be followed for the buck
converter control law and results in stable
operation for any D. Thus the benefit of using
the PDCPM controller can achieve the benefits
of traditional CPM control but avoid the
complexity of high performance ADCs and also
without the subharmonic instabilities that are
inherent with traditional CPM control.
Buck Converter Controller Design
V
O
C
O
V
REF
PWM
Modulator
Current
Sense
V
IN
L
O
H
FB
+

i
O
i
L
Q
U
Q
L
D
V
SW
ESR
R
O
Compensator
DCR
i
C
Fig 16) Simplified Buck Converter Diagram.
10
A simplified buck converter diagram is shown
in Fig 16. Based on the steady state and
switching ripple analysis developed in a
previous section the buck converter and boost
converter plant parameters are chosen as shown
in the Table 2.
Parameter Value Comment
D
Converter Duty Cycle
VIN 100V Input Voltage
Fsw 20kHz Switching Frequency
Fsample 50kHz ADC Sample Rate
Lo 1mH Output Inductor
DCR 200mOhms Inductor Resistance
Current Gain 1A/A Current Sense Gain
Co 100uF Output Capacitor
ESR 1mOhm Capacitor Resistance
Ro 25Ohm Load Resistor
HFB 1V/V Voltage Sense Gain
Table 2) Buck and Boost Converter Parameters.
A mathematical model is derived to show the
benefits of current mode control versus voltage
mode control for the buck converter. Figure 16
is used to derive the DC and AC characteristics
of the buck converter plant, controller and
modulator. First the variables for the system are
defined as shown in Figure 17 and the reference
designators match Table 2 and Figure 16.
Fig 17) Define Buck Converter Parameters.
The procedure of inductor voltsecond balance
and capacitor chargebalance described
previously is used to find the DC and AC
characteristics of the buck converter. The
equations are shown here:
D ( ) V
in
DCR I
L
V
o
( )
1 D ( ) DCR I
L
V
o
( )
+ V
L
0
(20)
D ( ) I
L
V
o
R
o
\


.
1 D ( ) I
L
V
o
R
o
\


.
+ I
C
0
(21)
These equations are used to derive vo/d for the
duty cycle to output voltage transfer function
shown below which is the plant of the voltage
mode buck converter
v
o
d
V
in
ESR
1
s C
o
+

\


.
ESR
1
s C
o
+ DCR + s L
o
+
(
(
(
(
(
(22)
ESR is the resistance of the capacitor; DCR is
the resistance of the inductor. To demonstrate
the control challenge using voltage mode
control a simple PWM modulator is used with a
sawtooth ramp of 1V. This is used to derive the
open loop system gain to the output voltage
from the duty cycle control signal with the
modulator gain applied. The open loop gain and
phase margin are shown in Figure 18.
Fig 18) Open Loop Buck Converter with VM Control.
11
Without compensation the loop bandwidth is
~5kHz and the phase margin is 7deg. This
system is very nearly unstable due to the 
180deg phase shift due to the underdamped LC
filter. A PID controller would be needed to
boost the phase sufficiently to stabilize the loop.
To investigate the benefit of current mode
control, the transfer functions are derived
assuming a simple PI controller. The current
mode plant model is first order as described
previously and the inductor pole is essentially
removed from the transfer function. The
inductor current to output voltage transfer
function is shown below.
v
o
i
L
ESR
1
C
o
s
+
(23)
The PI parameters can be designed based on the
plant model transfer function and analysis of the
bode plot. For example the figure below shows
the open loop gain of the plant model and
modulator of the current mode buck converter.
The red dot marks the loop bandwidth where the
gain equals one. And the blue dot marks the
phase margin at that frequency.
Since the final system is digital the sdomain
results should be modified to show the phase
shift of a digital system. This can be achieved
by adding the transfer function of the ZOH and
the phase shift from the sampling nature of the
peak current mode feedback loop.
The resulting system bode plot is shown below.
The proportional gain of the compensator, Kp
can be increased to increase the loop bandwidth
until the phase margin is reduced to some
minimal value. For this design, the gain is
increased until the phase margin drops to 60deg.
Therefore analytical expressions for the Kp and
Ki of the analog compensator
H
s
K
p
K
i
s
+
(24)
Can be determined as shown in Equations (25).
2
2 1 . 0
'
1
) (
P BW I
BW
BW
P
I
P
I
I
P C
K f K
f
f
K
K
s
K
K
s
s
K
K s H
=
=
+
= + =
t
(25)
12
Choosing some parameters for a PI controller,
the open loop gain and phase margin plots are
shown in Figure 19. The gain curve is shown to
have a 20dB/dec slope over a very large
frequency range demonstrating the single pole
response characteristic of current mode control.
Therefore a simple PI controller is sufficient for
the controller.
Fig 19) Open Loop Buck Converter with CPM Control.
Based on the bode plot analysis the continuous
controller coefficients are Kp=2 and Ki=1000.
The integrator is needed to minimize steady
state error and the proportional gain is needed to
add a zero for stability and to improve transient
response.
The bilinear transformation is used to derive the
coefficients for the equivalent discrete filter
coefficients for the digital controller. The
digital controller equation is:
K
p
K
i
T
sample
2
+

\


.
z
K
i
T
sample
2
+ K
p
z 1 (26)
And Kp=2.01 and Ki=1.99. As shown in
Figure 19, this controller yields open loop
bandwidth of ~650Hz and phase margin of
~63deg.
Buck Converter Simulation Results
To simulate the regulation and voltage and
current dynamics of the buck converter design a
continuous analog switching model is built in
the SIMPLIS simulation tool and the digital
switching model is built in Matlab. The
schematics are shown in Figure 20 and 21.
13
Fig 20) SIMPLIS Schematic of Analog Buck Converter Model.
Fig 21) Matlab Schematic of Digital Buck Converter Model with
PDCPM Control.
14
The buck converter of Figure 21 output voltage
step response is shown in Figure 22. The top
waveform is the inductor current and the bottom
waveform is the output voltage stepping from
0V to 50V. There is very little overshot and the
response is stable. Figure 23 shows the step
response from 50V to 70V again showing stable
response with little overshoot. Also, note the
system does not exhibit subharmonic oscillation
even though the duty cycle is >> 50% exhibiting
the benefit of PDCPM control.
Fig 22) Buck converter step response from 0V to 50V.
Fig 23) Buck converter step response from 50V to 70V.
Figure 24 shows the load transient response and
single cycle response of PDCPM. The load step
applied is 2A and the output voltage response is
stable and well damped. Figure 25 shows a
zoom in of the transient response showing
inductor current very nearly singlecycle
response.
Fig 24) Buck converter load step response for 2A step.
Fig 25) Buck converter load step response for 2A step.
For comparison the analog controller is
simulated in SIMPLIS tool. Figure 26 shows
the open loop Bode plot for the buck converter
with a similar PI controller.
15
Fig 26) Buck converter bode plot for analog controller.
Boost Converter Controller Design
V
O
C
O
V
REF
PWM
Modulator
V
IN
L
O
H
FB
+

i
O
i
L
Q
U
Q
L
D
ESR
R
O
Compensator
DCR
i
C
Current
Sense
DVo
Fig 27) Simplified Boost Converter Diagram.
A similar design procedure is followed for the
boost converter. A simplified boost converter
diagram is shown in Fig 27. The boost
converter parameters were shown in Table 2
except the VIN will be lower than the output
voltage.
A mathematical model is derived to show the
benefits of current mode control versus voltage
mode control for the boost converter. Figure 28
is used to derive the DC and AC characteristics
of the boost converter plant, controller and
modulator. First the variables for the system are
defined as shown in Figure 28.
Fig 28) Define Boost Converter Parameters.
The procedure of inductor voltsecond balance
and capacitor chargebalance described
previously is used to find the DC and AC
characteristics of the boost converter. The
equations are shown here:
D ( ) V
in
DCR I
L
( )
1 D ( ) V
in
DCR I
L
V
o
( )
+ V
L
(26)
D ( )
V
o
R
o

\


.
1 D ( ) I
L
V
o
R
o
\


.
+ I
c
(27)
These equations are used to derive vo/d for the
duty cycle to output voltage transfer function
shown below which is the plant for the boost
converter.
v
o
d
V
o
V
o
DCR L
o
s +
( )
R
o
D 1 ( )
+
(
(
D
1
R
o
C
o
s
C
o
ESR s 1 +
+

\


.
DCR L
o
s +
( )
D 1
+ 1
(
(
(
(
(28)
To demonstrate the control challenge using voltage
mode control a simple PWM modulator is used with
a sawtooth ramp of 1V. This is used to derive the
open loop system gain to the output voltage from
the duty cycle control signal with the modulator
gain applied. The open loop gain and phase margin
are shown in Figure 29.
16
Fig 29) Open Loop Boost Converter with VM Control.
Without compensation the loop bandwidth is
~5kHz and the phase margin is 13deg. This
system is unstable due to the 180 deg phase
shift of the double pole and also the righthalf
plane zero. A complex controller would be
needed to boost the phase sufficiently to
stabilize the loop.
To investigate the benefit of current mode
control, the transfer functions are derived
assuming a simple PI controller. The current
mode plant model is first order as described
previously and the inductor pole is essentially
removed from the transfer function. The
inductor current to output voltage transfer
function is shown below. This time the
derivation includes capacitor ESR and output
load resistor for better accuracy.
v
o
i
L
ESR
1
s C
o
+

\


.
R
o
ESR
1
s C
o
+ R
o
+
(29)
Choosing some parameters for a PI controller,
the open loop gain and phase margin plots are
shown in Figure 30. The gain curve is shown to
have a 20dB/dec slope over a very large
frequency range demonstrating the single pole
response characteristic of current mode control.
Therefore a simple PI controller is sufficient for
the controller.
Fig 30) Open Loop Boost Converter with CPM Control.
The controller is designed using the bode plots.
The proportional gain can be varied until the
phase margin drops to ~60deg which is a good
tradeoff between stability and transient
response. The analog controller equation is
shown:
H
s
K
p
K
i
s
+
(30)
Based on the bode plot analysis the continuous
controller coefficients are Kp=1 and Ki=1000.
The integrator is needed to minimize steady
state error and the proportional gain is needed to
add a zero for stability and to improve transient
response.
The bilinear transformation is used to derive the
coefficients for the equivalent discrete filter
coefficients for the digital controller. The
digital controller equation is:
17
K
p
K
i
T
sample
2
+

\


.
z
K
i
T
sample
2
+ K
p
z 1 (31)
And Kp=1.01 and Ki=0.99. As shown in
Figure 19, this controller yields open loop
bandwidth of ~470Hz and phase margin of
~68deg.
Boost Converter Simulation Results
To simulate the regulation and voltage and
current dynamics of the boost converter design a
continuous analog switching model is built in
the SIMPLIS simulation tool and the digital
switching model is built in Matlab. The
schematics are shown in Figure 31 and 32.
18
Fig 31) SIMPLIS schematic of Analog Boost Converter.
Fig 32) Matlab schematic of Digital Boost Converter.
19
The boost converter of Figure 32 output voltage
step response is shown in Figure 33. The top
waveform is the inductor current and the bottom
waveform is the output voltage stepping from
0V to100V. There is a small amount of
overshoot and the response is stable. Figure 34
shows the step response from 100V to 120V
again showing stable response with little
overshoot. Also, note the system does limit the
peak current so the transition to 120V is not as
fast. This is another benefit of peak current
mode control; it is easy to limit peak current.
Fig 33) Boost converter step response from 0V to 100V.
Fig 34) Boost converter step response from 100V to 120V.
Figure 35 shows the load transient response and
single cycle response of PDCPM. The load step
applied is 2A and the output voltage response is
stable and well damped. Figure 36 shows a
zoom in of the transient response.
Fig 35) Boost converter load step response for 2A step.
Fig 36) Boost converter load step response for 2A step.
20
Experimental Setup and Results
Fig. 37) shows the experimental setup of the bi
directional buck and boost converter with a 32
bit fixed point DSP (TMS320F2812) for digital
control implementation. The inductor,
capacitors and the load bank can be seen in the
figure.
Fig 37: Experimental setup of the bidirectional buck/boost converter
The open loop results of the bidirectional
converter running in buck mode under open
loop condition are given in Fig 38. The input
voltage is 100 V and a duty cycle of 0.25 is
chosen. The corresponding output voltage,
inductor current and PWM pulse for the
MOSFET are seen in the figure. It can be seen
that the output is slightly lower than 25% due to
the drop across the diode and the inductor.
Fig 38: Open loop result in the buck mode
(Ch1: Input voltage, Ch2: Output voltage, Ch3:
PWM and Ch4: Inductor current)
The open loop results of the bidirectional
converter running in boost mode under open
loop condition are given in Fig 39 The input
voltage of 25 V is given a duty cycle of 75%.
The corresponding output voltage, PWM pulse
and the inductor current is shown in the figure.
It can be seen that the output is considerable
different from ideally expected value (of 100
V). This is due to drop across the diode and
inductance as mentioned for buck converter. But
as the current value is much higher here, the
drop is also significantly higher, making the
values move farther from the ideal.
21
Fig 39: Open loop result in the boost mode
(Ch1: Input voltage, Ch2: Output voltage, Ch3:
PWM and Ch4: Inductor current)
Issue in closed loop implementation:
A 32bit fixed point DSP processor has been
used for the control implementation. While
writing the assembly code, 12.20 format has
been chosen which allows flexibility in
representing integer values up to + 2048 from
2048, while maintaining good accuracy of
fractional part representation with 20 bits.
Based on the discussion on control
implementation in the earlier sections, the plant
parameters (V
in
, V
o
and i
L
) are sampled for the
control system only once in a switching period.
So, proper sampling of these parameters has to
be done using an ADC and fed to the controller.
But there has been an issue in making the ADC
work. The CCS compiler as such was not
showing any error but it is possible that the
sequence of initialization is faulty. However,
when the code was executed assuming certain
values for V
in
, V
o
and i
L(ref)
the duty cycle
prediction for a given current, i
L,
was correct. It
is matching with the analytical expressions
shown in the previous sections.
The DSP code for the predictive current
algorithm for the boost mode is shown in the
appendix.
References:
[1] Robert W. Erickson and Dragan Maksimovic,
Fundamentals of Power Electronics, Kluwer academic
publishers, 2004, 2nd edition.
[2] J. Chen, A. Prodic, R. Erickson and D. Maksimovic,
Predictive Digital Current Programmed Control , IEEE
Trans. Power Electron., vol. 18, no. 1, Jan. 2003, pp. 411
419.
[3] V.J.Thottuvelil and G.C.Verghese, "Analysis and
control design of paralleled DC/DC converters with
current sharing," Power Electronics, IEEE Transactions
on , vol.13, no.4, pp.635644, Jul 1998.
[4] R. Mirzaei and V. Ramanarayanan, Digital Deadbeat
Current Control Method for DCDC Converters, in Proc
NPEC conference Dec. 2007.
22
Appendix DSP Code
****** Battery Management discharge emulation  Current loop ******
.sect "vectors2"
int2_4: .long isr_timer1
******************************************************************
; BEGIN DATA INITIALISATION
******************************************************************
.data
uk .long 0x000C7FCE ; value of angular freq w, rad/sec. corresponding to 50 Hz.
uk_1 .long 0x00000000
KI .long 0x01000000
KiT .long 0x00000347 ; KiT = KI * T/2 where Ki=1 & T = 100uS
y2k .long 0x00000000
y2k_1 .long 0x00000000
CONV .long 0x00014000
CONV1 .long 0x000015D8
ZERO .long 0x00000000
ONE1220 .long 0x00100000
ADC1 .long 0x00000000
ADC .word 0x0000
flag1 .word 0x0000
shift4 .word 0x0004
csgainpv .long 0x00253594 ; 2.33 (=1/0.43) in 12.20 format
vsgbm1 .long 0x02FC0000 ; 47.75 in 12.20 format
vsgbm2 .long 0x02F26666 ; 47.15 in 12.20 format
Iref_PV .long 0x00200000 ; 1 A in 12.20
Vin_PV .long 0x06400000 ; 3.74 in 8.24 format (170 V)
Vout_PV .long 0x06400000 ; 6.6 in 8.24 format (300 V)
Vinout .long 0x00000000 ; to store 1(Vin/Vout)
VoutTs .long 0x00000000 ; to store Vout*Ts
iL1_PV .long 0x00100000 ; 1.5 in 8.24 (1.5*0.784)
iL2_PV .long 0x0012D0E5
23
iL3_PV .long 0x0012D0E5
iL1_lim .word 0x0050
tempi .long 0x012D0E56
tempvin .long 0x04666666 ; 200*0.022 in 8.24 format
tempvout .long 0x06999999
temp_pv1 .word 0x0000
temp1 .long 0x00000000
temp2 .long 0x00000000
;L1_PV .long 0x0000353F ; 13.0 mH (at 10 kHz) in 12.20 format
L1_PV .long 0x0000147A ; 5 mH in 12.20 format
Ts_PV .long 0x00000068 ; 100 us in 12.20 format
TMR_PV .long 0x00003A98 ; timer period for 10 kHz
d1_PV .word 0x0000 ; duty ratio of converter 1
d_limit .word 0x2EE0 ; duty ratio limit  0.5
d_period .word 0x3A98 ; timer period
Num32 .long 0x00000000
Den32 .long 0x00000000 ; 1 = FF000001 in 8.24
Quot32 .long 0x00000000
AllF .long 0xFFFFFFFF
new1 .long 0x00000000
new2 .long 0x00000000
******************************************************************
; END OF DATA INITIALISATION
******************************************************************
.global main
.text
main:
SETC OBJMODE
CLRC AMODE
.c28_amode
EALLOW
******************************************************************
24
******************************************************************
; SETUP CLOCK
******************************************************************
MOVL XAR1,#PCLKCR; Peripheral Clock Control Register (address: 0x00701C)
MOV *XAR1,#0003H ; Enabling highspeed clock(HSPCLK) WITH IN EVA peripheral and eCAN
MOVL XAR1,#PLLCR; PLL Control Register
MOV *XAR1,#000AH; CLKIN or SYSCLKOUT = OSCCLK*10/2
MOVL XAR1,#HISPCP; HighSpeed Peripheral Clock(HSPCLK) Prescaler Register for HSPCLK clock
MOV *XAR1,#0000H ; HSPCLK = SYSCLKOUT/1
******************************************************************
; CONFIGURING GPIO PINS ...
******************************************************************
Removed due to space constraint
*****************************************************************
; ENABLING INTERRUPTS
*****************************************************************
Removed due to space constraint
******************************************************************************************
; SETTING TIMER REGISTERS
******************************************************************************************
Removed due to space constraint
************************************************************************
; START OF THE PROGRAM
************************************************************************
start:
MOV DP,#flag1
MOV @flag1,#0000H
************************************************************************
; Sensing iL, Vin and Vout using ADCs (12.20 format)
25
************************************************************************
; LCR _sample_inputs
; Sensing iL and converting it into 12.20 format (multiplied with sensor gain also)
; MOVW DP,#iL1_PV
; MOVL @iL1_PV,P ; iL1_PV, Vin_PV, Vout_PV has the current value
; MOVL ACC,@P
; Limiting the startup inductor curret.
; MOVW DP,#iL1_lim
; CMP AH,@iL1_lim
; B LOOP1,LEQ
; MOVL XAR1,#T1CMPR
; MOV *XAR1,#03A98H
; B here1,UNC
LOOP1:
; Calculation of duty ratio for the boost converter1
MOVW DP,#Vin_PV ; Vin_PV/Vout_PV in 12.20 format
MOVL XAR1,@Vin_PV
MOVW DP,#Num32
MOVL @Num32,XAR1
MOVW DP,#Vout_PV
MOVL XAR1,@Vout_PV
MOVW DP,#Den32
MOVL @Den32,XAR1
LC FracDiv32 ; Calling FracDiv32 Module (output in 12.20 format)
MOVW DP,#Quot32
MOVL XAR2,@Quot32 ; Vin_PV/Vout_PV in XAR2 (12.20 format)
MOVW DP,#ONE1220
MOVL ACC,@ONE1220
SUBL ACC,@XAR2
MOVW DP,#Vinout
MOVL @Vinout,ACC ; Vinout is stored with 1(Vin_PV/Vout_PV)
MOVW DP,#Vout_PV ; Vout_PV*Ts_PV in 12.20 format
MOVL XT,@Vout_PV ; 12.20*12.20 multiplication
SPM 0
26
MOVW DP,#Ts_PV
IMPYL P,XT,@Ts_PV ; lower 32bit of 32*32 product. Note this instruction uses SPM also
QMPYL ACC,XT,@Ts_PV ; higher 32bit of 32*32 product. No SPM is considered by this instruction
ASR64 ACC:P,#16
ASR64 ACC:P,#4 ; Final product output in 12.20 format in P register
MOVW DP,#VoutTs
MOVL @VoutTs,P ; Vout_PV*Ts_PV in VoutTs (12.20 format)
MOVW DP,#L1_PV ; L1_PV/Vout_PV*Ts_PV in 12.20 format
MOVL XAR1,@L1_PV
MOVW DP,#Num32
MOVL @Num32,XAR1
MOVW DP,#VoutTs ; VoutTs contains Vout_PV*Ts_PV
MOVL ACC,@VoutTs
MOVW DP,#Den32
MOVL @Den32,ACC
LC FracDiv32 ; Calling FracDiv32 Module (output in 12.20 format)
MOVW DP,#Quot32
MOVL XAR4,@Quot32 ; L1_PV/Vout_PV*Ts_PV in XAR4/ Quot32 (12.20 format)
MOVW DP,#new1 ; new
MOVL @new1,XAR4
MOVW DP,#Iref_PV
MOVL ACC,@Iref_PV
MOVW DP,#iL1_PV
SUBL ACC,@iL1_PV ; (Iref_PV  iL1_PV) in ACC
MOVW DP,#new2 ; new
MOVL @new2,ACC
MOVL XT,@ACC ; ACC contains (Iref_PV  iL1_PV)
SPM 0
MOVW DP,#Quot32 ; Quot32 contains L1_PV/Vout_PV*Ts_PV
IMPYL P,XT,@Quot32 ; lower 32bit of 32*32 product. Note this instruction uses SPM also
QMPYL ACC,XT,@Quot32 ; higher 32bit of 32*32 product. No SPM is considered by this instruction
ASR64 ACC:P,#16
ASR64 ACC:P,#4 ; Final product output in 12.20 format in P register
MOVL @ACC,P ; ACC contains (L1_PV/Vout_PV*Ts_PV)*(Iref_PV  iL1_PV) (12.20 format)
27
MOVW DP,#Vinout ; 1(Vin_PV/Vout_PV) in Vinout (12.20 format)
ADDL ACC,@Vinout ; Now ACC has "duty ratio" in 12.20 format. convert it into apt number for TCMP
MOVL XT,@ACC ; 12.20*12.20 multiplication of 00003A98 & 12.20 version of duty ratio
SPM 0
MOVW DP,#TMR_PV
IMPYL P,XT,@TMR_PV ; lower 32bit of 32*32 product. Note this instruction uses SPM also
QMPYL ACC,XT,@TMR_PV ; higher 32bit of 32*32 product. No SPM is considered by this instruction
ASR64 ACC:P,#16
ASR64 ACC:P,#4 ; Final product output in 12.20 format in P register
MOV AL,@PL
MOVW DP,#d_limit
CMP AL,@d_limit ; duty ratio limiter  0.7 max
B dlim1,LOS
MOVW DP,#d_limit
MOV AL,@d_limit
dlim1: MOVW DP,#temp_pv1
MOV @temp_pv1,AL ; PL contains binary number of dutyratio1 to compare with timer value
SETC SXM
MOV ACC,#3A98H <<0 ; <<0 is optional.
MOVW DP,#temp_pv1
SUB AL,@temp_pv1
MOVW DP,#d1_PV
MOV @d1_PV,AL ; Actually (1d). which when compared with trailing edge signal gives correct d.
MOVL XAR1,#T1CMPR
; MOV *XAR1,#0EA6H
MOV *XAR1,AL ; instruction is verified
B here1,UNC
here1: MOV DP,#flag1
MOV AL,@flag1
CMP AL,#0000H
B here1,EQ
B start,UNC
************************************************************************
28
isr_timer1:
MOV DP,#flag1
MOV @flag1,#01FFH
OR IER,#0002H ; Enabling global interrupt
MOVL XAR1,#EVAIFRA
MOV *XAR1,#0000000010000000B ; GP Timer1 period interrupt flag is reset
MOVL XAR1,#PIEACK
MOV *XAR1,#0002H
CLRC INTM
IRET
.include "FracDiv32.asm" ; Note that the output is in 12.20 format
.include "init.asm"
.include "adc.asm"
; .include "ivt.asm"
.include "pwm_init.asm"
; .include "variable.asm"
; .include "vectors.asm"
.include "reg_2812.h"
; .include "var.inc"
Note: The subroutines have not been included in the above code.