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B GIO DC V O TO
TRNG I HC S PHM K THUT TP.HCM
KHOA IN IN T
B MN IN T - VIN THNG
----- -----
N TT NGHIP
NGNH: CNG NGH IN T VIN THNG
ti:
THC HIN B GII M VITERBI
TRN FPGA
GVHD: ThS. L Minh Thnh
KS. ng Phc Hi Trang
SVTH: Hunh Minh Kh
MSSV: 06117029
SVTH: L Duy
MSSV: 06117010
Thnh ph H Ch Minh, thng 1 nm 2011
Thc hin b gii m Viterbi trn FPGA Trang i
LI CM N

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Thc hin b gii m Viterbi trn FPGA Trang ii
QUYT NH GIAO TI
H v tn sinh vin: Hunh Minh Kh MSSV: 06117029
L Duy MSSV: 06117010
Ngnh: Cng Ngh in t - Vin thng
Tn ti: Thc hin b gii m Viterbi trn FPGA
1) C s ban u:
T thc tin ca vic thng tin di ng v vin thng ngy cng bng n, cng
vi s am m trong lnh vc in t v vin thng, nhm thc hin ti quyt
nh chn ni dung n tt nghip l m t mt thut gii m knh truyn ph
bin l thut gii Viterbi cho m xon. y c th xem l mt s kt hp tt gia
kin thc vin thng v chuyn ngnh in t.
2) Ni dung cc phn thuyt minh v tnh ton:
o Tng quan v h thng thng tin s.
o M ha chp v thut ton gii m Viterbi.
o M phng thut ton gii m Viterbi trn Matlab.
o Xy dng thut ton gii m Viterbi trn KIT DE2.
3) Cc bn v:
..........................................................................................................................
..........................................................................................................................
4) Gio vin hng dn: ThS. L Minh Thnh
KS. ng Phc Hi Trang
5) Ngy giao nhim v: ....../....../2010
6) Ngy hon thnh nhim v: ....../....../2011

Phn A: Gii thiu
Gio vin hng dn Ngy........thng....nm 20.
Ch nhim b mn
B GIO DC V O TO
TRNG I HC S PHM K THUT
THNH PH H CH MINH
CNG HA X HI CH NGHA VIT NAM
c lp - T do - Hnh phc
Thc hin b gii m Viterbi trn FPGA Trang iii
NHN XT CA GIO VIN HNG DN

TP H Ch Minh, ngy......thng......nm 2011


Gio vin hng dn

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang iv
NHN XT CA GIO VIN PHN BIN

TP H Ch Minh, ngy......thng......nm 2011


Gio vin phn bin

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang v
LI NI U
Cng vi s pht trin ca khoa hc v cng ngh phc v cho cuc sng ca
con ngi, cng ngh vin thng trong nhng nm qua c nhng bc pht trin
mnh m cung cp ngy cng nhiu tin ch cho con ngi.
Th k 21 chng kin s bng n thng tin, trong thng tin di ng ng
mt vai tr rt quan trng. Nhu cu trao i thng tin ngy cng tng c v s
lng, cht lng v cc loi hnh dch v km theo, iu ny i hi phi tm ra
phng thc trao i thng tin mi ngy cng u vit v mang li hiu qu cao hn.
Cc cng ngh di ng v vin thng ngy mt pht trin nhanh chng hng ti
mc ch tng tc cng nh cht lng ca cc dch v nhm p ng nhu cu
ngy cng cao ca con ngi v cc thit b khng dy b ti.
Mt trong nhng khu quan trng nht ca vic thng tin khng dy l vic
truyn v nhn tn hiu. iu ny cn thit phi c mt loi m ha dnh ring cho
knh truyn c kh nng sa cha sai st ca tn hiu truyn i do cc tc ng ca
mi trng. Cc hnh thc c s dng m ha knh truyn trc u c
nhng khuyt im nht nh trong vic khi phc d liu b sai st trn ng
truyn, thng ch c kh nng pht hin li v bo v bn pht thc hin truyn
li tin tc b sai . iu ny lm chm qu trnh truyn tin tc. B m ha dng m
chp v thut gii m Viterbi l mt chun ang c ng dng rt rng ri trn
ton th gii vi nhiu u im vt tri so vi cc hnh thc trc , ngoi kh
nng pht hin li tt nh s kim sot cht ch tin tc truyn i, n cn c kh
nng t khi phc cc tin tc b sai trong qu trnh truyn trn knh truyn. iu
ny gip gim thiu ti a thi gian truyn nhn tin tc, do tc d liu ngy
mt c nng cao. Tuy vn cn mt s hn ch nht nh trong vic khi phc cc
on tin tc sai hng lot, nhng thut ton Viterbi vn l s la chn u tin v l
nn tng cho vic pht trin cc hnh thc m ha v gii m tt hn na hin ti v
sau ny.
V nhng u im ni bt v tnh ng dng cao ca thut ton ny trong hin
ti v tng lai ca ngnh vin thng, nhm thc hin quyt nh chn ti l
Thc hin b gii m Viterbi trn FPGA. Trong phm vi ca cun n ny,
nhm thc hin ti s gii thiu khi qut v hai hnh thc m ha v gii m
ny v tin hnh m phng thut ton m ha v gii m trn Matlab cng nh
m t phn cng trn kit DE2 ca Altera.
Ni dung ca n s bao gm cc vn sau:
Chng 1: Tng quan v h thng thng tin s

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang vi
Gii thiu v v tr vai tr ca m ha knh truyn trong h thng thng tin
s, so snh hai hnh thc m ha l m khi v m trellis.
Chng 2: Thut ton Viterbi
Khi nim v phn tch m chp, cch thc m ha s dng m chp, cng
nh cu trc ca b m ha chp. Gii thiu thut ton gii m Viterbi,
nguyn l thc hin gii m v phn loi mt s phng php gii m.
Chng 3: Xy dng thut gii Viterbi dng Matlab
Tin hnh i m phng thut ton m ha m chp v thut ton gii m
Viterbi. Phn tch thut ton
Chng 4: Xy dng thut gii Viterbi trn kit DE2
M phng thut ton thc t hn trn kit DE2 vi cc led hin th d liu t
thy c hiu qu ca thut ton Viterbi, ng dng ngn ng thit k
phn cng VHDL
Chng 5: Kt lun
nh gi kt qu thc hin ca n v a ra phng hng pht trin
ca ti trong tng lai.
TP HCM. Ngy thng nm 2011
Nhm thc hin ti

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang vii
MC LC
Trang
TRNG I HC S PHM K THUT TP.HCM ................................. 1
LI CM N ....................................................................................................... i
QUYT NH GIAO TI ........................................................................... ii
NHN XT CA GIO VIN HNG DN ............................................... iii
LI NI U ..................................................................................................... v
MC LC ......................................................................................................... vii
LIT K HNH ................................................................................................... x
LIT K BNG ................................................................................................ xii
PHN B .................................................................................................................. 13
CHNG 1 ....................................................................................................... 14
1.1 V tr ca m ha knh trong h thng thng tin s ................................. 14
1.2 Khi nim m ha knh v phn loi ...................................................... 15
1.2.1 Khi nim ......................................................................................... 15
1.2.2 Phn loi m ha knh ..................................................................... 16
1.3 Khi qut v m khi v m trellis .......................................................... 16
1.3.1 M khi ............................................................................................ 16
1.3.2 M trellis .......................................................................................... 17
CHNG 2 ....................................................................................................... 19
2.1 Khi nim m chp .................................................................................. 19
2.2 Phn tch m ha dng m chp .............................................................. 19
2.3 Cu trc m chp ..................................................................................... 23
2.4 Biu din m chp .................................................................................. 27
2.5 u nhc im ca m chp .................................................................. 30
2.5.1 u im ........................................................................................... 30
2.5.2 Nhc im ..................................................................................... 30
2.6 inh nghia thut toan Viterbi .................................................................. 30
2.7 Phn tch thut gii Viterbi ...................................................................... 31
2.8 Gii m quyt nh cng v gii m quyt nh mm ............................. 43

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang viii
2.8.1 Thut ton Viterbi quyt nh cng ................................................. 43
2.8.2 Thut ton Viterbi quyt nh mm ................................................. 49
2.8.2.1 Thut ton Viterbi quyt nh mm (phng php 1) ............... 49
2.8.2.2 Thut ton Viterbi quyt nh mm (phng php 2) ............... 50
2.8.3 u im ca gii m quyt nh mm so vi gii m quyt nh cng
.................................................................................................................... 52
2.9 Xc sut li ............................................................................................ 55
2.10 u nhc im ca thut ton gii m Viterbi ..................................... 56
2.10.1 u im ......................................................................................... 56
2.10.2 Nhc im ................................................................................... 56
CHNG 3 ....................................................................................................... 57
3.1 Gii thiu ............................................................................................... 57
3.2 S khi h thng ................................................................................ 57
3.3 Lu m phng ................................................................................... 58
3.3.1 Khi to bit ng vo ......................................................................... 58
3.3.2 Khi m ha ..................................................................................... 59
3.3.3 Khi cng nhiu Gausse trng ......................................................... 59
3.3.4 Khi gii m .................................................................................... 59
3.3.5 Tnh ton v v BER ........................................................................ 60
3.4 Hnh nh v chng trnh m phng ........................................................ 60
CHNG 4 ....................................................................................................... 66
4.1 Gii thiu s lc KIT DE2 v phn mm Quartus ................................ 66
4.1.1 KIT DE2 ca Altera .......................................................................... 66
4.1.1.1 Tng quan kit DE2 ..................................................................... 66
4.1.1.2 S dng nt nhn v Switch ..................................................... 68
4.1.1.3 S dng LCD ............................................................................ 69
4.1.2 Phn mm lp trnh Quatus II ......................................................... 69
4.2 Gii quyt vn .................................................................................... 70
4.2.1 Gii m viterbi quyt nh cng ........................................................ 70
4.2.2 Gii m viterbi quyt nh mm ........................................................ 74
4.3 Lu d thut ton lp trnh ....................................................................... 76
4.4 Kt qu ................................................................................................... 83

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang ix
CHNG 5: KT LUN ................................................................................. 89
5.1 Tng kt nhn xt ..................................................................................... 89
5.2 Tn ti v hng pht trin ca ti ...................................................... 89
PHN C .................................................................................................................. 91
I. Ph lc ....................................................................................................... 92
1. Hng dn s dng kit DE2 m phng ............................................. 92
2. Ti nguyn s dng trn Kit DE2 .......................................................... 92
3. M ngun Matlab ................................................................................. 95
4. M ngun VHDL ................................................................................ 106
II. Ti liu tham kho .................................................................................. 130

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang x
LIT K HNH
Hnh 1.1: V tr ca m ha knh truyn trong h thng thng tin s
Hnh 1.2: S phn chia m ha knh thnh hai nhnh ring bit
Hnh 2.1: B m ha cho m chp tc 1/ 2 R
Hnh 2.2: B m ha h thng vi 1/ 2 R
Hnh 2.3: B m ha h thng
Hnh 2.4: S b m ha h thng 2 / 3 R c phn cng n gin
Hnh 2.5: S tng qut b m chp
Hnh 2.6: B m chp (3,2,2)
Hnh 2.7: S b m chp vi N=3, k=1, n=3
Hnh 2.8: S hnh cy b m (2,1,3)
Hnh 2.9: S hnh li b m chp (2,1,3).
Hnh 2.10: S trng thi ca b m chp (2,1,3).
Hnh 2.11: B m chp tc
Hnh 2.12: hnh trng thi ca m chp
Hnh 2.13: Cc nhnh trong b m ha
Hnh 2.14: ng i hon chnh khi phc chnh xc tn hiu ti ng ra
Hnh 2.15: Tn hiu nhn c 2 bit sai ti t =2 v t = 11
Hnh 2.16: Ti thi im t = 1
Hnh 2.17: Ti thi im t = 2
Hnh 2.18: Ti thi im t = 3
Hnh 2.19: Ti thi im t = 4
Hnh 2.20: Ti thi im t = 5
Hnh 2.21: Tt c d liu c gii m v sa sai chnh xc
Hnh 2.22: B m tc 1/3 v K= (7,7,5)
Hnh 2.23: Gii m quyt nh cng v mm
Hnh 2.24: H thng m tch chp
Hnh 2.25: Kiu knh h thng nh phn, trong p l xc sut cho
Hnh 2.26: Biu din Viterbi theo v d
Hnh 2.27: M t gii m quyt nh cng vi b m parity
Hnh 2.28: M t gii m quyt nh mm vi b m parity
Hnh 3.1: S khi h thng
Hnh 3.2: Lu m phng
Hnh 3.3: Giao din khi u chng trnh m phng
Hnh 3.4: Giao din chng trnh m phng 1
Hnh 3.5: Giao din chng trnh m phng 2
Hnh 3.6: Nhp bit ngu nhin Quyt nh mm
Hnh 3.7: BER ca quyt nh mm

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang xi
Hnh 3.8: Nhp bit ngu nhin Quyt nh cng
Hnh 3.9: BER ca quyt nh cng
Hnh 3.10: So snh BER ca c quyt nh cng v mm
Hnh 3.11: T nhp bit vo Quyt nh mm
Hnh 4.1: KIT DE2 ca Altera
Hnh 4.2: S khi KIT DE2
Hnh 4.3: Chng di phm nhn
Hnh 4.4: Tnh ton metric nhnh v metric ng cho b gii m Viterbi
Hnh 4.5: Lu gii thut chnh ca chng trnh
Hnh 4.6: Lu gii thut b gii m
Hnh 4.7: Lu chi tit gii thut gii m viterbi tren Kit DE2
Hnh 4.8: Lu tnh khong cch Hamming
Hnh 4.9: Lu gii thut tnh khong cch Euclidean
Hnh 4.10: Lu khi tnh khong cch nhnh
Hnh 4.11: Lu khi ACS
Hnh 4.12: Lu khi truy hi
Hnh 4.13: Lu khi gii m
Hnh 4.14: Kt qu m phng 1
Hnh 4.15: Kt qu m phng 2
Hnh 4.16: Kt qu m phng 3
Hnh 4.17: Kt qu m phng 4
Hnh 4.18: Kt qu m phng 5
Hnh 4.19: Kt qu m phng 6
Hnh 4.20: M phng trn Matlab
Hnh 4.21: Hnh thc t b kit 1
Hnh 4.22: Hnh thc t b kit 2
Hnh 4.23: Hnh thc t b kit 3

Phn A: Gii thiu
Thc hin b gii m Viterbi trn FPGA Trang xii
LIT K BNG
Bng 2.1: Trng thi ng vo v ng ra ca b m ha tc
Bng 2.2: Bng ma trn tch ly ca c 8 bit ca bn tin
Bng 2.3: Bng lch s trng thi (state history table)
Bng 2.4: Bng cc trng thi c la chn khi truy hi
Bng 2.5: Bng trng thi k tip (next state table)
Bng 2.6: Bng cha cc d liu ca bn tin gc c khi phc
Bng 2.7: V d v punctured code
Bng 2.8: Cc gi tr metric bit thng thng
Bng 2.9: Cc gi tr metric bit cch 2
Bng 2.10: V d vi b m parity
Bng 2.11: Tnh ton khong cch Hamming cho quyt nh cng
Bng 2.12: Tnh ton khong cch Euclidean cho quyt nh mm
Bng 4.1: Th t kt ni phm nhn vi cc chn ca FPGA
Bng 4.2: Gn chn FPGA cho mn hnh LCD
Bng 4.3: Trng thi hin ti v trng thi trc ca n
Bng 4.4: Bng trng thi tip theo

Phn A: Gii thiu
PHN B
NI DUNG
Thc hin b gii m Viterbi trn FPGA Trang 14

CHNG 1
TNG QUAN V H THNG THNG TIN S
1.1 V tr ca m ha knh trong h thng thng tin s
M ha knh l mt khu rt quan trng trong h thng thng tin s khng dy
cng vi m ha ngun, ghp knh, iu ch, to ra mt tn hiu ph hp cho
vic truyn dn v tuyn v tn hiu c kh nng iu khin c s sai bit v
sa cc li xy ra nu c c th khi phc li gn nh nguyn dng tn hiu tin
tc m mnh truyn i.
Hnh 1.1: V tr ca m ha knh truyn trong h thng thng tin s
M ho knh: mc ch l lm gim xc sut sai thng tin khi truyn qua knh
truyn.
Vic gim thiu xc sut sai da vic pht hin sai v sa sai c th dn n vic
gim t s tn hiu trn nhiu (SNR) cn thit nh gim c cng sut, tit kim
nng lng. Vic sa sai hu hiu cho tn hiu SNR nh s thun li cho vic bo
mt, tri ph v tng chnh xc ca thng tin nhn- mc ch quan trng nht ca
truyn thng.

Chng 1: Tng quan v h thng thng tin s
Thc hin b gii m Viterbi trn FPGA Trang 15
1.2 Khi nim m ha knh v phn loi
1.2.1 Khi nim
M ha knh l vic a thm cc bit d vo tn hiu s theo mt quy lut no
y, nhm gip cho bn thu c th pht hin v thm ch sa c c li xy ra trn
knh truyn.
Mt s h thng c th khc phc li bng cch gi mt yu cu cho bn pht
gi li tn hiu nu pht hin li, l ch ARQ. Nhng vic ny ch thch hp
cho cc h thng truyn dn hu tuyn v mt s h thng v tuyn khng yu cu
v thi gian tr. Thay vo , vi cc h thng thng tin khng dy ngy nay, ngi
ta hay s dng mt loi m c th pht hin v khc phc li mt cch t ng.
Vic ny gim thiu thi gian tr so vi cc h thng yu cu truyn li. B m ny
thng c gi l m iu khin li (ECC), hay chnh xc hn l FEC.
Mc ch ca l thuyt M ha trn knh truyn l tm nhng m c th truyn
thng nhanh chng, cha ng nhiu t m t hp l v c th sa li hoc t nht
pht hin cc li xy ra. Cc mc ch trn khng ph thuc vo nhau, v mi loi
m c cng dng ti u cho mt ng dng ring bit. Nhng c tnh m mi loi
m ny cn cn tu thuc nhiu vo xc sut li xy ra trong qu trnh truyn thng.
i vi mt a CD thng thng, li trong m thanh xy ra ch yu l do bi
v nhng vt xc trn mt a. V th, cc m c lng vo vi nhau. D liu
c phn b trn ton b mt a. Tuy khng c tt cho lm, song mt m ti
din n gin c th c dng lm mt v d d hiu. Chng hn, chng ta ly mt
khi s liu bit (i din cho m thanh) v truyn gi chng ba ln lin. Bn my
thu, chng ta kim tra c ba phn lp li trn, tng bit tng bit mt, ri ly ci no
c s bu cao nht. im khc bit y l, chng ta khng ch truyn gi cc bit
theo th t. Chng ta lng n vo vi nhau. Khi d liu ny, trc tin, c chia
ra lm 4 khi nh. Sau chng ta gi mt bit khi u tin, tip theo mt bit
khi th hai v.v tun t qua cc khi. Vic ny c lp i lp li ba ln phn b
s liu ra trn b mt a. Trong ng cnh ca m ti din n gin trn, vic lm
ny hnh nh khng c hiu qu cho lm. Song hin nay c nhng m c hiu
ng cao, rt ph hp vi vic sa li xy ra t ngt do mt vt xc hay mt vt
bi, khi dng k thut lng s liu ni trn.
Mi m thng ch thch hp cho mt ng dng nht nh. Vin thng trong v
tr b gii hn bi nhiu nhit trong thit b thu. Hin trng ny khng xy ra mt
cch t pht bt thng, song xy ra theo mt chu trnh tip din. Tng t nh
vy, modem vi di tn hp b hn ch v nhiu m tn ti trong mng li in
thoi. Nhng nhiu m ny c th c biu hin r hn bng mt m hnh tp m
tip din. in thoi di ng hay c vn do s suy sng nhanh chng xy ra. Tn
s cao c dng c th gy ra s suy sng tn hiu mt cch nhanh chng, ngay c

Chng 1: Tng quan v h thng thng tin s
Thc hin b gii m Viterbi trn FPGA Trang 16
khi my nhn ch di ch vi phn Anh. Mt ln na, ngi ta hin c mt loi
m ha trn knh truyn c thit k i u vi tnh trng suy sng.
1.2.2 Phn loi m ha knh
L thuyt m ha i s c chia ra lm 2 loi m chnh
1. M khi.
2. M trellis.
Chng phn tch ba c tnh sau ca m (ni chung) l:
Chiu di ca m.
Tng s cc t m hp l.
Khong cch Hamming ti thiu gia hai t m hp l.
Hnh 1.2: S phn chia m ha knh thnh hai nhnh ring bit
Trong mi loi m li c phn tch thnh 2 nhnh na l m tuyn tnh v
m khng tuyn tnh.
Thng th cc m khng tuyn tnh khng c ng dng trong thc t v cc
nhc im ca n, nn y chng ta ch cp n cc m tuyn tnh.
Trong phn tip theo chng ta s khi qut s lc v m khi v m trellis.
1.3 Khi qut v m khi v m trellis
1.3.1 M khi
M khi tuyn tnh mang tnh nng tuyn tnh, chng hn tng ca hai t m no
y li chnh l mt t m; v chng c ng dng vo cc bit ca ngun trn
tng khi mt; ci tn m khi tuyn tnh l v vy. C nhng khi m bt tuyn

Chng 1: Tng quan v h thng thng tin s
Thc hin b gii m Viterbi trn FPGA Trang 17
tnh, song kh m chng minh c rng mt m no l mt m tt nu m y
khng c c tnh ny.
Bt c m khi tuyn tnh no cng c i din l (n,m,d
min
), trong
1. n, l chiu di ca t m, trong k hiu,
2. m, l s k hiu ngun c dng m ha tc thi,
3. d
min
, l khong cch hamming ti thiu ca m.
C nhiu loi m khi tuyn tnh, nh
1. M vng (M Hamming l mt b phn nh ca m tun hon).
2. M chn l.
3. M Reed-Solomon.
4. M BCH.
5. M Reed-Muller.
6. M hon ho.
M khi c gn lin vi bi ton ng gi ng xu l bi ton gy mt s
ch trong nhiu nm qua. Trn b din hai chiu, chng ta c th hnh dung c
vn mt cch d dng. Ly mt nm ng xu, nm trn mt bn, ri dn
chng li gn vi nhau. Kt qu cho chng ta mt mu hnh lc gic tng t nh
hnh t ong. Cc m khi cn da vo nhiu chiu khc na, khng d g m hnh
dung c. M Golay c hiu ng cao, dng trong truyn thng qua khong khng
v tr, s dng nhng 24 chiu. Nu c dng l m nh phn (thng thy), cc
chiu m ch n chiu di ca t m nh nh ngha trn.
1.3.2 M trellis
M trellis hay cn gi l m chp (kt hp) c s dng trong cc modem di
tn m (V.32, V.17, V.34) v trong cc in thoi di ng GSM, cng nh trong cc
thit b truyn thng ca qun i v trang v trong cc thit b truyn thng vi v
tinh.
Mc ch ca vic to ra m chp l nhm lm cho tt c cc k hiu t m tr
thnh tng trng s ca nhiu loi k hiu thng ip trong nhp liu. N tng t
nh ton kt hp c dng trong cc h tuyn tnh bt bin dng tm xut liu
ca mt h thng, khi chng ta bit nhp liu v cc p ng xung.
Ni chung chng ta tm xut liu ca b m chp h thng, tc s kt hp ca
nhp liu bit, i chiu vi trng thi ca b m ha kt hp, hoc trng thi ca cc
thanh ghi.

Chng 1: Tng quan v h thng thng tin s
Thc hin b gii m Viterbi trn FPGA Trang 18
V c bn m ni, m chp khng gip thm g trong vic chng nhiu hn mt
m khi tng ng. Trong nhiu trng hp, chng ni chung cho chng ta mt
phng php thc thi n gin hn, hn hn mt m khi c hiu qu tng ng.
B m ha thng l mt mch in n gin, c mt b nh, mt vi bin php
truyn thng tin phn hi bo tnh hnh, thng l cc cng loi tr XOR. B m
ha c th c thc thi trong phn mm hay phn sn.
Thut ton Viterbi l mt thut ton ti u nht c dng gii m cc m
chp. Hin c nhng phng php gim c gip vo vic gim khi lng tnh
ton phi lm. Nhng phng php ny phn ln da vo vic tm tuyn ng c
kh nng xy ra cao nht. Tuy khng ngn gn, song trong mi trng nhiu thp
hn, ngi ta thng thy chng cho nhng kt qu kh quan. Cc b iu hnh vi
x l hin i c kh nng thc hin nhng thut ton tm gim c ni trn vi t
l trn 4000 t m trong mt giy.
ti ch yu nghin cu v thut ton gii m Viterbi thy c u im
ca thut ton trong vic gim ti thiu sai s khi m ha v gii m tn hiu. Do
, trong cc phn tip theo ca n, chng ta ch tm hiu vic m ha tin tc
dng m chp v gii m da trn thut ton Viterbi cng nh nhng u khuyt
im ca chng. ng thi ta tin hnh m phng thut ton trn Matlab v trn
Kit FPGA kim chng thc t hn. Cn i vi cc m trellis cn li th ta s
khng phn tch trong phm vi cun n ny.

Chng 1: Tng quan v h thng thng tin s
Thc hin b gii m Viterbi trn FPGA Trang 19
CHNG 2
THUT GII M VITERBI
2.1 Khi nim m chp
M chp l mt k thut m ha sa sai. M chp thuc h m li (m ha
theo Trellis) v c xy dng da trn mt a thc sinh hoc mt s chuyn
trng thi (trellis m) c trng. Qu trnh gii m ca m chp phi da vo trellis
m thng qua cc gii thut khc nhau, trong ni ting nht l gii thut Viterbi.
Ti sao gi l m chp v cu trc m ha c th biu din di dng php tnh
chp gia a thc sinh m v chui tn hiu c m ha.
M ha chp v thut ton gii m Viterbi c s dng trong khong hn mt
t in thoi, c th l ln nht trong cc loi thut ton c ng dng. Tuy nhin,
hin ti th thut ton x l viterbi c ng dng nhiu nht trong cc thit b m
thanh v hnh nh k thut s. Ngy nay, chng cn c s dng trong cc thit b
bluetooth.
Mc ch ca m ha knh truyn l nhm tng dung lng knh truyn, bng
cch cng thm vo tn hiu nhng d liu d tha c thit k mt cch cn thn
trc khi truyn ln knh truyn. M ha chp v m ha khi l 2 dng chnh ca
m ha knh truyn. M ha chp th da trn d liu ni tip, 2 hoc mt vi bit
c truyn mt lc, cn m ha khi th da trn mt khi d liu ln tng quan
(c trng l khong vi trm bytes). V d, m Redsolomon l mt m ha khi.
S khc nhau c bn gia m ha khi v m ha chp l m ha khi l m
ha khng nh. Cho mt chui d liu K bit, th ng ra ca b m ha khi l mt
khi d liu n bit duy nht. M ha chp khng kt ni cc khi bit ring vo trong
mt khi t m, thay vo n s chp nhn mt chui bit lin tc v ta thnh mt
chui ng ra. Hiu qu hay tc d liu ca m ha chp c nh gi bng t l
ca s bit ng vo k, v s bit ng ra n. Trong m ha chp l c mt vi b nh
dng ghi nh dng bit vo. Thng tin ny c s dng m ha cc bit tip
theo.
2.2 Phn tch m ha dng m chp
M chp l m tuyn tnh c ma trn sinh c cu trc sao cho php m ha c
th xem nh mt php lc (hoc ly tng chp). M chp c s dng rng ri
trong thc t. Bi m ha c xem nh mt tp hp cc b lc s tuyn tnh vi
dy m l cc u ra ca b lc c ghp xen k. Cc m chp l cc m u tin
c xy dng cc thut ton gii m quyt nh mm hiu qu.
M khi t cc khi k du (hay ky hiu) to ra cc khi n du. Vi cc m
chp (thng c xem l cc m dng), b m ha hot ng trn dng lin tc

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 20
cc bit vo khng c phn thnh cc khi tin ri rc. Tuy nhin tc m
[ ]
n
F X 1
]
k
n
c hiu l c c k ng vo mi bc thi gian s to ra n ng ra.
Cc php tnh s hc s dng trong hnh thc m ha ny c th c thc hin
trn mt trng ty nhng thng thng vn l trn GF(2).
Ta biu th cc dy v cc hm truyn t nh cc chui ly tha ca bin x
(i khi cn dng k hiu D thay cho x). Dy {,m
-2
, m
-1
, m
0
, m
1
, m
2
, } (vi
cc phn t m
i
thuc trng F) c xem nh mt chui Laurent:
( )
e
e
e
m X m x


Tp tt c cc chui Laurent trn F l mt trng, ta k hiu trng ny l
[ ]
F X 1
]
. Nh vy [ ]
( ) m X F X 1
]
i vi dng nhiu bit vo ta dng k hiu m
(1)
(x) biu th dng u
vo u tin, m
(2)
(x) biu th dng u vo th hai. Tp cc dng vo xem nh mt
vect:
m(x) = [m
(1)
(x) m
(2)
(x)] [ ]
2
F X 1
]
B m ha cho m chp thng c coi l mt tp cc b lc s. Hnh 2.1 ch ra
mt v d v mt b m ha
Hnh 2.1: B m ha cho m chp tc
1
2
R
(cc D biu th cc nh mt bt cc trigger D)
Dng vo m
k
i qua hai b lc dng chung cc phn t nh to ra hai dng
ra.
C
(1)
k
= m
k
+ m
k-1
+ m
k-2
v C
(2)
k
= m
k
+ m
k-2
.
Hai dng ra ny c a ra xen k to ra dng c m ha C
k
. Nh
vy c mi bt vo li c hai bt m ha c a ra, kt qu l ta c mt m c tc

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 21
R = 1/2.
Thng thng ta coi trng thi ban u ca cc phn t nh l 0. Nh vy,
vi dng vo m = {1, 1, 0, 0, 1, 0, 1} cc u ra s l:
C
(1)
= {1, 0, 0, 1, 1, 1, 0, 1, 1}
v C
(2)
= {1, 1, 1, 1, 1, 0, 0, 0, 1}
Dng ra: C = {11, 01, 01, 11, 11, 10, 00, 10, 11}
y du phy phn cch cc cp bt ra ng vi mi bt vo.
Ta c th biu th hm truyn t u vo m(x) t u ra C
(1)
(x) nh sau:
g
1
(x) = 1 + x +x
2
.
Tng t ta c g
2
(x)= 1 + x
2
.
Dng vo m = {1, 1, 0, 0, 1, 0, 1} c th biu th nh sau:
m (x) = 1+ x+ x
4
+ x
6
.
Cc u ra s l:
C
(1)(
x) = m(x)g
1
(x) = (1+ x +x
4
+ x
6
)(1+ x + x
2
) = 1 +x
3
+x
4
+x
5
+x
7
+ x
8
C
(2)(
x) = m(x)g
2
(x) = (1+ x +x
4
+ x
6
)(1+ x
2
) = 1+x + x
2
+x
3
+x
4
+x
8
Vi mi m chp tc c mt hm truyn ma trn k n

(x) (cn
c gi l ma trn truyn). Vi m tc v d trn ta c:
G
a
(x) = [1+ x+ x
2
1 + x
2
]
Ma trn truyn ny khng ch c dng cc a thc, ta c th thy thng qua
v d sau:
V d 2.2.1: Xt ma trn truyn ca m chp sau:
V c 1 ct u tin nn dng vo s xut hin trc tip u ra an xen, bi
vy y l mt m chp h thng. B m ha cho m ny c m t hnh 2.2:
Hnh 2.2: B m ha h thng vi
1
2
R

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 22
Vi dng vo: m (x) = 1+ x + x
2
+ x
3
+ x
4
+ x
8
cc u ra C
(1)
k
v C
(2)
k
c
dng:
C
(1)
k
= m(x) =1 + x +x
2
+ x
3
+ x
4
+ x
8
( )
2 3 4 8 2
( 2)
2
(1 x x x x x )(1 )
1
k
x x
C x
x
+ + + + + + +

+
Mt b m ha ch c cc hng a thc trong ma trn truyn c gi l b
m ha c p ng xung hu hn. Mt b m ha c cc hm hu t trong ma trn
truyn gi l b m ha c p ng xung v hn.
Vi m c tc k/n vi k > 1 dy tin tc u vo (ta coi nh c tch ra
t mt dy tin tc thnh k dng), ta c:
m(x) = [m
(1)
( x), m
(2)
(x),,m
(k)
(x)]
v
Dy ra c biu th nh sau:
C(X) = [C
(1)
(x), C
(2)
(x),,C
(n)
(x)] = m(x)G(x)
Ma trn truyn G(x) c gi l h thng nu c th xc nh c mt ma
trn n v trong cc phn t ca G(x) (chng hn nu bng cc php hon v hng
v/hoc ct ca G(x) c th thu c mt ma trn n v).
V d 2.2.2: Cho m h thng tc
2
3
R
c ma trn truyn sau:
S th hin ca m ny cho trn hnh 2.3:

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 23
Hnh 2.3: B m ha h thng
Mt s m ha khc c hiu qu hn c m t hnh 2.4:
Hnh 2.4: S b m ha h thng
2
3
R
c phn cng n gin
Gi s: m(x) = [1+ x
2
+ x
4
+ x
5
+ x
7
+,x
2
+ x
5
+ x
6
+ x
7
+ ]
Khi u ra C(x) c dng:
C(x) = [1+ x
2
+ x
4
+ x
5
+ x
7
+ , x
2
+ x
5
+ x
6
+ x
7
+ , x+ x
3
+ x
5
+ ]
Khi a ra xen k dng ra s l:
{100, 001, 110, 001, 100, 111, 010, 110}
T cc v d trn ta c nh ngha sau cho m chp
nh ngha: M chp tc R = k/n trn trng cc chui Laurent hu t
[ ]
F X 1
]
trng F l nh ca mt nh x tuyn tnh n nh ca cc
chui Laurent k chiu m (x) [ ]
k
F X 1
]
vo cc chui Laurent C(x) [ ]
n
F X 1
]
2.3 Cu trc m chp
M chp c to ra bng cch cho chui thng tin truyn qua h thng cc
thanh ghi dch tuyn tnh c s trng thi hu hn. Cho s lng thanh ghi dch l
m (cng k hiu l N), b m c k bit ng vo v u ra b m chp c n bit ng ra
(n hm i s tuyn tnh hoc n ngo ra cng modulo). Tc m l R = k/n, s
nh ca b ghi dch l mk v tham s L gi l chiu di rng buc (Constraint
length) ca m chp (vi L=k(m-1)).

Chng 2: Thut gii m Viterbi
Chui m n bit
Thc hin b gii m Viterbi trn FPGA Trang 24
Cc thng s k,n c phm vi gii hn trong khong gi tr t 1 n 8, thng s m
trong khong t 2 n 10, v tc m R t 1/8 n 7/8 ngoi tr cc b m ha
c s dng trong vin thng v tr c th c tc 1/100 hoc thm ch cao hn.
Trong mt s ti liu, khi ni n m chp, ngi ta cn c trng cho b m
ha chp bng chiu di rng buc K v tc m R. Tc m, R=k/n, c hiu
l t s gia s bit ng vo v s k hiu ng ra ca b m ha. Thng s chiu di
rng buc, K, cho bit chiu di ca b m ha m chp, v d, c bao nhiu trng
thi k-bit c th a n mch logic t hp to ra k hiu ng ra. Trong ni dung
ti ny, chng ti s dng b m vi b d liu bao gm chiu di rng buc K
v tc b m R nh cp trn.
Khi thc hin vi m chp trong cc ng dng thng thng, ngi ta thng
ch chn s thanh ghi gii hn, mi thanh ghi ch c 1 nh n gin cho vic
thit k m vn m bo tnh nng m ha tt. Tng ng vi mi tc m ha
(cc b m n gin), ngi ta cng th nghim v chn ra ch mt s a thc
sinh cho hiu qu m ha cao s dng.
Gi thit, b m chp lm vic vi cc ch s nh phn, th ti mi ln dch s
c k bit thng tin u vo c dch vo thanh ghi dch th nht v tng ng c k
bit thng tin trong thanh ghi dch cui cng c y ra ngoi m khng tham gia
vo qu trnh to chui bit u ra. u ra nhn c chui n bit m t n b cng
mun-2 (xem hnh 2.5). Nh vy, gi tr chui u ra knh khng ch ph thuc
vo k bit thng tin u vo hin ti m cn ph thuc vo (m-1)k bit trc
, v c gi l m chp (n,k,m).
Hnh 2.5: S tng qut b m chp.
Gi s u l vct u vo, x l vct tng ng c m ho, by gi chng ta
m t cch to ra x t u. m t b m ho chng ta phi bit s kt ni gia
thanh ghi u vo vo u ra hnh 2.5. Cch tip cn ny c th gip chng ta ch ra
s tng t v khc nhau cng nh l vi m khi. iu ny c th dn ti nhng
k hiu phc tp v nhm nhn mnh cu trc i s ca m chp. iu lm
gim i tnh quan tm cho mc ch gii m ca chng ta. Do vy, chng ta ch

Chng 2: Thut gii m Viterbi
Chui thng tin
u vo k bit
1
1
2
2
...
.
k
k
1
1
2... k
k
1
1
2...
2
k
k
1
1
2
2
3
3
n
n
Thc hin b gii m Viterbi trn FPGA Trang 25
phc ho tip cn ny mt cch s lc. Sau , m t m ho s c a ra vi
nhng quan im khc.
m t b m ho hnh 2.5 chng ta s dng N ma trn b sung G
1
,G
2
,G
N
bao gm k hng v n ct. Ma trn G
i
m t s kt ni gia on th i ca k nh
trong thanh ghi ng vo vi n ca thanh ghi ng ra. N ng vo ca hng u tin
ca G
i
m t kt ni ca u tin ca on thanh ghi u vo th i vi n ca
thanh ghi ng ra. Kt qu l 1 trong G
i
ngha l c kt ni, l 0 ngha l khng
kt ni. Do chng ta c th nh ngha ma trn sinh ca m chp:
V tt c cc cc ng vo khc trong ma trn bng 0. Do nu ng vo l
vct u, tng ng vct m ho l:
. x u G

B m chp l h thng nu trong mi on ca n ch s uc to, k s u l


mu ca cc ch s u vo tng ng. N c th xc nh rng iu kin ny
tng ng c cc ma trn kn theo sau
v
i = 2,3,.,N
Chng ta xt mt vi v d minh ho sau y:
V d 2.3.1: Xt m (3,2,2). B m ho c ch trong hnh 2.6. By gi m c
nh ngha thng qua 2 ma trn:

B m ho l h thng, ma trn sinh c to ra:

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 26
Chui thng tin u = ( 11011011) c m ha thnh chui m
x = (111010100110)
Hnh 2.6: B m chp (3,2,2).
Mt cch tng t ta cng c th biu din ma trn sinh G = (G
1
,G
2
,,G
N
),
Nh vy ngha ca ma trn sinh l n ch ra phi s dng cc hm tng ng no
to ra vc t di n mi phn t c mt b cng mun-2, trn mi vc t c Nk
tham s biu din c hay khng cc kt ni t cc trng thi ca b ghi dch ti b
cng mun-2 . Xt vc t th i (g
i
, n i 1), nu tham s th j ca g
i
(Lk j
1) c gi tr 1 th u ra th j tng ng trong b ghi dch c kt ni ti b
cng mun-2 th i v nu c gi tr 0 th u ra th j tng ng trong b ghi
dch khng c kt ni ti b cng mun-2 th i.
V d 2.3.2: Cho b m chp c s thanh ghi N = 3, s nh trong mi thanh ghi
dch k = 1, chiu di chui u ra n = 3 tc l m (3,1,3) v ma trn sinh ca m
chp c dng sau:
1
2
100
101 (4, 5, 7)
111
n
g
g
G G G
g
1
1
1
1
1

1
1
1
1
]
]
M
C th biu din di dng a thc sinh l:
G(D) = [1 1+D
2
1+D+D
2
]
Do s m chp c biu din nh sau:

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 27
Hnh 2.7: S b m chp vi N=3, k=1, n=3
2.4 Biu din m chp
C ba phng php biu din m chp l: s li, s trng thi, v
s hnh cy. lm r phng php ny ta tp trung phn tch da trn v d
hnh 2.1 vi b m (2,1,3), a thc sinh (7,5).
* S hnh cy:
T v d hnh 2.1, gi thit trng thi ban u ca cc thanh ghi dch trong b
m u l trng thi ton 0. Nu bit vo u tin l bit 0 th u ra ta nhn c
chui 00, cn nu bit vo u tin l bit 1 th u ra ta nhn c chui 11.
Nu bit vo u tin l bit 1 v bit vo tip theo l bit 0 th chui th nht l
11 v chui th hai l chui 10. Vi cch m ho nh vy, ta c th biu din
m chp theo s c dng hnh cy (xem hnh 2.8).Vi hng ln l hng ca
bit 0 i vo b m, nhnh i xung biu hin cho bit 1 c dch vo. T s
hnh cy ta c th thc hin m ho bng cch da vo cc bit u vo v thc hin
ln theo cc nhnh ca cy, ta s nhn c tuyn m, t ta nhn c dy cc
chui u ra.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 28
00
10
0
1
00
10
01
11
00
10
01
11
00
10
01
11
00
00
11
00
11
00
10
01
10
01
11
11
00
01
10
Hnh 2.8: S hnh cy ca b m (2,1,3)
*S hnh li:
Do c tnh ca b m chp, cu trc vng lp c thc hin nh sau: chui n
bit u ra ph thuc vo chui k bit u vo hin hnh v (N-1) chui u vo trc
hay (N-1) k bit u vo trc . T v d hnh 2.1 ta c chui 2 bit u ra ph
thuc vo 1 bit u vo l 1 hoc 0 v 4 trng thi c th c ca hai thanh ghi
dch, l 00; 01; 10; 11. T s hnh cy trn, ta thy rng ti tng th 3,
c mi trng thi 00, 01, 10, 11 u c 2 nhnh n t cc trng thi trc ty
thuc vo bit c dch vo b m l bit 0 hay bit 1. Vi tnh cht ta c th biu
din m chp bng s c dng hnh li gn hn, trong cc ng lin nt
c k hiu cho bit u vo l bit 1 v ng t nt c k hiu cho cc bit
u vo l bit 0 (xem hnh 2.9). Ta thy rng t sau tng th hai hot ng ca
li n nh, ti mi nt c hai ng vo nt v hai ng ra khi nt. Trong hai
ng i ra th mt ng vi bit u vo l bit 0 v ng cn li ng vi bit u
vo l bit 1.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 29
T=1 T=0
State
00
State
01
State
10
State
11
00
11
T=2
11
00
10
01
T=3
11
00
10
11
00
01
10
01
T=4
11
00
10
11
00
01
10
01
T=5
11
00
10
11
00
01
10
01
Hnh 2.9: S hnh li b m chp (2,1,3) v b pht m (7,5).
Trng thi ban u ton bng 0
*S trng thi:
S trng thi c thc hin bng cch n gin s 4 trng thi c th
c ca b m (00, 01, 10 v 11) v trng thi chuyn tip c th c to ra t trng
thi ny chuyn sang trng thi khc, qu trnh chuyn tip c th l:
Next State/output symbol, if
Current State Input = 0: Input = 1:
00 00/00 10/11
01 00/11 10/00
10 01/10 11/01
11 01/01 11/10
Kt qu ta thu c s trng thi trong hnh 2.10 nh sau:
Hnh 2.10: S trng thi ca b m chp (2,1,3)

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 30
T s trng thi hnh 2.10, cc ng lin nt c k hiu cho bit u vo
l bit 0 v ng t nt c k hiu cho cc bit u vo l bit 1. So vi s
hnh li v s hnh cy th s trng thi l s n gin nht.
2.5 u nhc im ca m chp
2.5.1 u im
Cng nh cc m sa sai khc, m chp cho php chng ta c th sa li d liu
b sai lch khi truyn qua knh truyn khi phc chnh xc tn hiu gc.
Vic thc hin m ha dng m chp tng i n gin hn cc loi m sa sai
khc m cht lng m ha li tt.
Vic thc hin m ha dng m chp c th c thc hin bng phn cng v
phn mm.
Da trn hnh thc m ha m chp cng thut gii Viterbi cho n, cc b m
ha sau ny u k tha nhng c tnh u vit ca n.
2.5.2 Nhc im
Vic m ha v gii m lin quan n m chp ch gii quyt c cc li mt
bit cn i vi cc knh truyn xut hin nhiu bit lin tip th thut ton m ha v
gii m ny s khng cn hon ho na.
Knh truyn y phi l knh truyn t nhiu, v nu knh truyn nhiu qu
ln, m ha chp s khng cn tt na. Khi ta phi cn ti tri ph tn hiu
a tn hiu xung di mc nhiu gim thiu nh hng.
2.6 inh nghia thut toan Viterbi
Thut toan Viterbi la mt giai phap c s dung ph bin giai ma chui
bit c ma hoa bi b ma hoa ti ch chp. Chi tit cu a mt b giai ma ring phu
thuc vao mt b ma ho a tich chp tng ng. Thut toan Viterbi khng phai la
mt thut toan n le co th dung giai ma nhng chui bit ma c ma hoa bi
bt c mt b ma hoa chp nao.
Thut toan Viterbi c khi xng bi Andrew Viterbi nm 1967 nh la mt
thut toan giai ma cho ma chp qua ca c tuyn thng tin s co nhiu. No c s
dung trong ca hai h thng CDMA va GSM, ca c modem s , v tinh, thng tin vu
tru, va ca c h thng mang cu c b khng dy. Hin nay con c s dung ph bin
trong ky thut nhn dang giong noi, nhn dang t ma , ngn ng hoc may tinh.
Thut ton gii m Viterbi l mt trong hai loi thut ton gii m c s
dng vi b m ha m chp- mt loi khc l gii m tun t. u im ca gii
m tun t so vi Viterbi l n c th hot ng tt vi cc m chp c chiu di
rng buc ln, nhng n li c thi gian gii m bin i.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 31
Cn u im ca thut ton gii m Viterbi l n c thi gian gii m n nh.
iu rt tt cho vic thc thi b gii m bng phn cng. Nhng m yu cu v
s tnh ton ca n tng theo hm m nh l mt hm ca chiu di rng buc, v
vy, trong thc t, ngi ta thng gii hn chiu di rng buc ca n K = 9 hoc
nh hn. Stanford Telecom to ra mt b gii m Viterbi K = 9 hot ng tc
n 96 kbps, v mt b gii m vi K = 7 hot ng vi tc ln n 45 Mbps.
Cc k thut khng dy nng cao c th to ra mt b gii m Viterbi vi K = 9
hot ng tc ln n 2 Mbps. NTT tuyn b rng h to c b gii m
Viterbi hot ng tc 60 Mbps, nhng tnh kh thi ca n vn cha c kim
chng.
2.7 Phn tch thut gii Viterbi
Chng ta s ly v d v m chp c tc m l k/n =
Hnh 2.11: B m chp tc
FF: thanh ghi dch. Ti mi xung clock, ni dung ca thanh ghi dch c dch qua
phi 1 bit. Bit u tin s l ng vo, v bit cui cng s l ng ra. Mt thanh ghi
dch c th s xem xt vic cng tr vo ng vo. Cc thanh ghi dch c th c
hiu nh l b nh ca b m ha. N ghi nh nhng bit u ca chui.
Thanh ghi dch c khi u vi tt c gi tr l 0.
Thut ton XOR: 1 1= 0; 1 0=1; 0 1=1; 0 0=0
Nu chng ta lm vic trn mt chui ng vo l 01011101, ng ra l 00 11
10 00 01 10 01 00
2
. B m ha ny cng c th c m hnh bi mt bng trng
thi hu hn. Mi mt trng thi c quy nh bi 2 bit nh phn- trng thi ca 2
thanh ghi dch. Mi mt s chuyn trng thi c quy nh bi w/v1v2 vi w i
din cho bit ng vo, v v1v2 l i din cho 2 bit ng ra, trong trng hp ny
chng ta lun lun c w = v1.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 32
Bng 2.1: Trng thi ng vo v ng ra ca b m ha tc
Next State/output symbol, if
Current State Input = 0: Input = 1:
00 00/00 10/11
01 00/11 10/00
10 01/10 11/01
11 01/01 11/10
Hnh 2.12: hnh trng thi ca m chp
By gi chng ta c th m t thut ton gii m, phn chnh l thut ton
Viterbi. C l, khi nim quan trng nht h tr cho vic hiu c thut ton
Viterbi l s Trellis. Hnh bn di cho chng ta thy s trellis cho v d
ca chng ta tc , m ha chp vi chiu di rng buc K = 3 vi bn tin 8
bit.
T=5 T=6 T=7 T=8 T=9 T=10 T=4 T=3 T=2 T=1 T=0
State 00
State 01
State 10
State 11
Hnh 2.13: Cc nhnh trong b m ha

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 33
Bn trng thi c th ca b m ha c m t nh 4 hng ca nhng du
chm theo chiu ngang. C mt ct ca 4 chm cho trng thi khi u ca b m
ha v mt mi thi im ca bn tin. Cc ng in m kt ni cc im trong
s biu din cho s chuyn trng thi khi ng vo l mt bit 1. ng chm
chm l biu din cho s chuyn trng thi khi ng vo l bit 0. Ta c th thy r s
ph hp gia s trellis v hnh trng thi ni trn.
Hnh v bn di cho ta thy trng thi trellis cho ton b 8 bit ng vo. Cc bit
ng vo b m ha v k hiu ng ra c th hin bn di ca hnh.
T=5 T=6 T=7 T=8 T=9 T=10 T=4 T=3 T=2 T=1 T=0
State 00
State 01
State 10
State 11
ENCIN =
ENCOUT =
0 1 0 1 1 1 0 1 0 0
00 11 10 00 01 10 01 00 10 11
Hnh 2.14: ng i hon chnh khi phc chnh xc tn hiu ti ng ra.
Cc bit ng vo v cc k hiu ng ra ca b m th c th xem di cng ca
hnh trn. Ch s ph hp gia cc k hiu ng ra v bng ng ra chng ta
cp trn. Hy xem xt mt cch chi tit hn, s dng phin bn m rng ca s
chuyn i t mt trng thi tc thi n mt trng thi k tip nh hnh bn di:
State
00
State
01
State
10
State
11
00
11
10
01
11
00
01
10
Gi chng ta s xem xt cch thc gii m ca thut ton Viterbi. By gi
chng ta gi s l chng ta c mt mu tin m ha (c th c vi li) v chng ta
mun khi phc li tn hiu gc.
Gi s chng ta nhn c mu tin m ha trn vi 1 bit li.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 34
T=5 T=6 T=7 T=8 T=9 T=10 T=4 T=3 T=2 T=1 T=0
State 00
State 01
State 10
State 11
ENC IN =
ENC OUT =
0 1 0 1 1 1 0 1 0 0
00 11 10 00 01 10 01 00 10 11
RECEIVED=
00 11 11 00 01 10 01 00 10 11
ERRORS= X
Hnh 2.15: Tn hiu nhn c 1 bit sai ti t =2
mi thi im chng ta nhn c 2 bit trong k hiu. Chng ta s tnh ton
thng s metric o khong cch gia nhng g m chng ta nhn c vi tt
c cc cp bit k hiu knh truyn c th m chng ta c th nhn c. i t thi
im t=0 n t=1, ch c 2 trng thi m chng ta c th nhn c l 00 v 11.
l bi v chng ta bit c b m ha tch chp bt u vi trng thi tt c u l
0 v cho 1 bit vo l 0 hay 1 th ch c 2 trng thi m chng ta c th i n v 2
ng ra ca b m ha. Nhng ng ra ny c trng thi l 00 v 11.
Thng s metric m chng ta s s dng l khong cch Hamming gia cp bit
ca k hiu nhn c v cp bit c th ca knh truyn. Khong cch Hamming
c tnh mt cch n gin bng cch m c bao nhiu bit khc gia cp bit nhn
c t knh truyn v cp bit so snh. Kt qu ch c th l 0, 1, 2. Gi tr ca
khong cch Hamming (hay thng s metric) m chng ta tnh ton mi khong
thi gian cho ng dn ca trng thi ti thi im trc v trng thi hin ti
c gi l metric nhnh (branch metric). thi im u tin, chng ta s lu
nhng kt qu ny nh l thng s metric tch ly, c lin kt n cc trng
thi. thi im th 2, thng s metric tch ly s c tnh ton bng cch cng
thm thng s metric tch ly trc vo metric nhnh hin ti.
thi im t=1, ta nhn c 2 bit 00. Ch c mt cp k hiu knh truyn
m chng ta c kh nng nhn c l 00 v 11. Khong cch Hamming gia
00 v 00 l bng 0. Khong cch Hamming gia 00 v 11 l 2. Do , gi
tr thng s metric nhnh cho nhnh ng vi s chuyn trng thi t 00 n 00
l 0 v cho nhnh t 00 n 10 l 2. Khi m thng s metric tch ly trc l
0 th thng s metric tng s chnh bng thng s metric ca nhnh va xt. Tng
t ta tnh c thng s metric cho 2 trng thi kia. Hnh bn di minh ha kt qu
ti thi im t= 1

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 35
T=1 T=0
State
00
State
01
State
10
State
11
ENCIN =
ENCOUT =
0
00
RECEIVED = 00
Accumulated
Error Metric =
0
2
00
11
Hnh 2.16: Ti thi im t = 1
iu g s xy ra thi im t=2, chng ta nhn c mt cp k hiu knh
truyn l 11, trong khi cp k hiu knh truyn m chng ta c th nhn c
l 00 nu chuyn t trng thi 00 sang trng thi 00 v 11 khi chuyn t
trng thi 00 n trng thi 10, 10 khi chuyn t trng thi 10 n trng
thi 01, 01 khi chuyn t trng thi 10 n trng thi 11. Khong cch
Hamming gia 00 v 11 l 2, gia 11 v 11 l 0, gia 01 hoc 10 vi 11 l 1.
Chng ta cng cc thng s metric mi nhnh li vi nhau. thi im t=1 th
trng thi ch c th l 00 hoc 10, thng s metric tch ly s c cng vo l 0
hoc l 2 mt cch tng ng. Hnh bn di th hin s tnh ton thng s metric
tch ly thi im t=2.
T=1 T=0
State
00
State
01
State
10
State
11
ENCIN =
ENCOUT =
0
00
RECEIVED = 00
Accumulated
Error Metric =
0+2=2
00
11
T=2
1
11
11
11
00
10
01
2+1=3
0+0=0
2+1=3
Hnh 2.17: Ti thi im t = 2
l tt c s tnh ton cho thi im t=2. ng nt m l metric nhnh
c la chn v theo cc nhnh , thng s metric l nh nht. Gi chng ta s
tnh thng s metric tch ly cho mi trng thi ti thi im t=3.
Gi chng ta hy nhn vo hnh minh ha cho thi im t=3. Chng ta s gp
phi mt t phc tp hn y, ti mi trng thi trong 4 trng thi ti t=3 s c 2

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 36
ng n t 4 trng thi ca thi im t=2. Chng ta s xoay s th no? Cu tr
li l, chng ta s tnh ton thng s metric tch ly lin quan ca mi nhnh, v
chng ta s b i gi tr metric ln hn, tc l s loi b nhnh i. Nu cp thng
s metric mi trng thi l bng nhau th chng ta s gi li c 2 trng thi. Chng
ta s k tha nhng tnh ton thc hin thi im t=2. Thut ton cng thng
s metric tch ly trc vo nhnh mi, so snh kt qu v chn thng s metric
nh hn (nh nht) tip tc dng cho thi im k tip, c gi l thut ton
cng-so snh-chn. Hnh bn di cho thy kt qu ca vic x l ti thi im t=3.
T=1 T=0
State
00
State
01
State
10
State
11
ENCIN =
ENCOUT =
0
00
RECEIVED = 00
Accumulated
Error Metric =
00
11
T=2
1
11
11
11
00
10
01
0+1, 3+1 : 1
T=3
0
10
11
11
00
10
11
00
01
10
01
2+0, 3+2 : 2
0+1, 3+1 : 1
2+2, 3+0 : 3
Hnh 2.18: Ti thi im t = 3
Ch l cp k hiu knh truyn th 3 m chng ta nhn c s c mt li.
Thng s metric nh nht hin ti l 1.
Chng ta hy xem iu g xy ra thi im t=4. Tin trnh x l cng ging
nh thi im t=3. Kt qu xem hnh bn di
T=1 T=0
State
00
State
01
State
10
State
11
ENCIN =
ENCOUT =
0
00
RECEIVED = 00
Accumulated
Error Metric =
00
11
T=2
1
11
11
11
00
10
01
2+1 , 1+1 : 2
T=3
0
10
11
11
00
10
11
00
01
10
01
3+2 , 1+0 : 1
2+1 , 1+1 : 2
3+0 , 1+2 : 3
T=4
1
00
00
11
00
10
11
00
01
10
01
Hnh 2.19: Ti thi im t = 4

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 37
Ch l thi im t=4, ng trellis ca tin tc thc s truyn i c xc
nh bng ng in m, vi thng s metric tch ly l nh nht. Hy xem xt
thi im t=5:
T=1 T=0
State
00
State
01
State
10
State
11
ENCIN =
ENCOUT =
0
00
RECEIVED= 00
00
11
T=2
1
11
11
11
00
10
01
T=3
0
10
11
11
00
10
11
00
01
10
01
T=4
1
00
00
11
00
10
11
00
01
10
01
Accumulated
Error Metric =
1+0 , 2+2 : 1
3+1 , 2+1 : 3
1+2 , 2+0 : 2
3+1 , 2+1 : 3
T=5
1
01
01
11
00
10
11
00
01
10
01
Hnh 2.20: Ti thi im t = 5
thi im t=10, s trellis s nh th ny, cc nhnh ko c chn c
b i:
T=5 T=6 T=7 T=8 T=9 T=10 T=4 T=3 T=2 T=1 T=0
State 00
State 01
State 10
State 11
ENC IN =
ENC OUT =
0 1 0 1 1 1 0 1 0 0
00 11 10 00 01 10 01 00 10 11
RECEIVED = 00 11 11 00 01 10 01 00 10 11
ERRORS= X
Hnh 2.21: Tt c d liu c gii m v sa sai chnh xc
Kt qu y cho thy chng ta gii m ng chui d liu gc. Nu chng
ta nhn li con ng chng ta tm ra d liu gc l bng cch so snh d liu
nhn c vi d liu so snh ca b gii m c c t bng trng thi. iu ny
cho thy chng ta ang s dng thut ton gii m da trn s ging nhau ln nht.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 38
Vic x l gii m bt u vi xy dng mt thng s metric tch ly cho mt s
cp k hiu knh truyn nhn c, v lu gi trng thi mi thi im t m
thng s metric l nh nht. Mt khi thng tin ny c dng ln th b gii m
viterbi sn sng khi phc li chui bit a vo b m ha chp, khi mu tin
c m ha truyn i. iu ny t c bng nhng bc sau:
o u tin, chn mt trng thi c thng s metric nh nht v lu li
s trng thi ca trng thi .
o S dng lp li cho nhng bc k tip mi cho n khi bt u ca
trellis t c: da vo bng ghi nh trng thi cho trng thi c
chn, chn mt trng thi mi c lit k trong bng ghi nh trng
thi khi chuyn t trng thi trc n trng thi . Lu s trng thi
ca mi trng thi c chn. Bc ny c gi l truy hi
(traceback).
o Chng ta lm vic tip vi danh sch nhng trng thi c chn c
lu trong bc x l trc . Chng ta tra xem bit ng vo no ph hp vi
s truyn dn t mi trng thi trc n trng thi k tip. y l bit m
phi c m ha bng m tch chp.
Bng sau cho chng ta thy ma trn tch ly ca y 8 bit (cng vi 2 bit ph
thm) ca bn tin mi thi im t:
Bng 4.2: Bng ma trn tch ly ca c 8 bit ca bn tin
Ch rng v d v b gii m Viterbi ng vo quyt nh cng ny, thng
s metric tch ly nh nht trng thi cui ch ra c c bao nhiu li k hiu
knh truyn xy ra.
Bng lch s trng thi bn di cho thy trng thi tn ti trc cho mi trng
thi ti thi im t:

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 39
Bng 2.3: Bng lch s trng thi
Tng ng 0,1,2,3 l cc v tr 00,01,10,11
2
.
Bng sau cho thy trng thi c la chn khi truy hi ng dn t bng trng
thi tn ti trn:
Bng 2.4: Bng cc trng thi c la chn khi truy hi
S dng bng ta thy c s chuyn i trng thi n cc ng vo gy ra chng,
gi chng ta c th to li bn tin gc. Bng ny rt ging vi v d ca chng ta
b m ha chp tc v K= 3.
Bng 2.5: Bng trng thi k tip

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 40
Ghi ch: trong bng trn, x ch ra l mt s chuyn trng thi khng th xy ra
t mt trng thi n mt trng thi khc.
By gi chng ta c tt c cc cng c cn thit ti to li bn tin gc t bn
tin m chng ta nhn c.
Bng 2.6: Bng cha cc d liu ca bn tin gc c khi phc
Hai bit ph c b qua.
Lm th no m thut ton truy hi cui cng cng tm ra con ng i ng
nht ca n thm ch nu n chn trng thi ban u l sai. iu ny c th xy ra
nu c hn mt trng thi c thng s metric tch ly l nh nht. Chng ta s dng
li hnh 2.18 lm sng t iu ny:
T=1 T=0
State
00
State
01
State
10
State
11
ENCIN =
ENCOUT =
0
00
RECEIVED = 00
Accumulated
Error Metric =
00
11
T=2
1
11
11
11
00
10
01
0+1 , 3+1 : 1
T=3
0
10
11
11
00
10
11
00
01
10
01
2+0 , 3+2 : 2
0+1 , 3+1 : 1
2+2 , 3+0 : 3
thi im t=3, c 2 trng thi 01 v 11 u c thng s metric l 1.
ng i ng i n trng thi 01, ch l ng in m l ng i thc s
ca bn tin n trng thi ny. Nhng gi s chng ta chn trng thi 11 bt
u qu trnh truy hi ca chng ta. Trng thi trc ca trng thi 11 l trng
thi 10, cng l trng thi trc ca trng thi 01. iu ny l bi v thi
im t=2, trng thi 10 c thng s metric tch ly l nh nht. V vy, sau trng
thi bt u sai, chng ta c th ngay lp tc tr li vi tuyn ng ng.
Vi v d v bn tin 8 bit, chng ta tin hnh xy dng mt s trellis cho
ton b bn tin trc khi bt u qu trnh truy hi. Vi cc bn tin di hn hoc
cc chui d liu lin tc, iu ny l khng thc t, bi v b nh chiu di rng
buc v s tr hon trong gii m. Nghin cu cho thy l su truy hi ca Kx5
ch cho vic gii m viterbi vi loi b m m chng ta ang tho lun. Bt c

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 41
mt s truy hi su hn s lm tng thi gian delay gii m v b nh yu cu cho
vic gii m v cng ko lm tng hiu qu vic gii m, ngoi tr b m ha thng
(punctured code) m chng ta s ni sau.
thc thi mt b gii m Viterbi bng phn mm, bc u tin l phi xy
dng mt vi cu trc d liu xoay quanh thut gii m s c thc thi. Nhng
cu trc d liu ny c thc thi tt nht khi l cc mng. Su mng chnh m
chng ta cn cho b gii m viterbi l:
- Mt bn sao ca Bng tri thi k tip ca b m ha
m chp, bng chuyn trng thi ca b m ha. Kch
c ca bng ny (hng x ct) l 2
(K-1)
x 2
K
. Mng ny
phi c khi u trc khi bt u tin trnh gii m.
- Mt bn sao ca bng ng ra ca b m ha m chp.
Kch c ca bng ny l 2
(K-1)
x 2
K
. Mng ny cng cn
phi c khi u trc khi bt u tin trnh gii m.
- Mt mng lu tr trng thi hin ti v trng thi k
ca b m ha m chp, vi gi tr ng vo (0 hoc 1) s
cho ra trng thi k tip v trng thi hin ti. Chng ta
s gi bng ny l bng ng vo. Kch thc ca bng
l 2
(K-1)
x 2
(K-1)
. Mng ny cng cn phi c khi u
trc khi bt u tin trnh gii m.
- Mt mng lu tr lch s cc trng thi trc cho
mi trng thi ca b m ha cho Kx5 + 1 cp k hiu
knh truyn nhn c. Chng ta s gi bng ny l
bng lch s trng thi. Kch thc ca mng ny l
2
(K-1)
x (Kx5 +1). Mng ny khng cn khi ng trc
khi bt u tin trnh gii m.
- Mt mng lu tr thng s metric tch ly cho mi
trng thi c tnh ton s dng nguyn tc cng- so
snh- la chn. Mng ny s c gi l mng thng
s metric tch ly. Kch thc ca mng ny l 2
(K-1)
x
2. Mng ny khng cn khi ng trc khi bt u tin
trnh gii m.
- Mt mng dng lu tr danh sch cc trng thi
c quyt nh trong sut qu trnh truy hi. N c
gi l mng chui trng thi. Kch thc ca mng
ny l (Kx5 + 1). Mng ny khng cn khi ng trc
khi bt u tin trnh gii m.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 42
Gi chng ta hy ni v tc ca nhng b m ha chp m c th c gii
m bi cc b gii m Viterbi. trn chng ta cp n b m ha thng, l
mt hng chung ca b m ha tc cao, tc ln hn t k n n. Punctured
code c to ra bi d liu m ha u tin s dng mt b m ha tc 1/n
nh l b m ha th d c m t trc y v sau xa b mt vi k hiu
knh truyn ng ra ca b m ha. Qu trnh ny c gi l puncturing. V d,
to ra m tc t m tc , th n gin l s xa k hiu knh truyn
theo mu punctured sau y:
Bng 2.7: V d v punctured code
Trong , bit 1 ch ra rng mt k hiu knh truyn s c truyn, v bit
0 ch ra rng mt k hiu knh truyn s c xa. xem lm th no m
vic ny c th to ra b m tc . Hy ngh l mi ct ca bng trn tng ng
vi mt bit ng vo n b m ha v mi mt bit 1 trong bng tng ng vi
mt k hiu knh ng ra. C 3 ct trong bng v 4 bit 1. Thm ch bn c th
to ra b m tc 2/3 s dng mt b m ha vi mu puncturing sau:
vi 2 ct v 3 bit 1.
gii m mt punctured code, bit 1 phi thay th nhng k hiu rng cho
nhng k hiu b xa ng vo ca b gii m Viterbi. K hiu rng c th l k
hiu c lng t n mc 1 yu v mc 0 yu hoc hn na c th l mt k
hiu c c bit, m khi c x l bng mch ACS trong b gii m, kt qu l
khng thay i thng s metric tch ly t trng thi trc.
D nhin, n khng phi bng 2. V d, mt m tc 1/3 v K=3 (7,7,5) c
th c m ha s dng b m ha nh bn di:

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 43
Hnh 2.22: B m tc 1/3 v K= (7,7,5)
B m ha ny c 3 b cng modulo, v vy vi mi mt bit ng vo, c th to ra
3 ng ra k hiu knh truyn. D nhin, vi mu puncturing ph hp, bn c th to
ra nhng m tc cao hn s dng b m ha ny.
2.8 Gii m quyt nh cng v gii m quyt nh mm
Gii m quyt nh mm v quyt nh cng da vo loi lng t ha c s
dng cc bit nhn c. Gii m quyt nh cng s dng loi lng t ha 1 bit
trn cc gi tr knh nhn c. Gii m quyt nh mm s dng loi lng t ha
nhiu bit trn cc gi tr knh nhn c. i vi gii m quyt nh mm l tng
(lng t ha khng xc nh), cc gi tr knh nhn c c s dng trc tip
trong b gii m ha knh. Hnh 2.23 biu din gii m quyt nh cng v quyt
nh mm.
Hnh 2.23: Gii m quyt nh cng v mm
2.8.1 Thut ton Viterbi quyt nh cng
i vi m tch chp, chui ng vo c xon thnh chui m ha c. Chui c
c pht xuyn qua knh nhiu v chui nhn c l chui r. Thut ton Viterbi
l thut c on kh nng xy ra ln nht (Maximum Likelihood-ML) cho ra
chui m ha c c on y t chui nhn c r cho chui ny t c xc

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 44
xut p(r/y) ln nht. Chui y phi l mt trong nhng chui m ha cho php v
khng th l bt k chui ty no.
Hnh 2.24 trnh by cu trc h thng
Hnh 2.24: H thng m tch chp
i vi mt m tch chp c tc r, cc ng vo ca b m ha k bit song
song v cc ng ra n bit song song ti mi bc. Chui ng ra l
0 0 0 1 1 1 1 1
(1), (2), ..., ( ), (1), (2), ..., ( ), (1), ..., ( )
l m l m
x x x x k x x x k x x k
+ +
(2.8.1)
V chui c m ha l
0 0 0 1 1 1 1 1
(1), (2), ..., ( ), (1), (2), ..., ( ), (1), ..., ( )
l m l m
c c c c n c c c n c c n
+ +
(2.8.2)
Trong L l chiu di ca chui tin ng vo v m l chiu di ln nht ca cc
thanh ghi dch. Yu cu phi thm vo ui ca chui m ha vi m bit zero cho
b m ha tch chp tr v trng thi tt c zero. Yu cu b m ha phi bt u v
kt thc ti trng thi tt c zero. Cc ch s bn di l ch s thi gian v cc ch
s bn trn l bit ch ra khi k bit ng vo hay n bit ng ra ring l. Cc chui c
c on y v chui nhn c r c th c m t tng t.
1 1
(1) ( 2 ) ( ) (1) ( 2 ) ( ) (1) ( )
1 1 1
, , ..., , , , ..., , , ...,
l m l m
n n n
o o o
r r r r r r r r r
+ +
1

]
(2.8.3)
V
1 1
(1) ( 2 ) ( ) (1) ( 2) ( ) (1) ( )
1 1 1
, , ..., , , , ..., , , ...,
l m l m
n n n
o o o
y y y y y y y y y
+ +
1

]
(2.8.4)
i vi gii m ML, thut ton Viterbi chn y P(r/y) ln nht. Gi thit knh
l khng nh, v v vy qu trnh nhiu nh hng ln bit nhn c c lp vi
qu trnh nhiu nh hng ln tt c cc bit khc. T l thuyt xc sut (xc sut
lin kt), xc sut ca tp hp cc s kin c lp tng ng vi tnh xc sut ca
cc s kin ring l. V vy,
( )
( ) ( ) ( )
1
(1) (1) ( 2 ) ( 2 ) ( ) ( )
0
| | | .... |
L m
n n
i i i i i i
i
p r y p r y p r y p r y
+

(2.8.5)

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 45
( )
( )
1
( ) ( )
0 1
| |
L m n
j j
i i
i j
p r y p r y
+

_


,

(2.8.6)
Biu thc ny c gi l hm c kh nng xy ra ca y vi r nhn c. Vic
c on P(r/y) ln nht cng l logP(r/y) ln nht bi v cc hm logarit l cc
hm tng u. V vy, mt hm log ca kh nng xy ra c th c nh ngha log
log(/),
( )
1
( ) ( )
0 1
log ( | ) log |
l m n
j j
i i
i j
p r y p r y
+

_


,

(2.8.7)
V thao tc trn cc tng d dng hn thao tc trn cc hm log nn mt metric
bit c nh ngha nh sau:
( ) ( )
( ) ( ) ( ) ( )
| log |
j j j j
i i i i
M r y a p r y b
1
+
]
(2.8.8)
Trong a v b c chn trc cho metric bit l mt s nguyn dng nh
nht. Cc gi tr a v b c nh ngha cho knh h thng nh phn (BSC) hay gii
m quyt nh cng. Hnh 2.25 trnh by mt BSC
Hnh 2.25: Kiu knh h thng nh phn, trong p l xc sut cho
i vi BSC a v b c th c chn theo 2 cch phn bit. Theo cch thng
thng a v b c chn nh sau:
(2.8.9)
V
(2.8.10)

Kt qu metric bit l
(2.8.11)

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 46
T kiu BSC, r rng ch ly gi tr p v 1-p. Bng 2.8 trnh by kt qu metric bit
Bng 2.8: Cc gi tr metric bit thng thng
Bit nhn Bit nhn
Bit c gii m
0 1
Bit c gii m
1 0
Metric bit ny biu din c lng ca cc bit gii m v cc bit nhn. V d
nu bit c gii m y
i
(j)
= 0 v bit nhn c r
i
(j)
= 0 th c lng M(y
i
(j)
| r
i
(j)
) = 0.
Tuy nhin, nu bit c gii m y
i
(j)
= 0 v bit nhn c r
i
(j)
= 1 th c lng
M(y
i
(j)
| r
i
(j)
) = 1. Nh vy iu ny lin quan n khong cch Hamming v c
bit nh l metric ca khong cch Hamming. V vy, thut ton Viterbi chn chui
m y qua trellis c c lng/khong cch Hamming nh nht lin quan n chui
nhn c r.
Cch khc a v b c th c chn nh sau:
(2.8.12)
V
(2.8.13)
Kt qu metric bit cch 2 l
(2.8.14)
Bng 2.9: Cc gi tr metric bit cch 2
Bit nhn Bit nhn

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 47
Bit c gii m
1 0
Bit c gii m
0 1
i vi trng hp ny thut ton Viterbi chn chui m ha y qua trellis c
c lng/khong cch Hamming ln nht i vi chui nhn c r. Hn na,
i vi mt knh ty (khng nht thit l BSC), cc gi tr a v b c tm theo
nguyn tc th- v sai ly metric bit c th chp nhn c.
T metric bit, metric ng c nh ngha l:
(2.8.15)
V ch ra tng c lng ca vic c on chui bit nhn c r vi chui bit
c m ha y trong s d trellis. Hn na metric nhnh th K c nh ngha
nh sau:
(2.8.16)
V metric ng thnh phn c nh ngha nh sau:
(2.8.17)
Do :
(2.8.18)
Metric nhnh th k ch ra vic c lng chn mt nhnh t biu trellis.
Metric ng th k ch ra vic c lng chn mt chui bit c m ha tng
phn y ti ch s thi gian k.
Thut ton Viterbi s dng biu trellis tnh cc metric ng. Mi trng
thi (nt) trong biu trellis c gn mt gi tr gi l metric ng thnh phn.
Metric ng tng phn c xc nh t trng thi s = 0 ti thi im t = 0 n

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 48
mt trng thi c bit s = k ti thi im t >= 0. Ti mi trng thi metric ng
tng phn tt nht c chn t cc ng kt thc ti trng thi . Metric ng
tng phn tt nht, c th l metric ln nht hay nh nht ph thuc vo a v b c
chn theo cch thng thng hay chn la khc. Metric c chn din t bng
ng tn ti (survivor) v cc metric cn li c din t bng ng khng ph
hp (nonsurvivor). Cc ng tn ti c lu li trong khi cc ng khng ph
hp b loi b trong s trellis. Thut ton Viterbi chn ng tn ti n gin i
t cui ca tin trnh ging nh ng ML. Sau truy ngc theo ng ML
trong biu trellis s tm c chui gii m ML.
Thut ton Viterbi quyt nh cng c th c thc hin nh sau:
S
k,t
l trng thi trong biu trellis tng ng vi trng thi S
k
ti thi im t.
Mi trng thi trong Trellis c gn mt gi tr l V(S
k,t
).
1. (a) khi to t = 0
(b) khi to V(S
0,0
) = 0 v tt c cc V khc V(S
k,t
) = +oo
2. (a) ly t = t+1
(b) Tnh cc metric ng tng phn cho tt c ng i n trng thi S
k
ti thi im t.
u tin, tm metric nhnh th t
(2.8.19)
Metric ny c tnh t khong cch Hamming
(2.8.20)
Th hai, tnh metric ng thnh phn th t
(2.8.21)
Metric ny c tnh t
3. a) Ly V(S
k,t
) n metric ng tng phn tt nht l trng thi S
k
ti
thi im t. Thng thng, metric ng tng phn tt nht l metric
ng tng phn c gi tr nh nht
(b) Nu c mt nt TIE nm trn metric ng tng phn tt nht, sau
bt k mt metric ng tng phn c th c chn.
4. Lu tr metric ng tng phn v cc v cc ng trng thi cng
vi bit tn ti lin kt ca n.
5. Nu t < L+m-1, tr v bc 2.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 49
Kt qu ca thut ton Viterbi l mt ng Trellis duy nht tng ng
vi t m ML.
V d: Biu chuyn tip trng thi trnh by cc bit tin v cc bit m ha
c c on theo cc nhnh (cn thit cho qu trnh gii m ). Vic gii m chn
ng ML thng qua trellis nh c trnh by trong hnh 2.26. Metric ng tng
phn (c lu tr) c chn cho v d ny l khong cch Hamming ln nht v
c trnh by trong hnh cho mi nt. Cc metric ng tng phn m tng ng
vi ML. Cc ng tn ti c biu din bi cc ng lin nt m v cc ng
cnh tranh c biu din bi cc ng nt t.
Hnh 2.26: Biu din Viterbi theo v d
2.8.2 Thut ton Viterbi quyt nh mm
C 2 phng php tng qut thc hin thut ton Viterbi quyt nh mm.
Phng php th nht (phng php 1) s dng metric khong cch Euclidean thay
cho metric khong cch Hamming. Cc bit nhn s dng trong metric khong cch
Euclidean c x l bng lng t ha nhiu mc. Phng php th hai (phng
php 2) s dng mt metric tng quan trong cc bit nhn c ca n dng
trong metric ny cng c x l bng lng t ha nhiu mc.
2.8.2.1 Thut ton Viterbi quyt nh mm (phng php 1)
Trong gii m quyt nh mm, b thu khng gn 0 hay 1 (lng t ha bit
n) cho mi bit nhn c m s dng cc gi tr lng t ha nhiu bit hay bit
khng xc nh. L tng, chui thu r c lng t ha bit khng xc nh v
c s dng trc tip trong b gii m quyt nh mm. Thut ton Viterbi quyt
nh mm tng t vi thut ton quyt nh cng ngoi tr khong cch Euclidean
bnh phng c s dng trong metric thay cho khong cch Hamming.
Thut ton Viterbi quyt nh mm c th c thc hin nh sau

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 50
S
k, t
l trng thi trong biu trellis tng ng vi trng thi S
k
ti thi im t.
Mi trng thi trong trellis c gn mt gi tr l V(S
k, t
).
1. (a) khi to t = 0
(b) Khi to V(S
0, 0
) = 0 v tt c cc V khc V(S
k, t
) = +00
2. (a) Ly t = t + 1
(b) Tnh cc metric ng thnh phn cho tt c cc ng i n trng thi
S
k
ti thi im t.
u tin tm metric nhnh th t
(2.8.22)
Metric ny c tnh t khong cch Euclidean
(2.8.23)
Th 2, tnh metric ng tng phn th t
(2.8.24)
Metric ny c tnh t
(2.8.25)
3. (a) Gn V(S
k,
t ) cho metric ng tng phn tt nht l trng thi S
k,
ti thi
im t. Thng thng metric ng tng phn tt nht l metric ng tng
phn c gi tr nh nht.
(b) Nu c mt TIE cho mt metric ng tng phn tt nht, th sau bt
k mt trong nhng metric ng tng phn c th c chn.
4. Lu tr metric ng tng phn v cc ng trng thi v cc bit tn ti
lin kt ca n.
5. Nu t <= L+m -1, tr v bc 2.
2.8.2.2 Thut ton Viterbi quyt nh mm (phng php 2)
Thut ton viterbi quyt nh mm th 2 c trnh by bn di. Hm kh
nng xy ra c biu din bng hm mt xc sut Gaussian
(2.8.26)
Trong E
b
l nng lng nhn c /bit ca t m v N
0
l mt ph nhiu
mt pha. Bit nhn c l bin ngu nhin Gaussian c trung bnh l v
phng sai l N/2. Hm log ca kh nng xy ra c th c nh ngha l:

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 51

Trong
Trong C1 v C2 l hng s, khng phi l hm ca y
(2.8.28)
T y metric bit c nh ngha l
(2.8.29)
Thut ton Viterbi quyt nh mm c th c thc hin nh sau:
S
k, t
l trng thi trong biu trellis tng ng vi trng thi S
k
ti thi im t.
Mi trng thi trong trellis c gn mt gi tr l V(S
k, t
).
1. (a) Khi to t = 0
(b) Khi to V(S
0, 0
) = 0 v tt c cc V khc V(S
k, t
) = +00
2. (a) Ly t = t + 1
(b) Tnh cc metric ng thnh phn cho tt c cc ng i n trng thi
S
k
ti thi im t.
u tin tm metric nhnh th t
(2.8.30)
Metric ny c tnh t s tng quan ca v , .

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 52
Th 2, tnh metric ng tng phn th t
(2.8.31)
Metric ny c tnh t
(2.8.32)
3. (a) Ly V(S
k,t
) n metric ng tng phn tt nht l trng thi S
k
ti thi
im t. Metric ng tng phn tt nht l metric ng tng phn c gi tr
ln nht.
(b) Nu c mt thay i cho metric ng thnh phn tt nht, th sau bt
k mt trong nhng metric ng tng phn c th c chn.
4. Lu tr metric ng tng phn v cc ng trng thi v cc bit tn ti
lin kt ca n.
5. Nu t < L + m 1, tr v bc 2.
Thng thng i vi gii m quyt nh mm, trong knh nhiu Gaussian th
li m ha khong 2dB so vi gii m quyt nh cng.
2.8.3 u im ca gii m quyt nh mm so vi gii m quyt nh cng
Vi vic thut ton gii m quyt nh mm chia ra nhiu mc nhn dng
tn hiu thu c th tin cy gii m s m bo hn so vi gii m quyt nh
cng ch c 2 mc duy nht cho tn hiu nhn c.
thy r u im ca thut ton quyt nh mm so vi quyt nh cng,
chng ta xt mt v d n gin s dng b m parity sau:
Bng 2.10: V d vi b m parity
Bit vo 1 Bit vo 2
Bit parity c to
bi b m ha
T m
0 0 0 0
0 1 1 011
1 0 1 101
1 1 0 110
Tt c cc trng thi c th c to bi b m ha l 000, 011, 101, 110.
By gi chng ta s tin hnh truyn bn tin 01 xuyn qua knh truyn.

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 53
i vi gii m quyt nh cng:
Gi s h thng thng tin ca chng ta bao gm mt b m ha to kim
parity, knh truyn, v mt b thu gii m quyt nh cng
Vi bn tin 01 a n b m ha parity, t m ng ra ta nhn c s l 011,
Hnh 2.27 M t gii m quyt nh cng vi b m parity
T m ny gi s s c truyn qua knh truyn nh sau: 0 c truyn
di dng in p 0 volt, 1 c truyn vi in p 1 volt. Knh truyn c
nhiu s lm suy gim tn hiu v tn hiu thu c ti b nhn s b suy gim (dng
sng mu ). B gii m quyt nh cng thc hin quyt nh da trn mt mc
in p ngng. Vi trng hp ny, in p ngng ca chng ta s l 0,5 volt
(nm gia cc mc 0V v 1V). mi thi im ly mu ca b thu (nh hnh trn),
b tch sng quyt nh cng s quyt nh trng thi l mc 0 nu mc p thu
c l nh hn 0,5V v s chn l mc 1 nu p thu c ln hn 0,5V. Do
, ng ra ca khi quyt nh cng trn s l 001. C l ng ra 001 ny l v
l khi so snh vi cc t m c th nh bng trn, do , cc bit ca t m trn c
th sai do tc ng trn knh truyn. B gii m quyt nh cng so snh ng ra
ca khi gii m quyt nh cng trn vi tt c cc trng thi c th ca t m v
tnh ton khong cch Hamming b nht cho mi trng hp. M t nh bng bn
di:
Bng 2.11: Tnh ton khong cch Hamming cho quyt nh cng
Tt c t m c th Ng ra quyt nh
cng
Khong cch
Hamming
000 001 1
011 001 1
101 001 1

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 54
110 001 3
Cng vic ca b gii m l chn ta t m pht i da trn khong cch
Hamming b nht. Tuy nhin, y c ti 3 trng hp cho ra khong cch
Hamming u l 1. Do , b gii m c th s chn ngu nhin mt trong 3 trng
hp trn lm quyt nh cui cng. V vy, xc xut ng ch l 1/3.
i vi b gii m quyt nh mm:
S khc bit ch yu ca thut ton quyt nh cng v quyt nh mm nh
ta bit chnh l thut ton gii m quyt nh mm s dng khong cch
Euclidean thay v khong cch Hamming.
Vi cng mt b m ha v knh truyn, gi ta s xem hiu qu ca quyt
nh mm so vi quyt nh cng.
Hnh 2.28 M t gii m quyt nh mm vi b m parity
Mc in p ca tn hiu nhn c ti mi thi im ly mu nh hnh trn.
Khi quyt nh cng tnh ton khong cch Euclidean ca tt c cc t m c th
vi tn hiu nhn c.
Bng 2.12: Tnh ton khong cch Euclidean cho quyt nh mm
T m c th
Mc in p ti mi
thi im ly mu ca
dng sng nhn c
Tnh ton khong
cch Euclidean
Khong cch
Euclidean
0 0 0
( 0V 0V 0V )
0.2V 0.4V 0.7V
(0-0.2)
2
+ (0-0.4)
2
+
(0-0.7)
2
0.69
0 1 1
( 0V 1V 1V )
0.2V 0.4V 0.7V
(0-0.2)
2
+ (1-0.4)
2
+
(1-0.7)
2
0.49

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 55
1 0 1
( 1V 0V 1V )
0.2V 0.4V 0.7V
(1-0.2)
2
+ (0-0.4)
2
+
(1-0.7)
2
0.89
1 1 0
( 1V 1V 0V )
0.2V 0.4V 0.7V
(1-0.2)
2
+ (1-0.4)
2
+
(0-0.7)
2
1.49
Khong cch Euclidean b nht l 0,49 tng ng vi t m 011, chnh l
t m m chng ta truyn i. B gii m quyt nh mm s chn n lm t m
gii c ng ra, nu b to kim parity khng th sa li th lu gii m
quyt nh mm ny s gip khi phc tin tc trong trng hp ny.
Qua v d trn ta c th thy c u im ca gii m quyt nh mm so
vi gii m quyt nh cng. Tuy nhin, vi trng hp trn, ngi ta cng c th
nhanh chng tm ra li ca phng php x l ny nu cc mc in p tng ng
l 0,2V, 0,4V v 0,6V. l bi v b to kim parity khng c kh nng sa li
m ch c th pht hin li 1 bit. Khi , s dng b gii m quyt nh mm s
nng cao hiu qu ca b nhn chng 2 dB so vi b gii m quyt nh cng.
2.9 Xc sut li
C 2 xc sut li lin quan n m tch chp, l xc sut li s kin u tin v
xc sut li bit. Xc sut li s kin u tin, P
e,
l xc sut li m mt li bt u
ti thi im c bit. Xc sut li bit, P
b
, l s cc li bit chui c m ha.
i vi gii m quyt nh cng, xc sut li bit v xc sut li s kin u tin
c nh ngha nh sau:
(2.9.1)
V
(2.9.2)
Trong ,
(2.9.3)
V
(2.9.4)
i vi gii m quyt nh mm, xc sut li s kin u tin v xc sut li bit
c nh ngha nh sau:
(2.9.5)
V

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 56
(2.9.6)
2.10 u nhc im ca thut ton gii m Viterbi
2.10.1 u im
Thut ton Viterbi l thut gii m c nh nn vic gii m c chnh xc
cao.
Tc x l ca m gii m Viterbi cao hn nhiu so vi b gii m tun t
v cng mt thi im, b gii m Viterbi gii quyt ht tt c cc nhnh
cn b gii m tun t ch chn ngu nhin mt nhnh nn n s mt thi
gian nu s la chn trc l khng ng.
2.10.2 Nhc im
Thut ton gii m Viterbi da trn thut gii m ging nhau ln nht (ML-
Maximum likelihood), thut ton ny li phi da trn cc nguyn l sau
vic gii m c chnh xc:
Li xy ra phi khng thng xuyn, xc sut li phi nh
Xc sut li kp phi thp hn nhiu so vi li 1 bit, do li phi
c phn b mt cch ngu nhin.
Do vy, vi knh truyn c xc sut li ln v thng xuyn, li nhiu bit
lin tip th hiu qu ca vic gii m s khng nh mong mun.
Mt nhc im na l thut ton gii m Viterbi s dng b nh ghi li
cc trng thi v thng s metric nn cn c b nh cho gii m, b gii m
cng phc tp th dung lng b nh cng ln.
Khng thch hp vi cc m c chiu di rng buc di v t s S/N ln (ch
thch hp vi b gii m tun t).

Chng 2: Thut gii m Viterbi
Thc hin b gii m Viterbi trn FPGA Trang 57
CHNG 3
M PHNG THUT GII M VITERBI
BNG MATLAB
3.1 Gii thiu
Matlab l mt phn mm c ng dng rng ri trong nhiu lnh vc nh vin
thng, c in, h thng iu khin t ng , trong ng dng m phng x l
tn hiu trong vin thng l mt ng dng mnh nht ca Matlab. Matlab tch hp
khong hn 400 hm cho php ngi lp trnh s dng cho cng vic mt cch hiu
qu v nhanh chng.
Vi ti ny, m phng qu trnh m ha dng m chp, truyn tn hiu trn
knh truyn c nhiu v s dng thut ton Viterbi gii m ha, ngi thc hin
ti s dng cc hm c sn trong Matlab thc hin. d dng hn cho
vic quan st v trnh by, tc gi s dng giao din ha GUI m phng
thut gii viterbi. Qu trnh m phng s c trnh by r rng trong phn sau.
3.2 S khi h thng
Hnh 3.1: S khi h thng
Tn hiu sau khi c s ha thnh cc bit, cc bit ny c a n b m ha
m chp. Sau khi c m ha, tn hiu (cc bit) c truyn trn knh truyn c
nhiu, y tc gi ch xt nhiu Gauss trng. Tn hiu b thay i bi nhiu
c thu v gii m nh b gii m Viterbi. Nh thut ton Viterbi, tn hiu c
gii m s gn ging nht vi tn hiu ban u.

Chng 3: M phng thut ton Viterbi dng Matlab
Khi m ha
m chp
Khi gii m
Viterbi
Ng ra bit
Ng vo
bit
Bit
m
ha
Bit
nhn
c
AWGN
Knh truyn
Thc hin b gii m Viterbi trn FPGA Trang 58
3.3 Lu m phng
Hnh 3.2: Lu m phng
3.3.1 Khi to bit ng vo
Tc gi a ra hai la chn cho vic to bit tn hiu ng vo. Th nht l to bit
ngu nhin theo s lng bit nhp t ngi dng, v th hai l nhp trc tip chui
bit vo.
to bit vo ngu nhin, trong Matlab tc gi s dng hm randint.
inbits = randint(1, numbit ) ;
vi inbits l chui bit ng vo, numbit l s lng bit ng vo c nhp bi
ngi dng trn giao din GUI. Hm randint vi 2 thng s s mc nh to mt

Chng 3: M phng thut ton Viterbi dng Matlab
M ha m
chp
Cng nhiu
Gauss trng
Lng t bit
nhn c
Gii m
Viterbi
Tnh v v
BER
Xy dng s
trellis
Xc nh a thc sinh
v chiu di rng buc
To bit
Khi to
bit ng vo
Khi
m
ha
Khi
gii
m
Thc hin b gii m Viterbi trn FPGA Trang 59
ma trn s nh phn vi chiu ca ma trn tng ng vi 2 thng s . Kch
thc ti a c th to ra ph thuc vo b nh dnh cho chng trnh. Vi cu
lnh nh trn th numbit ti a ch l 10
6
.
3.3.2 Khi m ha
i vi b m ha m chp, nh gii thiu, c rt nhiu cch ngi ta quy
c cho mt b m ha m chp da trn s thanh ghi, ng vo, ng ra, a thc
sinh, tc b m..v.v. v tng ng vi mi b m c mt phng php tnh
ton ring.
y tc gi m t vic tnh ton m chp da trn b m c quy c bi cc
nh sn xut chip thc hin m chp bao gm cc thng s: chiu di rng buc K
v tc ca b m R.
V G1 v G2 l cc a thc sinh, c nhp bi ngi s dng.
to s trellis, trong Matlab tc gi s dng hm poly2trellis:
trellis = poly2trellis (len, [g1 g2]);
Dng hm convenc m ha m chp tn hiu:
encbits = convenc(inpbits,trellis);
3.3.3 Khi cng nhiu Gausse trng
Khi ny m phng cho vic tn hiu b can nhiu khi truyn trn knh truyn.
Tn hiu b cng nhiu Gauss vi thng s SNR xc nh trc.
S dng hm awgn cng nhiu vo tn hiu:
awgnbits = awgn(encbits,snr,measured);
3.3.4 Khi gii m
Tn hiu sau khi c cng nhiu c a n b thu, ti y tn hiu c
lng t trc khi s dng thut ton viterbi gii m. Ty vo kiu quyt nh
gii m m s dng cc lng t khc nhau.
Vi quyt nh cng
Tn hiu thu c lng t v 2 mc 0 v 1 tng ng vi tn hiu c mc in
p nh hn v ln hn 0. S dng hm quantiz lng t tn hiu.
partition = [0];
codebook = [0 1];
quanbits = quantiz(awgnbits,partition,codebook);
S dng hm vitdec vi quyt nh cng gii m Viterbi
decbits = vitdec(quanbits,trellis,numbit-1,term,hard);

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 60
Vi quyt nh mm
Tn hiu thu c lng t v 8 mc v vic s dng hm quantiz nh sau
partition = [-.8571 -.5714 -.2857 0 .2857 .5714 .8571];
codebook = [-.99 -.8571 -.5714 -.2857 0 .2857 .5714 .8571];
quanbits = quantiz(awgnbits,partition,codebook);
S dng hm vitdec vi quyt nh mm
decbits = vitdec(quanbits,trellis,numbit -1,term,soft,3);
3.3.5 Tnh ton v v BER
T s bit li l s t s bit li sau khi gii m so vi tng s bit ng vo. Trong
matlab tc gi s dng hm semilogy v BER
semilogy(Eb_N0_dB,ratioerr_comp,mp-,LineWidth,2);
3.4 Hnh nh v chng trnh m phng
Hnh 3.3: Giao din khi u chng trnh m phng

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 61
Hnh 3.4: Giao din chng trnh m phng 1
Hnh 3.5: Giao din chng trnh m phng 2

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 62
Hnh 3.6: Nhp bit ngu nhin Quyt nh mm
Hnh 3.7: BER ca quyt nh mm

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 63
Hnh 3.8: Nhp bit ngu nhin Quyt nh cng
Hnh 3.9: BER ca quyt nh cng

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 64
Hnh 3.10: So snh BER ca c quyt nh cng v mm
Hnh 3.11: T nhp bit vo Quyt nh mm

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 65
Nhn xt :
- T cc hnh 3.6 v 3.8 ta c th thy rng, vi cng mt s lng bit
vo nh nhau th gii m quyt nh cng s gii m vi s bit sai nhiu
hn so vi gii m quyt nh mm. Bi v nh chng ta cp trc
, gii m quyt nh mm s dng lng t ha nhiu bit, do n to
tin cy khi gii m cao hn so vi gii m quyt nh mm ch s dng
lng t 1 bit.
- T s tn hiu/nhiu SNR cng cao th iu c ngha knh truyn
cng t nhiu, khi , gii m quyt nh cng v mm s cho kt qu gii
m l gn nh nhau.
- Hnh 3.10 cho ta thy c gin BER ca c hai loi quyt nh.
ng BER ca gii m quyt nh mm lun nm thp hn ng BER
ca gii m quyt nh cng. iu c ngha l vi cng mt t s E
b
/N
0
th gii m quyt nh mm lun c BER nh hn so vi gii m quyt nh
cng. Do , xc sut sai bit s nh hn.
- V gii m quyt nh mm s dng lng t nhiu bit nn b nh cn
lu tr cho vic gii m quyt nh mm s ln hn nhiu so vi khi gii
m quyt nh cng.

Chng 3: M phng thut ton Viterbi dng Matlab
Thc hin b gii m Viterbi trn FPGA Trang 66
CHNG 4
XY DNG THUT GII M VITERBI TRN
KIT DE2
4.1 Gii thiu s lc KIT DE2 v phn mm Quartus
4.1.1 KIT DE2 ca Altera
4.1.1.1 Tng quan kit DE2
KIT DE2 c rt nhiu ti nguyn cho php ngi s dng thc thi rt nhiu mch
ng dng t cc mch n gin cho ti cc d n ln c phc tp cao.
Hnh 4.1 KIT DE2 ca Altera
Mt s ti nguyn trn Kit DE2:
Chip FPGA Cyclone II 2C35.
Thit b cu hnh ni tip EPCS16.
Cng USB cho lp trnh v iu khin, h tr c 2 ch JTAG v
ni tip (AS).
512 Kbyte SRAM.
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 67
8 Mbyte SDRAM.
4 Mbyte b nh Flash.
4 nt nhn v 18 Switch.
18 Led v 9 led xanh.
2 b to dao ng 50Mhz v 27 Mhz.
Chip codec Audio 24 bit v chip DAC video 10 bit, cng ethernet
10/100
Cng RS232 9 chn v cng PS/2 cho kt ni chut v bn phm.
B nhn tn hiu hng ngoi.
V mt s chc nng khc...
S khi
Hnh 4.2 S khi KIT DE2
Chip Cyclone EPCS16:
33,216 Logic Elements
105 M4K RAM blocks
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 68
Tng cng 483,840 RAM bits
4 PLLs
475 chn I/O
4.1.1.2 S dng nt nhn v Switch
KIT DE2 c 4 nt nhn, mi nt nhn c chng di bng mch Smith
trigger nh hnh 4.3. Cc ng ra ca mch Smith Trigger c gi l
KEY0,...,KEY3 c kt ni trc tip n Cyclone II FPGA. Cc nt nhn cung
cp mc logic cao (3.3V) khi khng nhn v cung cp logic thp (0V) khi c
nhn.
Hnh 4.3: Chng di phm nhn
C tng cng 18 Switch gt trn kit DE2, mi switch c kt ni trc tip
n chn ca Cyclone II FPGA. Khi switch v tr DOWN (gn cnh ca board),
n cung cp mc logic thp (0V) n FPGA, v khi n c gt n v tr UP th
cho ra mc logic cao (3.3 V).
C 27 led n trn board, 18 led v 9 led xanh, mi led cng c kt ni
trc tip n 1 chn ca FPGA. Led sng khi nhn c mc logic cao t FPGA,
ngc li led tt.
C 8 Led 7 on trn Kit chia lm 2 cp v mt nhm 4 led, led sng mc
thp. Mi on ca led c kt ni trc tip n 1 chn ca FPGA.
Bng 4.1: Th t kt ni phm nhn vi cc chn ca FPGA
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 69
4.1.1.3 S dng LCD
LCD c phng ch ci sn c th dng hin th cc vn bn bng cch gi cc
lnh n b iu khin hin th (HD44780).
Bng 4.2: Gn chn FPGA cho mn hnh LCD
4.1.2 Phn mm lp trnh Quatus II
Quartus II l cng c phn mm pht trin ca hng Altera, cung cp mi trng
thit k ton din cho cc thit k SOPC (h thng trn 1 chip kh trnh - system on
a programmable chip).
y l phn mm ng gi tch hp y phc v cho thit k logic vi cc linh
kin logic kh trnh PLD ca Altera, gm cc dng APEX, Cyclone, FLEX, MAX,
Stratix... Quartus cung cp cc kh nng thit k logic sau:
Mi trng thit k gm cc bn v, s khi, cng c son tho cc ngn
ng: AHDL, VHDL, v Verilog HDL.
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 70
Thit k LogicLock.
L cng c mnh tng hp logic.
Kh nng m phng chc nng v thi gian.
Phn tch thi gian.
Phn tch logic nhng vi cng c phn tch SignalTap@ II.
Cho php xut, to v kt ni cc file ngun to ra cc file chng trnh.
T ng nh v li.
Kh nng lp trnh v nhn din linh kin.
Phn mm Quartus II s dng b tch hp NativeLink@ vi cc cng c
thit k cung cp vic truyn thng tin lin mch gia Quartus vi cc cng
c thit k phn cng EDA khc.
Quartus II cng c th c cc file mch (netlist) EDIF chun, VHDL v
Verilog HDL cng nh to ra cc file netlist ny.
Quartus II c mi trng thit k ha gip nh thit k d dng vit m,
bin dch, sot li, m phng...
Vi Quartus c th kt hp nhiu kiu file trong 1 d n thit k phn cp. C
th dng b cng c to s khi (Quartus Block Editor) to ra s khi m
t thit k mc cao, sau dng cc s khi khc, cc bn v nh: AHDL Text
Design Files (.tdf), EDIF Input Files (.edf), VHDL Design Files (.vhd), v Verilog
HDL Design Files (.v) to ra thnh phn thit k mc thp.
Quartus II cho php lm vic vi nhiu file cng thi im, son tho file thit
k trong khi vn c th bin dch hay chy m phng cc d n khc. Cng c bin
dch Quartus II nm trung tm h thng, cung cp quy trnh thit k mnh cho
php ty bin t c thit k ti u trong d n. Cng c nh v li t ng
v cc bn tin cnh bo khin vic pht hin v sa li tr nn n gin hn.
4.2 Gii quyt vn
4.2.1 Gii m viterbi quyt nh cng
Gi ta s i gii quyt thut ton vic gii m Viterbi (quyt nh cng) cho b m
tc vi K= 3 v b pht m (hay a thc sinh) l (5,7)
8
nhc n trong
chng 4 v thut ton Viterbi.
Ta bit rng, vi trng hp b m ny th nu c N bit m ha ng vo th s
phi tm t 2
N
s kt hp c th (tng ng mt bit vo s c 2 bit ra). iu ny tr
nn v cng phc tp nu N cng ln. Tuy nhin, ng Andrew J Viterbi trong mt
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 71
ghi chp v Error bounds for convolutional codes and an asymptotically optimum
decoding algorithm, IEEE Transactions on Information Theory 13(2):260269,
thng 4 nm 1967 m t mt s ko gim tnh phc tp n mc c th
iu khin c. Mt vi gi thuyt quan trng c a ra nh sau:
- Nh chng ta thy trong bng 4.1 v hnh 4.2 th bt k mt trng thi no
cng u n t ch 2 trng thi c th trc .
- Trong 2 trng thi th ch c mt trng thi ng l trng thi trc .
Chng ta c th tm ra trng thi da trn bit m ha nhn c v b qua
trng thi cn li.
- Li xut hin trong chui bit m ha nhn c l mt phn b ngu nhin
v xc xut ca li l nh.
Da theo cc gi thuyt nh trn, Lu gii m c tin hnh nh sau: Gi s
l c N bit c m ha, ly 2 bit m ha cng mt thi im x l v tnh
ton khong cch Hamming, metric nhnh, metric ng, v thng s ng tn
ti cho N/2 +K-1 ln, ly i l bin chy t 1 n N/2 + K -1.
Tnh ton khong cch Hamming
gii m, ta hy xem xt 2 bit m ha nhn c thi im y
i
v tnh ton
khong cch hamming gia tt c nhng s kt hp c th ca 2 bit ny. S bit khc
nhau c th c tnh ton bng thut ton XOR gia y
i
vi 00, 01, 10, 11 v
sau tnh ton s bit 1.
l s bit 1 thu c sau php tnh
l s bit 1 thu c sau php tnh
l s bit 1 thu c sau php tnh
l s bit 1 thu c sau php tnh
Tnh ton metric nhnh v metric ng
Nh cp trc , mi trng thi ch c th n t 2 trng thi c th
trc (th hin bng 2 ng mu v xanh tng ng trong hnh 4.4). Thng
s metric nhnh chnh l tng ca metric ng ca trng thi trc v khong
cch hamming trong s chuyn i gia 2 trng thi. Trong 2 metric nhnh c
c, thng s metric nhnh nh hn s c chn gi li. y chnh l nhim
v chnh ca b ACS (Add Compare and Select).
Ghi ch:
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 72
1. Theo quy c th m ha chp lun bt u t trng thi 00, v b gii m
Viterbi cng tng t.
2. Khi i = 1, metric nhnh cho trng thi 00 (t trng thi 00_dch bit 0 vo) v
trng thi 10 (t trng thi 00_ dch bit 1 vo) c th c tnh ton. Trong
trng hp ny, metric ng cho mi trng thi l chnh bng vi metric
nhnh khi cc nhnh cn li l khng hp l (khng tn ti).
3. Khi i = 2, metric nhnh cho trng thi 00 (t trng thi 00), trng thi 01 (t
trng thi 10), trng thi 10 (t trng thi 00), v trng thi 11 (t trng thi
10) c th c tnh ton. Trong trng hp ny cng vy, metric ng cho
mi trng thi chnh bng metric nhnh khi cc nhnh khc l khng hp l.
4. Bt u t thi im i = 3, mi trng thi c 2 nhnh v chng ta cn tin hnh
thut ton ACS ni trn.
5. Trong trng hp 2 metric nhnh c cng gi tr, chng ta chn ngu nhin 1
trng thi tin hnh x l tip
Hnh 4.4 Tnh ton metric nhnh v metric ng cho b gii m Viterbi
Trng thi 00 c th n t 2 nhnh
(a) Trng thi 00 vi ng ra 00. Metric nhnh cho s chuyn i ny,
(4.1)
(b) Trng thi 01 vi ng ra 11. Metric nhnh cho s chuyn i ny,
(4.2)
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 73
Metric ng cho trng thi 00 c chn da trn gi tr nh hn trong 2 metric
nhnh trn.
(4.3)
ng tn ti cho trng thi 00 c lu tr trong bin metric ng tn ti
Trng thi 01 c th n t 2 nhnh
(c) Trng thi 10 vi ng ra 10. Metric nhnh cho s chuyn i ny,
(4.4)
(d) Trng thi 11 vi ng ra 01. Metric nhnh cho s chuyn i ny,
(4.5)
Metric ng cho trng thi 01 c chn da trn gi tr nh hn trong 2 metric
nhnh trn.
(4.6)
ng tn ti cho trng thi 01 c lu tr trong bin metric ng tn ti
Trng thi 10 c th n t 2 nhnh
(e) Trng thi 00 vi ng ra 11. Metric nhnh cho s chuyn i ny,
(4.7)
(f) Trng thi 01 vi ng ra 00. Metric nhnh cho s chuyn i ny,
(4.8)
Metric ng cho trng thi 10 c chn da trn gi tr nh hn trong 2 metric
nhnh trn.
. (4.9)
ng tn ti cho trng thi 10 c lu tr trong bin metric ng tn ti
Trng thi 11 c th n t 2 nhnh
(g) Trng thi 10 vi ng ra 01. Metric nhnh cho s chuyn i ny,
(4.10)
(h) Trng thi 11 vi ng ra 10. Metric nhnh cho s chuyn i ny,
(4.11)
Metric ng cho trng thi 11 c chn da trn gi tr nh hn trong 2 metric
nhnh trn.
. (4.12)
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 74
ng tn ti cho trng thi 11 c lu tr trong bin metric ng tn ti
Khi truy hi
Khi ng tn ti c tnh ton N/2 + K 1 ln, thut ton gii m c th
bt u c lng chui ng vo. Nh vo s c mt ca cc bit tn cng (K-1 bit 0
thm vo), th trng thi cui cng ca chui bit theo b m ha chp l trng thi
00.
V vy, bt u t metric ng cui cng c tnh ton thi im N/2 +
K -1 cho trng thi 00, t ng tn ti, ta tm ra trng thi trc tng ng vi
trng thi hin ti. T kin thc v trng thi hin ti v trng thi trc, chui ng
vo c th c quyt nh (xem bng 4.3 v trng thi ng vo v trng thi ng
ra). Tip tc truy hi da theo ng tn ti v c lng chui ng vo cho n
thi im i = 1.
Bng 4.3: Trng thi hin ti v trng thi trc ca n
Input,
if previous state
Current state 00 01 10 11
00 0 0 x x
01 x x 0 0
10 1 1 x x
11 x x 1 1
4.2.2 Gii m viterbi quyt nh mm
trn chng ta bn v thut ton lp trnh gii m Viterbi quyt nh
cng, gi chng ta tin hnh phn tch thut ton gii m viterbi quyt nh mm.
iu ch c s dng l BPSK v knh truyn c gi s l knh AWGN.
M hnh h thng
Chui m nhn c l
, trong c l chui m ha c iu ch s c gi tr nu
bit c m ha l bit 1 v nu bit c m ha l bit 0, n l nhiu Gauss
trng cng tnh vi hm phn phi xc xut l,
vi gi tr trung bnh v phng sai .
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 75
Hm phn b xc xut (PDF) c iu kin ca y nu bit c m ha l bit 0 l,
(4.13)
Hm phn b xc xut (PDF) c iu kin ca y nu bit c m ha l bit 1 l,
(4.14)
Khong cch Euclidean
Trong gii m Viterbi quyt nh mm, da trn v tr ca k hiu c m ha
nhn c, bit m ha c c lng; nu k hiu nhn c l ln hn 0, bit
m ha nhn c s l 1; nu k hiu nhn c l b hn hoc bng 0, bit
m ha nhn c s l bit 0.
Trong gii m quyt nh mm, thay v c lng bit c m ha v tm
khong cch Hamming, ta s tm khong cch gia k hiu nhn c v k hiu c
th c pht i.
Khong cch Euclidean nu bit m ha c truyn i l bit 0 l,
(4.15)
Khong cch Euclidean nu bit m ha c truyn i l bit 1 l,
(4.16)
Cc thnh phn , y
2
, v l chung cho c 2 biu thc nn chng c th c
b i. Khong cch Euclidean sau khi n gin biu thc l,
v (4.17)

Khi thut ton Viterbi nhn c 2 bit m ha cng mt thi im x l, chng
ta cn phi tm ra khong cch Euclidean t c 2 bit.
(4.18)
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 76
4.3 Lu d thut ton lp trnh
Lu gii thut chnh ca chng trnh
Bt u
Ci t ban u
D liu vo
Tnh 4 khong cch nhnh
Lin kt vi cc khong
cch nhnh trc
Cng-So snh-La chn
Lu tr thng tin ng
Trellis cui ?
Truy hi
D liu ra
Kt thc

S
Hnh 4.5: Lu gii thut chnh ca chng trnh
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 77
Khi ci t ban u thit lp nhng thng s cho b m ging nh bn phn
m chp, ng thi nhn cc bit ng vo t knh truyn. Bng trng thi tip theo
cng c tnh ton trc v lu vo b nh khi ny.
Sau , vi mi xung b gii m s tnh ton 4 khong cch nhnh Hamming
hoc Euclidean (gi chung l khong cch), ph thuc vo ch quyt nh cng
hay mm la chn ban u. Vi mi trng thi, khi Cng-So snh-La chn
(ACS) tnh ton hai khong cch ng, so snh v la chn ra ng c khong
cch b nht. Ti thi im ny, b gii m cng lu li cc thng s tch ly cho
trng thi.
Ging nh m chp, s trellis c xy dng, trn s ny, cc im
truyn c nh du vi cc thng s tng tng nh thng s ng v trng thi
trc . Khi tt c cc bit vo c nhn, s trellis xy dng xong, tnh
ton tt c cc thng s tch ly, da vo bng tch ly b gia m tm ng tn
ti, kt hp gia ng tn ti v bng trng thi tip theo b gii m s tm ra
chui bit ban u.
Tnh
Thng s
nhnh
D liu vo
Cng
So snh
La chn
Lu tr
thng s
ng
Truy hi - Tm ng ti
u nht
D liu ra
Hnh 4.6: Lu gii thut b gii m
Sau y l lu chi tit hn cho b gii m Viterbi
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 78
Vo 3 bit
Quyt nh cng / mm
Tnh khong cch
Euclidean
3 bit 3 bit
Chn ch
Mm Cng
Vo 1 bit
Tnh khong cch
Hamming
1 bit 1 bit
input0 input1
input0 input1
Quyt nh cng / mm
Chn ch
Cc khong cch
Dist_00 Dist_01 Dist_10 Dist_11
So Snh
+ +
Lu tr thng s tch ly
Trellits Cui ?
B nh lu tr trng thi
tip theo v ng ra
D liu ra
D liu ra
Truy hi tm ng tn ti
S

S
Hnh 4.7: Lu chi tit gii thut gii m Viterbi trn Kit DE2
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 79
Trc khi thc hin gii m, b gii m phi c ci t ch quyt nh
cho gii m t bn ngoi. Vi mi ch , s c cch tnh khong cch nhnh khc
nhau, Hamming (tng ng vi quyt nh cng) hay Euclidean (tng ng vi
quyt nh mm).
Khi tnh khong cch Hamming
Lng t 1bit
1 bit vo
Lng t 1bit
1 bit vo
1

b
i
t
Bit chun Ging nhau ? Ging nhau ?
Khong cch = 0

Khong cch = 1
S
Khong cch = 0
Khong cch = 1

S
+
Khong cch Hamming
1

b
i
t
Hnh 4.8: Lu tnh khong cch Hamming
Nh trnh by trong phn trc, cc bit nhn c b thu s c lng t
vi 1 bit, khong cch Hamming c tnh da trn s khc nhau gia bit thu c
v bit chun tng ng 00, 01, 10, 11. Sau khi qua khi tnh khong cch
Hamming, kt qu c a n khi ACS tm ra ng tn ti.
Theo s trn, mc d khi cng c 4 ng vo, tuy nhin ti 1 thi im, ch
c 2 ng vo tng ng vi gi tr khi so snh s ging nhau ca bit thu c v bit
chun.
Khi tnh khong cch Euclidean
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 80
Lng t 3 bit (Y)
1 bit vo
Lng t 3 bit (Y)
1 bit vo
3

b
i
t
3

b
i
t
Bit chun (X)
+
Khong cch Euclidean
(X Y )(X Y ) (X Y )(X Y )
Hnh 4.9: Lu gii thut tnh khong cch Euclidean
Khi ch la chn l quyt nh mm th b gii m s tnh ton khong cch
Euclidean thay cho khong cch Hamming. L thuyt v vic tnh ton khong cch
Euclidean c trnh by phn trc.
Kt qu tnh ton khong cch Hamming hay Euclidean u c lu vo 1
bin duy nht tng ng vi bit chun (00, 01, 10, 11). Cc gi tr ny c so snh
vi nhau tm ra khong cch c gi tr nh nht. Cc thng s lin quan n gi
tr nh nht ny c lu tr bo b nh phc v cho qu trnh truy hi sau ny.
Khi trng thi tip theo
Khi va cp ngun, b gii m s thc hin tnh ton v lu tr mt bng bao
gm cc gi tr ca ng ra v gi tr tip theo tng ng vi tt c cc gi tr ng
vo. Bng ny gi l bng trng thi tip theo. Bng trng thi tip theo c s
dng kt hp vi gi tr ca ng ti u tm ra chui bit ban u.
Vic to ra cc gi tr tip theo ging nh to m chp cho cc gi tr ng vo
c cho trc. Cc gi tr ny nm cc v tr c xc nh, b gii m c
th truy cp n mt cch chnh xc tm ra bit ng vo chnh xc.
Bng trng thi tip theo ca b m c s dng trong bi bo co ny c
xc nh nh sau:
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 81
Bng 4.4: Bng trng thi tip theo
Previous
State
INPUT 0 INPUT 1
Next State Output Bit Next State Output Bit
00 00 00 10 11
01 00 11 10 00
10 01 01 11 10
11 01 10 11 01
Khi tnh khong cch nhnh
Vo 3 bit
Tnh khong cch
Euclidean
3 bit 3 bit
Vo 1 bit
Tnh khong cch
Hamming
1 bit 1 bit
input0 input1
input0 input1
Quyt nh cng / mm
Chn ch
Cc khong cch
Dist_00 Dist_01 Dist_10 Dist_11
Hnh 4.10: Lu khi tnh khong cch nhnh
Tng ng vi mi cp bit vo, b gii m tnh ra 4 khong cch nhnh tng ng
vi cc cp bit chun 00, 01, 10, 11.
Khi cng so snh la chn
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 82
+
Dist _00
Bngthng stchly
+
Dist _11
<
0 1
Hnh 4.11: Lu khi ACS
Khong cch nhnh ti trrng thi hin ti c cng dn vi gi tr tch ly
trc trn cng ng i ca s trellis. Sau khi cng, b gii m s so snh 2
kt qu cng trn, gi s ti thi im ny, hai kt qu ny bng nhau, b so snh s
tip tc dch ln mt trng thi v tin hnh so snh ln th hai, lc ny b gii m
s tm ra gi tr nh nht, t b so snh truy ngc li v xc nh gi tr la
chn trng thi trc. Gi tr sau khi c la chn s c lu vo bng tch ly,
bng ny s phc v cho vic tm ng tn ti sau ny.
Khi truy hi
Tngtrng thi ln 1
So snhcc khongcch
nhnh tch lytrong trng
thi
Trng thi 0
Trng thi cui ?
Lu li khongcch nh
nht
S

ngti unht
Hnh 4.12: Lu khi truy hi
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 83
T trng thi u tin, khi truy hi s so snh cc gi tr trong bng tch ly
tm ra ng tn ti ti u nht.
Khi gii m
Bng trng thi tip theo
ng ti u nht
Ging nhau ?
D liu ra
B m
Bit 0 vo Bit 1 vo Trng thi tip theo
Hnh 4.13: Lu khi gii m
Sau khi qua khi truy hi, b gii m tm c ng tn ti. B gii m s
tin hnh so snh gi tr tip theo ca ng tn ti ti thi im hin ti vi gi tr
ca ng tn ti ti thi im sau mt trng thi. Vi mi ln so snh, b gii m
s th vi mt trong hai bit vo l 0 hay 1, so snh s ging nhau tng ng vi gi
tr vo l 0 hay 1, b gii m s xc nh c bit c m ha ban u khi pht
l 0 hay 1.
Sau khi hon thnh so snh tt c cc trng thi, b gii m xc nh c
chui bit ban u.
4.4 Kt qu
Qu trnh thc hin c chia lm hai qu trnh, th nht l lp trnh gii thut
m ha m chp v thut gii Viterbi chy m phng s dng phn mm m phng
c sn trong Quartus II; th hai l tin hnh bin dch tng hp v chng trnh
ln Kit DE2 c km theo chng trnh hin th trn LCD c cc Led n, trong
chng trnh ln Kit DE2 th ngi lp trnh loi b khi m ha m chp.
Gi s cho chui bit ban u trc khi m ha m chp l: 11100101.
Sau khi m ha m chp cho ra chui bit sau: 1110011011110100
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 84
Cho ngc chui 16 bit trn vo ng vo ca b gii m Viterbi. Kt qu ng ra
l: 11100101
V khng c nhiu tc ng nn kt qu ca hai quyt nh cng v mm l nh
nhau.
Kt qu m phng trn phn mm Quartus II nh sau:
Hnh 4.14: Kt qu m phng 1
Gi s ng vo b gii m Viterbi b sai 2 bit: 1010011010110100
Kt qu ra vn chnh xc: 11100101
Hnh 4.15: Kt qu m phng 2
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 85
Gi s ng vo b gii m Viterbi b sai 3 bit : 1010011010110101
Kt qu 1 bit cui b gii m sai: 11100100
Hnh 4.16: Kt qu m phng 3
Gi s ng vo b gii m Viterbi b sai 4 bit : 1010001010110101
Kt qu 1 bit cui b gii m sai: 11100100
Hnh 4.17: Kt qu m phng 4
Kt qu trn chng minh b gii m Viterbi c kh nng sa sai bit n rt tt.
Gi s ng vo b gii m Viterbi b sai 1 cp bit : 1101011011110100
Kt qu 2 bit b gii m sai: 10110101
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 86
Hnh 4.18: Kt qu m phng 5
Gi s ng vo b gii m Viterbi b sai 1 bit n v 1cp bit :
1101011011111100
Kt qu 5 bit b gii m sai: 10110010
Hnh 4.19: Kt qu m phng 6
Kt qu trn cho thy, thut gii m Viterbi khng c kh nng sa li sai trong
trng hp li a bit.
So snh vi kt qu m phng trn Matlab
Vn chui bit vo nh trn: 11100101. Vi m phng trn Matlab, h thng c
tc ng ca nhiu trng Gaussian. Kt qu gii m b sai 1 bit vi quyt nh
mm.
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 87
Hnh 4.20: M phng trn Matlab
V m phng trn Kit DE2 l mi trng l tng, d liu bit nhn c nhp
vo bi ngi s dng, khng b tc ng ca knh truyn, do kt qu gii m
cho chnh xc hn so vi gii m trn Matlab.
Hnh nh thc t trn Kit DE2 nh sau:
Hnh 4.21: Hnh thc t b kit 1
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Khi ng chng trnh m
phng, LCD hin th DH
SPKT TPHCM v dng ch
DO AN TOT NGHIEP
Thc hin b gii m Viterbi trn FPGA Trang 88
Hnh 4.22: Hnh thc t b kit 2
Hnh 4.23: hnh thc t b kit 3
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Tip theo, LCD hin th
nhm thc hin ti
4. LCD hin
th chui d
liu cn gii
m v chui d
liu sau gii
m.
5. 8 LED biu din
chui d liu sau gii
m.
2. 16 SW gn d
liu cn gii m.
3. Mc 1
bt
u gii
m.
1. Mc 0
chn
gii m
quyt nh
mm
Key 0
reset mch
Thc hin b gii m Viterbi trn FPGA Trang 89
CHNG 5: KT LUN
5.1 Tng kt nhn xt
Tng kt li, trong cun n ny nhm thc hin c nhng ni dung
sau:
Gii thiu v v tr vai tr ca m ha knh truyn trong h thng thng tin
s, so snh hai hnh thc m ha l m khi v m trellis.
Khi nim v phn tch m chp, cch thc m ha s dng m chp, cng
nh cu trc ca b m ha chp.
Khi nim v phn tch thut ton gii m Viterbi, cch m thut ton Viterbi
gii m mt tn hiu v sa sai cc li xy ra trn knh truyn, phn bit hai
phng php gii m l gii m quyt nh cng v quyt nh mm.
Thc hin m phng Matlab xem hiu qu ca thut ton Viterbi.
Thc hin m t trn Kit DE2 bng ngn ng VHDL kim chng kt qu
m phng.
Qua kt qu m phng bng Matlab v kt qu m t trn kit DE2, nhm rt
ra c nhng nhn xt sau:
M ha knh truyn gip gim thiu tc ng ca nhiu v ci thin
tin tc tt.
Thut ton gii m viterbi t hiu qu cao, xc sut li thp
Trn knh truyn c li Gauss trng, tn hiu c th c phc hi tt.
Thut ton viterbi vi quyt nh mm cho kt qu tt hn quyt nh
cng. V vi quyt nh mm tn hiu sau khi c nhn b thu c
lng t vi nhiu mc, do dn n xc sut sai s thp hn so vi quyt
nh cng.
i vi cc li nhiu bit lin tip, thut ton Viterbi khng mang li
hiu qu.
Trong knh truyn c t s SNR cao, thut ton viterbi vi c 2 quyt
nh cng v mm u cho kt qu tt gn nh nhau.
5.2 Tn ti v hng pht trin ca ti
Nhng mt cn tn ti:
- Vic m phng trn matlab cng nh m t trn kit DE2 u ch mi tin
hnh vi b m n gin tc vi chiu di rng buc thp. V th,
kt qu m phng c th s khng bao qut v ni ht c u nhc
im ca thut ton.
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
Thc hin b gii m Viterbi trn FPGA Trang 90
- Vic m t trn kit DE2 ch l khu gii m vi chui bit nhn c nhp
bi ngi s dng. Do , ta khng th nh gi c ht tc ng ca
nhiu ch vi vi ln th nghim vi cc bit nhn c l sai.
- Vic gii m Viterbi quyt dnh mm ch mi thc hin vi phng php
dng khong cch Euclidean.
Hng pht trin ti:
- Vi gii hn thi gian cng nh kh nng c hn nn nhm tc gi vn
cn cha tm hiu hon chnh v m chp cng nh thut gii Viterbi. V
vy, c th phng php thc hin cng nh lp trnh s khng l gii
php ti u. Nu c c hi nghin cu tip th ti c th nng ln
thc hin ti u ha cho b thu Viterbi, th nghim vi cc b m khc
nhau t tm ra b m ti u nht cho knh truyn AWGN.
- Ci thin vic m t trn kit DE2 bng cch thm phn to bit nhn ngu
nhin ch khng nhp trc tip bng tay, t tng hp nh gi tc ng
ca nhiu ln tn hiu mt cch tng qut hn.
- T kt qu ca ti, chng ta c th thit k cc IC thc hin cc chc
nng khc nhau trong h thng thng tin s.
- Nghin cu tin hnh xy dng b m ha ngun.
Chng 4: Xy dng thut ton gii m Viterbi trn Kit DE2
PHN C
PH LC V TI
LIU THAM KHO
I. Ph lc
1. Hng dn s dng kit DE2 m phng
Chc nng cc mt s thit b trn Kit DE2 nh sau:
- Switch 0: Chc nng start, bt u qu trnh gii m. Mc 1 tng
ng vi lnh thc hin bt u.
- Switch 1: Chc nng la chn ch quyt nh cng hay mm.
1. Mc 0: Quyt nh cng
2. Mc 1: Quyt nh mm
- Switch 2 n 17: Tng ng vi 16 bit ng vo.
- Nt nhn Key 0: Chc nng reset mch.
- LCD: Chc nng hin th thng tin v n v d liu vo ra ca b
gii m.
- Led 0 n 7: Chc nng hin th gi tr ca 8 bit ng ra.
1. Led sng: Mc 1
2. Led tt: Mc 0
Qu trnh m phng trn Kit DE2 nh sau:
Sau khi np chng trnh t my tnh xung Kit DE2, mn hnh LCD s
hin th mt s thng tin v n. Khi gt cc Switch t 2 n 17 cp d liu
ng vo cho b gii m, LCD s hin th gi tr 16 bit ny. Khi gt Switch 0, qu
trnh gii m bt u, LCD hin th thm 8 bit ra dng th 2, ng thi cc Led s
sng.
Nu nhn nt Key 0 (Reset), LCD s hin th li cc thng tin ban u, nu lc ny,
Switch Start ang bt th cc Led vn sng, nu Switch Start gt xung mc 0 th
cc Led tt ht.
2. Ti nguyn s dng trn Kit DE2
Bng: Thng bo v ti nguyn s dng trn kit DE2
Phn C: Ph lc v ti liu tham kho
Bng: Danh sch cc chn s dng trn Kit DE2
Signal Name PIN Discription
Clock_50 PIN_N2 50 mHz clock input
SW[0] PIN_N25 Toggle Switch[0]
SW[1] PIN_N26 Toggle Switch[1]
SW[2] PIN_P25 Toggle Switch[2]
SW[3] PIN_AE14 Toggle Switch[3]
SW[4] PIN_AF14 Toggle Switch[4]
SW[5] PIN_AD13 Toggle Switch[5]
SW[6] PIN_AC13 Toggle Switch[6]
SW[7] PIN_C13 Toggle Switch[7]
SW[8] PIN_B13 Toggle Switch[8]
SW[9] PIN_A13 Toggle Switch[9]
SW[10] PIN_N1 Toggle Switch[10]
SW[11] PIN_P1 Toggle Switch[11]
SW[12] PIN_P2 Toggle Switch[12]
SW[13] PIN_T7 Toggle Switch[13]
SW[14] PIN_U3 Toggle Switch[14]
Phn C: Ph lc v ti liu tham kho
SW[15] PIN_U4 Toggle Switch[15]
SW[16] PIN_V1 Toggle Switch[16]
SW[17] PIN_V2 Toggle Switch[17]
LEDR[0] PIN_AE23 LED Red[]
LEDR[1] PIN_AF23 LED Red[]
LEDR[2] PIN_AB21 LED Red[]
LEDR[3] PIN_AC22 LED Red[]
LEDR[4] PIN_AD22 LED Red[]
LEDR[5] PIN_AD23 LED Red[]
LEDR[6] PIN_AD21 LED Red[]
LEDR[7] PIN_AC21 LED Red[]
KEY[0] PIN_G26 Pushbutton[0]
LCD_DATA[0] PIN_J1 LCD DATA []
LCD_DATA[1] PIN_J2 LCD DATA []
LCD_DATA[2] PIN_H1 LCD DATA []
LCD_DATA[3] PIN_H2 LCD DATA []
LCD_DATA[4] PIN_J4 LCD DATA []
LCD_DATA[5] PIN_J3 LCD DATA []
LCD_DATA[6] PIN_H4 LCD DATA []
LCD_DATA[7] PIN_H3 LCD DATA []
LCD_RW PIN_K4 LCD Read/Write Select, 0 = Write, 1 =
Read
LCD_EN PIN_K3 LCD Enable
LCD_RS PIN_K1
LCD Command/Data Select, 0 =
Command, 1 = Data
LCD_ON PIN_L4 LCD Power ON/OFF
Phn C: Ph lc v ti liu tham kho
LCD_BLON PIN_L2 LCD Back Light ON/OFF
3. M ngun Matlab
function varargout = viterbi2(varargin)
gui_Singleton = 1;
gui_State = struct('gui_Name', mfilename, ...
'gui_Singleton', gui_Singleton, ...
'gui_OpeningFcn', @viterbi2_OpeningFcn, ...
'gui_OutputFcn', @viterbi2_OutputFcn, ...
'gui_LayoutFcn', [] , ...
'gui_Callback', []);
if nargin && ischar(varargin{1})
gui_State.gui_Callback = str2func(varargin{1});
end

if nargout
[varargout{1:nargout}] = gui_mainfcn(gui_State, varargin{:});
else
gui_mainfcn(gui_State, varargin{:});
end
function viterbi2_OpeningFcn(hObject, eventdata, handles, varargin)
handles.output = hObject;
guidata(hObject, handles);
h1 = getappdata(0,'GUI1_handle');
close(h1)
h2 = gcf;
setappdata(0,'GUI2_handle',h2);
axes(handles.logo);
imshow('KHOADIENTU.png');
viterbi3;
set(handles.bitin,'Enable','inactive');
global inbit numin ;
inbit =0;
function varargout = viterbi2_OutputFcn(hObject, eventdata, handles)
varargout{1} = handles.output;
Phn C: Ph lc v ti liu tham kho

function button_back_Callback(hObject, eventdata, handles)
viterbi1;

function button_exit_Callback(hObject, eventdata, handles)
exit = questdlg('Ready to quit?',...
'Exit Dialog','Yes','No','No');
switch exit
case 'Yes',
disp('Exiting MATLAB');
save
quit
case 'No'
quit cancel;
end

function numin_Callback(hObject, eventdata, handles)
user_entry = str2double(get(hObject,'String'));
if isnan(user_entry)
errordlg('Type the integer, maximum value is 10^6! ','Input Error !','modal')
set(hObject,'String','');
return
end

function numin_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function numin_ButtonDownFcn(hObject, eventdata, handles)

function g2_Callback(hObject, eventdata, handles)
user_entry = str2double(get(hObject,'string'));
if isnan(user_entry)
errordlg('Type the integer ! ','Input Error !','modal')
set(hObject,'String','');
return
end

function g2_CreateFcn(hObject, eventdata, handles)
Phn C: Ph lc v ti liu tham kho
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function g1_Callback(hObject, eventdata, handles)
user_entry = str2double(get(hObject,'string'));
if isnan(user_entry)
errordlg('Type the integer ! ','Input Error !','modal')
set(hObject,'String','');
return
end

function g1_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function length_Callback(hObject, eventdata, handles)
user_entry = str2double(get(hObject,'string'));
if isnan(user_entry)
errordlg('Type the integer ! ','Input Error !','modal')
set(hObject,'String','');
return
end

function length_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function numout_Callback(hObject, eventdata, handles)
user_entry = str2double(get(hObject,'string'));
if isnan(user_entry)
errordlg('Type the integer ! ','Input Error !','modal')
set(hObject,'String','');
return
end
Phn C: Ph lc v ti liu tham kho
if (user_entry > 2)||(user_entry < 1)
errordlg('The Viterbi decoder is just for maximum 2 outputs !','Input
Error !','modal')
set(hObject,'String','');
return
end
if user_entry == 1
set(handles.g2,'Enable','inactive');
set(handles.textber,'ForegroundColor','black')
elseif user_entry == 2
set(handles.g2,'Enable','on');
set(handles.textber,'ForegroundColor','blue')
end
function numout_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function auto_Callback(hObject, eventdata, handles)
if (get(hObject,'Value') == get(hObject,'Max'))
a = 1;
set(handles.numin,'Enable','inactive');
set(handles.numin,'String','');
set(handles.bitin,'Enable','on');
set(handles.bitin,'String','');
set(handles.text7,'ForegroundColor','black');
else
a = 0;
set(handles.numin,'Enable','on');
set(handles.bitin,'Enable','inactive');
set(handles.text7,'ForegroundColor','blue');
end

function bitin_Callback(hObject, eventdata, handles)


function bitin_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
Phn C: Ph lc v ti liu tham kho
end

function bitencoded_Callback(hObject, eventdata, handles)
function bitencoded_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function bitout_Callback(hObject, eventdata, handles)
function bitout_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function ber_Callback(hObject, eventdata, handles)
clc;
if (get(handles.auto,'Value') == get(handles.auto,'Max'))
a = 1;
else
a = 0;
end
if a == 1
inbit = get(handles.bitin,'String');
inbit = str2num(inbit);
numin = length(inbit);
else
numin = get(handles.numin,'String');
numin = str2num(numin);
inbit = randint(1,numin);
end
numout = get(handles.numout,'String');
numout = str2num(numout);
len = get(handles.length,'String');
len = str2num(len);
g1 = get(handles.g1,'String');
g1 = str2num(g1);
Phn C: Ph lc v ti liu tham kho
g2 = get(handles.g2,'String'
g2 = str2num(g2);

Eb_N0_dB = [1:1:10];
for i = 1:length(Eb_N0_dB)
snr_db = Eb_N0_dB(i)
if numout == 1
trellis = poly2trellis(len,g1);
elseif numout == 2
trellis = poly2trellis(len,[g1 g2]);
end

encbits = convenc(inbit,trellis);
encbits = 2*encbits - 1;
awgnbits = awgn(encbits,snr_db,'measured');


str = get(handles.typeofdec,'String');
val = get(handles.typeofdec,'Value');
switch str{val}
case 'Soft Decision'
select = 0;
case 'Hard Decision'
select = 1;
case 'Both'
select = 2;
end

if select == 0
partition = [-.8571 -.5714 -.2857 0 .2857 .5714 .8571];
codebook = [-.99 -.8571 -.5714 -.2857 0 .2857 .5714 .8571];
quanbits = quantiz(awgnbits,partition,codebook);
tblen = numin -1 ;
opmode = 'term';
dectype = 'soft';
nsdec = 3;
decbits = vitdec(quanbits,trellis,tblen,'term','soft',nsdec);
end
if select == 1
partition = [0];
Phn C: Ph lc v ti liu tham kho
codebook = [0 1];
quanbits = quantiz(awgnbits,partition,codebook);
tblen = numin-1;
opmode = 'term' ;
dectype = 'hard';
decbits = vitdec(quanbits,trellis,tblen,'term','hard');
end
if select == 0 || select == 1
[numerr ratioerr] = biterr(inbit, decbits);
ratioerr_comp(i) = ratioerr
end

if select == 2
partition_h = [0];
codebook_h = [0 1];
quanbits_h = quantiz(awgnbits,partition_h,codebook_h);
tblen_h = numin-1;
opmode_h = 'term' ;
dectype_h = 'hard';
decbits_h = vitdec(quanbits_h,trellis,tblen_h,'term','hard');

partition_s = [-.8571 -.5714 -.2857 0 .2857 .5714 .8571];
codebook_s = [-.99 -.8571 -.5714 -.2857 0 .2857 .5714 .8571];
quanbits_s = quantiz(awgnbits,partition_s,codebook_s);
tblen_s = numin -1 ;
opmode_s = 'term';
dectype_s = 'soft';
nsdec = 3;
decbits_s = vitdec(quanbits_s,trellis,tblen_s,'term','soft',nsdec);
[numerr_s ratioerr_s] = biterr(inbit, decbits_s);
ratioerr_comp_s(i) = ratioerr_s
[numerr_h ratioerr_h] = biterr(inbit, decbits_h);
ratioerr_comp_h(i) = ratioerr_h
end
end
if select == 0
figure
semilogy(Eb_N0_dB,ratioerr_comp,'mp-','LineWidth',2);
axis([0 10 10^-8 0.5])
grid on
Phn C: Ph lc v ti liu tham kho
legend('Viterbi-Soft decision(rate-1/2, [5,7]_8)');
xlabel('Eb/No, dB');
ylabel('Bit Error Rate');
title('BER for Viterbi-Soft decision decoding in AWGN');
end
if select == 1
figure
semilogy(Eb_N0_dB,ratioerr_comp,'bd-','LineWidth',2);
axis([0 10 10^-8 0.5])
grid on
legend('Viterbi-Hard decision(rate-1/2, [5,7]_8)');
xlabel('Eb/No, dB');
ylabel('Bit Error Rate');
title('BER for Viterbi-Hard decision decoding in AWGN');
end
if select == 2
figure
semilogy(Eb_N0_dB,ratioerr_comp_s,'mp-','LineWidth',2);
hold on;
semilogy(Eb_N0_dB,ratioerr_comp_h,'bd-','LineWidth',2);
axis([0 10 10^-8 0.5])
grid on
legend('Viterbi-Soft decision(rate-1/2, [5,7]_8)','Viterbi-Hard decision(rate-1/2,
[5,7]_8)');
xlabel('Eb/No, dB');
ylabel('Bit Error Rate');
title('BER for both types of decision of Viterbi decoding in AWGN');
end
function reset_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function start_Callback(hObject, eventdata, handles)
clc;
global inbit numin ratioerr
inbit = get(handles.bitin,'String');
Phn C: Ph lc v ti liu tham kho
inbit = str2num(inbit);
numin = length(inbit);
numout = get(handles.numout,'String');
numout = str2num(numout);
len = get(handles.length,'String');
len = str2num(len);
g1 = get(handles.g1,'String');
g1 = str2num(g1);
g2 = get(handles.g2,'String');
g2 = str2num(g2);

if numout == 1
trellis = poly2trellis(len,g1);
elseif numout == 2
trellis = poly2trellis(len,[g1 g2]);
end

encbits = convenc(inbit,trellis);
encbits = num2str(encbits);
set(handles.bitencoded,'String',encbits)
encbits = str2num(encbits);
encbits = 2*encbits - 1;
snr = get(handles.snr,'String');
snr = str2num(snr);
awgnbits = awgn(encbits, snr, 'measured');

str = get(handles.typeofdec,'String');
val = get(handles.typeofdec,'Value');
switch str{val}
case 'Soft Decision'.
select = 0;
case 'Hard Decision'
select = 1;
case 'Both'
select = 2;
end

if select == 0
partition = [-.8571 -.5714 -.2857 0 .2857 .5714 .8571];
codebook = [-.99 -.8571 -.5714 -.2857 0 .2857 .5714 .8571];
quanbits = quantiz(awgnbits,partition,codebook);
Phn C: Ph lc v ti liu tham kho
tblen = numin -1 ;
opmode = 'term';
dectype = 'soft';
nsdec = 3;
decbits = vitdec(quanbits,trellis,tblen,'term','soft',nsdec);
end
if select == 1
partition = [0];
codebook = [0 1];
quanbits = quantiz(awgnbits,partition,codebook);
tblen = numin-1;
opmode = 'term' ;
dectype = 'hard';
decbits = vitdec(quanbits,trellis,tblen,'term','hard');
end

decbits = num2str(decbits);
set(handles.bitout,'String',decbits)
decbits = str2num(decbits);

[numerr ratioerr] = biterr(inbit, decbits);
numerr = num2str(numerr);
set(handles.numerr,'String',numerr);
numerr = str2num(numerr);
ratioerr = num2str(ratioerr);
set(handles.ratioerr,'String',ratioerr);
ratioerr = str2num(ratioerr);

function reset_Callback(hObject, eventdata, handles)
clc;
set(handles.typeofdec,'Value',1);
set(handles.auto,'Value',0);
set(handles.bitin,'Enable','inactive');
set(handles.numin,'String','');
set(handles.numout,'String','2');
set(handles.length,'String','3');
set(handles.g1,'String','5');
set(handles.g2,'String','7');
set(handles.snr,'String','5');
set(handles.bitin,'String','');
set(handles.bitencoded,'String','');
Phn C: Ph lc v ti liu tham kho
set(handles.bitout,'String','');
set(handles.numerr,'String','');
set(handles.ratioerr,'String','');
set(handles.g2,'Enable','on');
set(handles.textber,'ForegroundColor','blue')

function togglebutton1_Callback(hObject, eventdata, handles)

function edit17_Callback(hObject, eventdata, handles)
function edit17_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function snr_Callback(hObject, eventdata, handles)
user_entry = str2double(get(hObject,'string'));
if isnan(user_entry)
errordlg('Type the integer ! ','Input Error !','modal')
set(hObject,'String','');
return
end
function snr_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end

function pushbutton5_Callback(hObject, eventdata, handles)
function start_KeyPressFcn(hObject, eventdata, handles)
function taoinbit_Callback(hObject, eventdata, handles)
clc;
global inbit numin ;
if (get(handles.auto,'Value') == get(handles.auto,'Max'))
a = 1;
else
Phn C: Ph lc v ti liu tham kho
a = 0;
end
if a == 1
inbit = get(handles.bitin,'String');
inbit = str2num(inbit);
else
numin = get(handles.numin,'String');
numin = str2num(numin);
inbit = randint(1,numin);
end
inbit = num2str(inbit);
set(handles.bitin,'Enable','on');
set(handles.bitin,'String',inbit);
inbit = str2num(inbit);
function viwebit_Callback(hObject, eventdata, handles)
close 'Gui_3' ;

function typeofdec_Callback(hObject, eventdata, handles)
function typeofdec_CreateFcn(hObject, eventdata, handles)
if ispc && isequal(get(hObject,'BackgroundColor'),
get(0,'defaultUicontrolBackgroundColor'))
set(hObject,'BackgroundColor','white');
end
4. M ngun VHDL
Viterbi.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.distance.all;
USE work.converter.all;
ENTITY viterbi is
Phn C: Ph lc v ti liu tham kho
GENERIC(
CONSTANT K: natural: = 1;
CONSTANT N: natural: = 2;
CONSTANT L: natural: = 3;
CONSTANT Ga: natural: = 5;
CONSTANT Gb: natural: = 7;
CONSTANT V: natural: = 8
);
PORT(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
dec_in: in std_logic;
sel_dec: in std_logic;
data : in std_logic_vector (V*N-1 downto 0);
data_out: out std_logic_vector (V-1 downto 0);
conv_in: in std_logic_vector(V-1 downto 0);
conv_out: out std_logic_vector(V*N-1 downto 0)
);
END viterbi;
ARCHITECTURE rtl OF viterbi IS
TYPE matrix_1 is array (0 to 3, 0 to 1) of std_logic_vector(3 downto 0);
TYPE matrix_2 is array (0 to 3, 0 to 10) of integer ;
TYPE matrix_3 is array (0 to 3, 0 to 1) of integer;
TYPE matrix_4 is array (0 to 8) of integer;
TYPE matrix_7 is array (0 to 7) of std_logic_vector (1 downto 0);
TYPE matrix_8 is array (0 to 3, 0 to 10) of integer;
TYPE matrix_9 is array (0 to 10) of integer;
SIGNAL data_in : matrix_7;
SIGNAL ne_st_reg: matrix_1;
Phn C: Ph lc v ti liu tham kho
BEGIN
---------------------------------------------------------------------------------
-- the firt part is get data input
---------------------------------------------------------------------------------
get_data_in: PROCESS(dec_in,reset,sel_dec)
VARIABLE v2: integer;
BEGIN
IF reset = '0' THEN v2: = 0;
ELSIF dec_in = '1' THEN
FOR v2 in 0 to 7 LOOP
data_in(7-v2) <= data(v2*2+1 downto v2*2);
END LOOP;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
-- The second part is to initialize the next state
--------------------------------------------------------------------------------
next_state_out_reg: PROCESS(reset)
VARIABLE lp1: std_logic_vector(1 downto 0);
VARIABLE lp2: std_logic;
VARIABLE l1,l2,l3: integer;
BEGIN
IF reset = '0' THEN
lp1: = "00";
lp2: = '0';
ELSE
FOR l1 in 0 to 3 LOOP
FOR l2 in 0 to 1 LOOP
lp1: = conv_std_logic_vector(l1,2);
IF l2=0 THEN
Phn C: Ph lc v ti liu tham kho
lp2: = '0';
ELSE
lp2: = '1';
END IF;
-- next state and output bits
ne_st_reg(l1,l2) <= lp2&lp1(1)&(lp2 xor lp1(0))&(lp2 xor lp1(1) xor lp1(0));
END LOOP;
END LOOP;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
-- The third part is calculate Hamming distance
--------------------------------------------------------------------------------
Hd_calculation: PROCESS(clk,start)
VARIABLE pre_state_reg: matrix_2; -- previous states for trace back
VARIABLE aem_reg : matrix_3; -- aem
VARIABLE ssa_reg : matrix_4; -- trace back
VARIABLE result : std_logic_vector(V-1 downto 0);
VARIABLE ac_reg : matrix_8; -- accumalated metric table
VARIABLE sv_reg : matrix_9; -- survier path register
VARIABLE cnt : integer: =0; -- internal cuonter
VARIABLE flag : std_logic: = '0';
VARIABLE dist_00, dist_01, dist_10, dist_11: integer;
VARIABLE v3: integer: =0;
VARIABLE t1: std_logic_vector (1 downto 0);
VARIABLE t3,t4: integer range 0 to 3;
VARIABLE l1,l2,l3: integer;
VARIABLE dec_en: std_logic: = '0';
BEGIN
IF reset = '0' THEN v3: = 0; cnt: = 0;
ELSIF start = '1' THEN
Phn C: Ph lc v ti liu tham kho
IF Rising_edge(clk) THEN
-- cnt is a counter to count terllics diagrame to tell us which step now
cnt: = cnt + 1;
IF cnt = 10 THEN
cnt: = 0;
END IF;
-- This part is to calculate Hamming distance or Euclidean distance
IF sel_dec = '1' THEN -- Euclidean
dist_00: = euclid(data_in(cnt-1),"00");
dist_01: = euclid(data_in(cnt-1),"01");
dist_10: = euclid(data_in(cnt-1),"10");
dist_11: = euclid(data_in(cnt-1),"11");
ELSE -- Hamming
dist_00: = hamming(data_in(cnt-1),"00");
dist_01: = hamming(data_in(cnt-1),"01");
dist_10: = hamming(data_in(cnt-1),"10");
dist_11: = hamming(data_in(cnt-1),"11");
END IF;
------------------------------------------------
-- This is ACS block
-------------------------------------------------
-- This is Branch Metric Unit
CASE cnt is
WHEN 0 =>
FOR l1 in 0 to 3 LOOP
aem_reg(l1,0): = 0;
aem_reg(l1,1): = 0;
FOR l2 in 0 to 8 LOOP
ac_reg(l1,l2): = 0;
END LOOP;
Phn C: Ph lc v ti liu tham kho
END LOOP;
WHEN 1 =>
ac_reg(0,1): = dist_00 ;
ac_reg(2,1): = dist_11 ;
pre_state_reg(0,1): = 0;
pre_state_reg(2,1): = 0;
WHEN 2 =>
ac_reg(0,2): = dist_00 + ac_reg(0,1);
ac_reg(1,2): = dist_01 + ac_reg(2,1);
ac_reg(2,2): = dist_11 + ac_reg(0,1);
ac_reg(3,2): = dist_10 + ac_reg(2,1);
pre_state_reg(0,2): = 0;
pre_state_reg(2,2): = 0;
pre_state_reg(1,2): = 2;
pre_state_reg(3,2): = 2;
WHEN others =>
aem_reg(0,0): = dist_00 + ac_reg(0,cnt-1);
aem_reg(2,0): = dist_11 + ac_reg(0,cnt-1);
aem_reg(1,0): = dist_01 + ac_reg(2,cnt-1);
aem_reg(3,0): = dist_10 + ac_reg(2,cnt-1);
aem_reg(0,1): = dist_11 + ac_reg(1,cnt-1);
aem_reg(2,1): = dist_00 + ac_reg(1,cnt-1);
aem_reg(1,1): = dist_10 + ac_reg(3,cnt-1);
aem_reg(3,1): = dist_01 + ac_reg(3,cnt-1);
END CASE;
--The following part compare each 2 possible path and select
-- a small one and write the survival path to the survival path register.
IF (cnt >= 3) and (cnt <= 8) THEN
FOR l1 in 0 to 3 LOOP
t1: = conv_std_logic_vector(l1,2);
Phn C: Ph lc v ti liu tham kho
IF aem_reg(l1, 0) <= aem_reg(l1, 1) THEN
ac_reg(l1,cnt): = aem_reg(l1, 0);
pre_state_reg(l1,cnt): = conv_int(t1(0) & '0');
ELSE
ac_reg(l1,cnt): = aem_reg(l1, 1);
pre_state_reg(l1,cnt): = conv_int(t1(0) & '1');
END IF;
END LOOP;
END IF;
-- This is the trace back part which finds the Most Likelihood Path
IF cnt = 9 THEN
sv_reg(0): = 0; -- 0 is allway the first step
IF ac_reg(0,1) < ac_reg(2,1) THEN -- the second step
sv_reg(1): = 0;
ELSIF ac_reg(0,1) > ac_reg(2,1) THEN
sv_reg(1): = 2;
ELSE -- compare the third step
IF ac_reg(0,2) <= ac_reg(2,2) THEN
l2: = ac_reg(0,2);
ELSE
l2: = ac_reg(2,2);
END IF;
IF ac_reg(1,2) <= ac_reg(3,2) THEN
l3: = ac_reg(1,2);
ELSE
l3: = ac_reg(3,2);
END IF;
IF l2 <= l3 THEN
sv_reg(1): = 0;
ELSE
Phn C: Ph lc v ti liu tham kho
sv_reg(1): = 2;
END IF;
END IF;
FOR l1 in 2 to 8 LOOP
IF ac_reg(0,l1) <= ac_reg(1,l1) THEN
l2: = ac_reg(0,l1);
ELSE
l2: = ac_reg(1,l1);
END IF;
IF ac_reg(2,l1) <= ac_reg(3,l1) THEN
l3: = ac_reg(2,l1);
ELSE
l3: = ac_reg(3,l1);
END IF;
IF l2 < l3 THEN
IF ac_reg(0,l1) <= ac_reg(1,l1) THEN
sv_reg(l1): = 0;
ELSE
SV_reg(l1): = 1;
END IF;
ELSIF l2 > l3 THEN
ac_reg(2,l1) <= ac_reg(3,l1) THEN
sv_reg(l1): = 2;
ELSE
sv_reg(l1): = 3;
END IF;
ELSE
IF ac_reg(0,l1+1) <= ac_reg(1,l1+1) THEN
l2: = ac_reg(0,l1+1);
ELSE
Phn C: Ph lc v ti liu tham kho
l2: = ac_reg(1,l1+1);
END IF;
IF ac_reg(2,l1+1) <= ac_reg(3,l1+1) THEN
l3: = ac_reg(2,l1+1);
ELSE
l3: = ac_reg(3,l1+1);
END IF;
IF l2 <= l3 THEN
IF ac_reg(0,l1+1) <= ac_reg(1,l1+1) THEN
sv_reg(l1): = pre_state_reg(0,l1+1);
ELSE
SV_reg(l1): = pre_state_reg(1,l1+1);
END IF;
ELSIF l2 > l3 THEN
IF ac_reg(2,l1+1) <= ac_reg(3,l1+1) THEN
sv_reg(l1): = pre_state_reg(2,l1+1);
ELSE
sv_reg(l1): = pre_state_reg(3,l1+1);
END IF;
END IF;
END IF;
IF l1 = 8 THEN flag: = '1';
ELSE flag: = '0';
END IF;
END LOOP;
END IF;
-----------------------------------------------------------------------
-- when the flag is one, it means the TB part is done.
-- Then the decoder begins to decode the data
IF flag = '1' THEN
FOR l1 in 0 to 7 LOOP
t3: = sv_reg(l1);
Phn C: Ph lc v ti liu tham kho
t4: = sv_reg(l1+1);
IF t4 = conv_int(ne_st_reg(t3, 0)(3 downto 2)) THEN
result(l1): = '0';
ELSIF t4 = conv_int(ne_st_reg(t3, 1)(3 downto 2)) THEN
result(l1): = '1';
END IF;
END LOOP;
END IF;
END IF;
FOR l1 in 0 to 7 LOOP
data_out(l1) <= result(7-l1);
END LOOP;
IF l1 = 7 THEN dec_en: = '1';
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------
-- This part is show convolution processor.
Convolution: PROCESS(clk,reset)
VARIABLE conv_out_v: std_logic_vector(15 downto 0);
VARIABLE ff: std_logic_vector(2 downto 0):="000";
VARIABLE i: integer: = 8;
VARIABLE j: integer: = 15;
BEGIN
IF reset = '0' THEN i:= 8; j: = 15;
ELSIF Rising_edge(clk) THEN
IF i > 0 THEN
ff: = ff(1 downto 0) & conv_in(i-1) ;
conv_out_v(j): = ff(0) xor ff(2);
conv_out_v(j-1): = ff(0) xor ff(1) xor ff(2);
Phn C: Ph lc v ti liu tham kho
END IF;
j: = j-2;
i: = i-1 ;
END IF;
IF i = 0 THEN
conv_out <= conv_out_v(15 downto 0) ;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
CONVERTER.VHD
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
PACKAGE converter IS
FUNCTION conv_std_logic(gt_v: in INTEGER; sl_v: in INTEGER)
RETURN std_logic_vector;
FUNCTION conv_int(gt_i: in std_logic_vector(1 downto 0)) RETURN
integer;
END converter;
PACKAGE BODY converter IS
FUNCTION conv_std_logic(gt_v,sl_v: integer) RETURN std_logic_vector
IS
VARIABLE i_v: integer range 0 to (gt_v - 1): = 0;
VARIABLE u_v: std_logic_vector(sl_v downto 0);
BEGIN
IF gt_v /= 0 THEN
FOR i in 0 to (gt_v - 1) LOOP
u_v: = u_v + 1;
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END LOOP;
END IF;
RETURN u_v;
END conv_std_logic;
FUNCTION conv_int(gt_i: in std_logic_vector(1 downto 0)) RETURN
integer IS
VARIABLE i_i, u_i: integer;
BEGIN
CASE gt_i IS
WHEN "00" => i_i: = 0;
WHEN "01" => i_i: = 1;
WHEN "10" => i_i: = 2;
WHEN others => i_i: = 3;
END CASE;
RETURN i_i;
END conv_int;
END converter;
DISTANCE.VHD
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.converter.all;
PACKAGE distance IS
FUNCTION hamming(i1,i2: in std_logic_vector(1 downto 0)) RETURN
integer;
FUNCTION euclid(e1,e2: in std_logic_vector(1 downto 0)) RETURN
integer;
END distance;
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PACKAGE BODY distance IS
FUNCTION hamming(i1,i2: in std_logic_vector(1 downto 0)) RETURN
integer IS
VARIABLE result: integer: = 0;
VARIABLE u: std_logic_vector(1 downto 0);
BEGIN
IF i1(0) > '0' THEN
u(0): = '1';
ELSE
u(0): = '0';
END IF;
IF i1(1) > '0' THEN
u(1): = '1';
ELSE
u(1): = '0';
END IF;
IF u(0) = i2(0) THEN
result: = 0;
ELSE
result: = result + 1;
END IF;
IF u(1) = i2(1) THEN
result: = result;
ELSE
result: = result + 1;
END IF;
RETURN result;
END hamming;
END distance;
Phn C: Ph lc v ti liu tham kho
DISPLAY.VHD
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package display_types is
type display_mode is ( name, information,author, inoutbit, bits);
end package display_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.display_types.all;
USE work.lcd_types.all;
package display_components is
component display is
PORT (
reset, clock: IN STD_LOGIC;
SW : IN std_logic_vector(17 downto 0);
DATA_OUT: IN std_logic_vector(7 downto 0);
mode: IN display_mode;
lcd_dd: OUT CHAR_VECTOR(0 to 31)
);
end component;
end package;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE work.display_types.all;
USE work.lcd_types.all;
USE work.lcd_conv.all;
ENTITY display IS
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PORT (
reset, clock: IN STD_LOGIC;
SW : IN std_logic_vector(17 downto 0);
DATA_OUT: IN std_logic_vector(7 downto 0);
mode: IN display_mode;
lcd_dd: OUT CHAR_VECTOR(0 to 31)
);
END ENTITY display;
ARCHITECTURE display OF display IS
SIGNAL A: char: = x"41";SIGNAL B: char: = x"42";
SIGNAL C: char: = x"43";SIGNAL D: char: = x"44";
SIGNAL E: char: = x"45";SIGNAL F: char: = x"46";
SIGNAL G: char: = x"47";SIGNAL H: char: = x"48";
SIGNAL I: char: = x"49";SIGNAL J: char: = x"4A";
SIGNAL K: char: = x"4B";SIGNAL L: char: = x"4C";
SIGNAL M: char: = x"4D";SIGNAL N: char: = x"4E";
SIGNAL O: char: = x"4F";SIGNAL P: char: = x"50";
SIGNAL Q: char: = x"51";SIGNAL R: char: = x"52";
SIGNAL S: char: = x"53";SIGNAL T: char: = x"54";
SIGNAL U: char: = x"55";SIGNAL V: char: = x"56";
SIGNAL W: char: = x"57";SIGNAL X: char: = x"58";
SIGNAL Y: char: = x"59";SIGNAL Z: char: = x"5A";
SIGNAL s1: char: = x"31";SIGNAL s6: char: = x"36";
SIGNAL s2: char: = x"32";SIGNAL s7: char: = x"37";
SIGNAL s3: char: = x"33";SIGNAL s8: char: = x"38";
SIGNAL s4: char: = x"34";SIGNAL s9: char: = x"39";
SIGNAL s5: char: = x"35";SIGNAL s0: char: = x"30";
SIGNAL KT: char: = x"20"; -- KHOANG TRONG
BEGIN
-- the first row
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with mode select lcd_dd(0 to 15) <=
-- DH SPKT TP HCM
(KT,D,H,KT,S,P,K,T,KT,T,P,KT,H,C,M,KT) when information,
-- GIAI THUAT
(KT,KT,G,I,A,I,KT,KT,T,H,U,A,T,KT,KT,KT) when name,
--SVTH LE DUY
(S,V,T,H,KT,KT,L,E,KT,D,U,Y,KT,KT,KT,KT) when author,
--16 BITS VAO
(s1,s6,KT,B,I,T,S,KT,V,A,O,KT,KT,KT,KT,KT) when inoutbit,
-- hien thi 16 bitS vao
(b162slv(SW(15 downto 0))) when bits;
-- the second row
with mode select lcd_dd(16 to 31) <=
--DO AN TOT NGHIEP
(D,O,KT,A,N,KT,T,O,T,KT,N,G,H,I,E,P) when information,
-- VITERBI
(KT,KT,KT,KT,V,I,T,E,R,B,I,KT,KT,KT,KT,KT) when name,
-- HUYNH MINH KHA
(KT,H,U,Y,N,H,KT,M,I,N,H,KT,K,H,A,KT) when author,
--8 BIT RA
(s8,KT,B,I,T,S,KT,R,A,KT,KT,KT,KT,KT,KT,KT) when inoutbit,
-- hien thi 8 bits ra
(b82slv(DATA_OUT(7 downto 0))) when bits;
END ARCHITECTURE display;
LCD.VHD
library ieee;
use ieee.std_logic_1164.all;
package lcd_types is
subtype char is std_logic_vector(7 downto 0);
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type char_vector is array(natural range <>) of char;
end package lcd_types;
library ieee;
use ieee.std_logic_1164.all;
use work.lcd_types.all;
package lcd_components is
component lcd is
port(
reset, clock: IN STD_LOGIC;
dd: IN CHAR_VECTOR(0 to 31);
LCD_ON: OUT STD_LOGIC;
LCD_BLON: OUT STD_LOGIC;
LCD_RW: OUT STD_LOGIC;
LCD_EN: OUT STD_LOGIC;
LCD_RS: OUT STD_LOGIC;
LCD_DATA: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component lcd;
end package lcd_components;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.lcd_types.all;
ENTITY lcd IS
PORT(
reset, clock: IN STD_LOGIC;
dd: IN CHAR_VECTOR(0 to 31);
LCD_ON: OUT STD_LOGIC;
LCD_BLON: OUT STD_LOGIC;
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LCD_RW: OUT STD_LOGIC;
LCD_EN: OUT STD_LOGIC;
LCD_RS: OUT STD_LOGIC;
LCD_DATA: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY lcd;
ARCHITECTURE lcd of lcd is
SIGNAL wait_counter: INTEGER: = 0;
SIGNAL timing_counter: INTEGER: = 0;
TYPE timing_states IS (idle, setup, hold);
SIGNAL timing_state: timing_states: = idle;
TYPE timing_modes IS (idle, read_cmd, read_data, write_cmd, write_data);
SIGNAL timing_mode: timing_modes: = idle;
SIGNAL timing_done: STD_LOGIC: = '1';
CONSTANT init_cmds_count: INTEGER: = 4;
CONSTANT init_cmds: CHAR_VECTOR(0 to init_cmds_count - 1): = (
x"38", -- set up interface
x"0C",-- set up display
x"01", -- clear screen
x"06" -- set up entry mode
);
CONSTANT init_cmds_wait: INTEGER: = 100000; -- wait 2 ms for each
init command
TYPE states IS (
init,
init_cmd,
init_cmd_complete,
update_dd,
update_dd_addr,
update_dd_addr_complete,
update_dd_data,
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update_dd_data_complete
);
SIGNAL state: states: = init;
SIGNAL i, j: INTEGER: = 0;
BEGIN
LCD_ON <= '1';
LCD_BLON <= '1';
timing: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
timing_state <= idle;
timing_counter <= 0;
timing_done <= '1';
ELSIF (clock = '1' AND clock'event) THEN
IF (timing_counter > 0) THEN
timing_counter <= timing_counter - 1;
ELSE
CASE timing_state IS
WHEN idle =>
CASE timing_mode IS
WHEN idle =>
LCD_RS <= '0';
LCD_RW <= '1';
timing_done <= '1';
timing_state <= idle;
WHEN read_cmd =>
LCD_RS <= '0';
LCD_RW <= '1';
timing_done <= '0';
timing_counter <= 3;
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timing_state <= setup;
WHEN read_data =>
LCD_RS <= '1';
LCD_RW <= '1';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
WHEN write_cmd =>
LCD_RS <= '0';
LCD_RW <= '0';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
WHEN write_data =>
LCD_RS <= '1';
LCD_RW <= '0';
timing_done <= '0';
timing_counter <= 3;
timing_state <= setup;
END CASE;
WHEN setup =>
LCD_EN <= '1';
timing_counter <= 30;
timing_state <= hold;
WHEN hold =>
LCD_EN <= '0';
timing_counter <= 3000; -- a 60 microsecond wait
guarantees operation execution
timing_state <= idle;
WHEN others =>
timing_state <= idle;
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END CASE;
END IF;
END IF;
END PROCESS;
fsm: PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
timing_mode <= idle;
state <= init;
ELSIF (clock = '1' AND clock'event) THEN
IF (timing_mode /= idle) THEN
timing_mode <= idle;
ELSIF (timing_done /= '1') THEN
ELSIF (wait_counter > 0) THEN
wait_counter <= wait_counter - 1;
ELSE
CASE state IS
WHEN init =>
i <= 0;
timing_mode <= idle;
wait_counter <= init_cmds_wait;
state <= init_cmd;
WHEN init_cmd =>
LCD_DATA <= init_cmds(i);
timing_mode <= write_cmd;
wait_counter <= init_cmds_wait;
state <= init_cmd_complete;
WHEN init_cmd_complete =>
IF (i = init_cmds_count - 1) THEN
state <= update_dd; -- sai
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ELSE
i <= i + 1;
state <= init_cmd;
END IF;
WHEN update_dd => -- hien thi lcd 16X2
i <= 0;
j <= 0;
state <= update_dd_addr;
WHEN update_dd_addr =>
LCD_DATA <= "1" & std_logic_vector(to_unsigned(i,
1)) & "00" & std_logic_vector(to_unsigned(j, 4));
timing_mode <= write_cmd;
state <= update_dd_addr_complete;
WHEN update_dd_addr_complete =>
state <= update_dd_data;
WHEN update_dd_data =>
LCD_DATA <= dd(i * 16 + j);
timing_mode <= write_data;
state <= update_dd_data_complete;
WHEN update_dd_data_complete =>
IF (j = 15) THEN
IF (i = 1) THEN
state <= update_dd; -- quay lai lam lai
ELSE
j <= 0;
i <= i + 1;
state <= update_dd_addr;
END IF;
ELSE
j <= j + 1;
state <= update_dd_addr;
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END IF;
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE lcd;
LCD_CONV.VHD
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE lcd_conv_type is
TYPE out_vector is array (0 to 15 ) of std_logic_vector(7 downto 0);
END PACKAGE lcd_conv_type;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE work.lcd_types.all;
USE work.lcd_conv_type.all;
PACKAGE lcd_conv IS
FUNCTION b162slv(bin: in std_logic_vector(15 downto 0)) RETURN
char_vector;
FUNCTION b82slv(bin: in std_logic_vector(7 downto 0)) RETURN
char_vector;
END lcd_conv;
PACKAGE BODY lcd_conv IS
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FUNCTION b162slv(bin: in std_logic_vector(15 downto 0)) RETURN char_vector
IS
VARIABLE slv: char_vector (15 downto 0) ;
VARIABLE t: integer;
BEGIN
FOR t in 0 to 15 LOOP
CASE bin(t) IS
WHEN '0' => slv(t): = x"30"; -- 0
WHEN others => slv(t): = x"31"; -- 1
END CASE;
END LOOP;
RETURN slv;
END b162slv;
FUNCTION b82slv(bin: in std_logic_vector(7 downto 0)) RETURN char_vector IS
VARIABLE slv: char_vector (15 downto 0);
VARIABLE t: integer;
BEGIN
FOR t in 0 to 7 LOOP
CASE bin(t) IS
WHEN '0' => slv(t+4): = x"30";
WHEN others => slv(t+4): = x"31";
END CASE;
END LOOP;
FOR t in 0 to 3 LOOP
slv(t): = x"20"; -- khoang trang
END LOOP;
FOR t in 12 to 15 LOOP
slv(t): = x"20"; -- khoang trang
END LOOP;
RETURN slv;
END b82slv;
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END lcd_conv;
II. Ti liu tham kho
[1] John Proakis, Digital Communications (Chapter 8-Block and Convolutional
Channel Codes), McGraw-Hill Science/ Engineering/ Math, 4
th
, 2000.
[2] Fu Hua Huang, Evaluation of Soft Output Decoding for Turbo
Codes(chapter 2_convolution codes), Master's Thesis, 1997.
[3] Mr. Chip Fleming, Tutorial on Convolutional Coding with Viterbi
Decoding, Spectrum Applications, 2006.
[4] Wei Chen, RTL implementation of Viterbi decoder, Masters thesis
performed in Computer Engineering, 2006.
[5] Nguyn Minh Khnh Ngc, Lun vn cao hc Thit k v thc hin gi
thut Viterbi trn FPGA, 2009.
[6] Mt s trang web m nhm c tham kho:
http://www.altera.com
http://www.fotech.org
http://www.ngohaibac.net
http://www.mathwork.com
http://en.wikipedia.org
http://www.dsplog.com
http://home.netcom.com
http://gaussianwaves.blogspot.com
Phn C: Ph lc v ti liu tham kho