Tema #2 C. A1. A0. B1. B0. S3. S2. S1. S0. P. L H H H H H H H H H 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 C.

L = H Suma Gray 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1

C.L = L Suma XS3

Tema 3

F1 puesta en el mapa.

F1 simplificada

Circuito solo con NAND

Circuito con NOR

Funcin Original en el mapa

Simplificacin por pasos

a. Reduccin del termino

b. Reduccin del termino

c. Reduccin del termino

d. Reduccin del termino

e. Reduccin del termino

f. Reduccin del termino

g. Todo junto

Circuito POS

Circuito NAND

Circuito NOR

Funcin Simplificada

Circuito POS

Circuito NAND

Circuito NOR

Problema #4 library ieee; use ieee.std_logic_1164.all; entity TEMA_4 is port ( A,B,C : in std_logic_vector(3 downto 0); Co S Fin end entity TEMA_4; architecture RTL of TEMA_4 is signal X : std_logic_vector(3 downto 0); begin With Co Select X <= not(A) When "00", <= (B xor C) When "01", <= (A and B) When "10", <= "ZZZ" when others; Fin <= '0' when Co = "11" else '1'; end architecture RTL; : in std_logic_vector(1 downto 0); : out std_logic_vector(3 downto 0); : out std_logic);