MT29F4G08ABCH

Micron Confidential and Proprietary
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Features
NAND Flash Memory

MT29F4G08AAC, MT29F4G16AAC, MT29F4G08ABC, MT29F4G16ABC, MT29F8G08EACC3 Features
Figure 1: TSOP Example
ONFI 1.0 compliant1 Single-level cell (SLC) technology Organization Page size: x8: 2,112 bytes (2,048 + 64 bytes) x16: 1,056 words (1,024 + 32 words) Block size: 64 pages (128K + 4K bytes) Plane size: 2,048 blocks Device size: 4Gb: 4,096 blocks READ performance Sequential READ: 3.3V: 25ns (MIN) 1.8V: 35ns (MIN) WRITE performance PROGRAM PAGE: 220s (TYP) 3.3V PROGRAM PAGE: 300s (TYP) 1.8V BLOCK ERASE: 2ms (TYP) BLOCK LOCK (1.8V only) Data retention: 10 years Endurance: 100,000 PROGRAM/ERASE cycles First block (block address 00h) guaranteed to be valid with ECC when shipped from factory2 Industry-standard basic NAND Flash command set Advanced command set: PROGRAM PAGE CACHE MODE PAGE READ CACHE MODE One-time programmable (OTP) commands Two-plane commands Interleaved die operations READ UNIQUE ID Operation status byte provides a software method of detecting: Operation completion Pass/fail condition Write-protect status Ready/busy# (R/B#) signal provides a hardware method of detecting operation completion WP# signal: write protect entire device RESET required after power-up
INTERNAL DATA MOVE operations supported within the plane from which data is read
Options
Density: 4Gb, single die 8Gb, dual die (3.3V x8 only) Device width: x8, x16 Configuration: # of die # of CE# # of R/B# I/O 1 1 1 Common 2 2 2 Separate Vcc: 2.73.6V A 1.651.95V B Package: 48-pin TSOP Type 1 OCPL3 (lead-free plating) 52-pad ULGA (8Gb only) 63-ball VFBGA (1.8V only) Operating temperature: Extended (40C to +85C) Commercial (0C to +70C) Notes: 1. This data sheet includes only part of the ONFI specification. 2. See Error Management on page 75. 3. OCPL = off-center parting line.
NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__1.fm - Rev. 1.5 4/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
Draft 4/ 20/ 2008
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Part Numbering Information
Part Numbering Information

Micron NAND Flash devices are available in several different configurations and densities (see Figure 2). Figure 2: Part Number Chart
MT 29F 4G 08 Micron Technology Product Family
29F = Single-supply NAND Flash memory
C3
:C Design Revision
C = Third revision
Production Status
Blank = Production ES = Engineering sample MS = Mechanical sample QS = Qualification sample
Density
4G = 4Gb 8G = 8Gb
Device Width
08 = 8 bits 16 = 16 bits
Operating Temperature Range

Blank = Commercial (0C to +70C)
Classification
# of die # of CE# # of R/B# I/O
Blank 1 2 Common Separate
A E
1 2
1 2
Flash Performance
Blank = Standard
Operating Voltage Range

A = 3.3V (2.73.6V) B = 1.8V (1.651.95V)
Package Code
C3 = 52-pad ULGA HC = 63-ball VFBGA (lead-free) WC = 48-pin TSOP OCPL Type 1 (lead-free)
Feature Set
C = Feature set C
Valid Part Number Combinations

After building the part number from the part numbering chart, verify that the part number is offered and valid by using the Micron Parametric Part Search Web site at www.micron.com/products/parametric. If the device required is not on this list, contact the factory.
Draft 4/ 20/ 2008
Reserved for Future Use
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Table of Contents Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RANDOM DATA READ 05h-E0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PAGE READ CACHE MODE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 READ UNIQUE ID (EDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 READ PARAMETER PAGE ECh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Internal Data Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PROGRAM for INTERNAL DATA MOVE 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Block Lock Feature (1.8V only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 WP# and Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 UNLOCK 23h-24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LOCK 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LOCK-TIGHT 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 BLOCK LOCK READ STATUS 7Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 One-Time Programmable (OTP) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 OTP DATA PROGRAM A0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 OTP DATA PROTECT A5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 OTP DATA READ AFh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Features Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 GET FEATURES EEh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SET FEATURES EFh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TWO-PLANE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Two-Plane Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50aTOC.fm - Rev. 1.5 4/08 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
Draft 4/ 20/ 2008
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Table of Contents

TWO-PLANE PAGE READ 00h-00h-30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TWO-PLANE RANDOM DATA READ 06h-E0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TWO-PLANE INTERNAL DATA MOVE 00h-00h-35h/85h-11h-85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TWO-PLANE READ for INTERNAL DATA MOVE 00h-00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 TWO-PLANE BLOCK ERASE 60h-D1h-60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TWO-PLANE/MULTIPLE-DIE READ STATUS 78h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50aTOC.fm - Rev. 1.5 4/08 EN
Draft 4/ 20/ 2008
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory List of Figures List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: TSOP Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Assignment (Top View) 48-Pin TSOP OCPL Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment (Top View) 52-Pad ULGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ball Assignment: 63-Ball VFBGA (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ball Assignment: 63-Ball VFBGA (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Map for MT29F4G08xxx (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory Map for MT29F4G16xxx (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Array Organization for MT29F4G08xxx (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Array Organization for MT29F4G16xxx (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PAGE READ CACHE MODE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 READ UNIQUE ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 READ PARAMETER PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 INTERNAL DATA MOVE with Optional RANDOM DATA OUTPUT and RANDOM DATA INPUT 40 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Flash Array Protected: Inverted Area Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Flash Array Protected: Invert Area Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 UNLOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LOCK-TIGHT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PROGRAM/ERASE Issued to Locked Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 BLOCK LOCK READ STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 BLOCK LOCK Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 OTP DATA PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 OTP PROGRAM with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 OTP DATA PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 OTP DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 OTP DATA READ with RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Get Features EEh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Set Features EFh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TWO-PLANE PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TWO-PLANE PAGE READ with RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TWO-PLANE PROGRAM PAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 TWO-PLANE PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TWO-PLANE INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ . . . . . . . . . . . 68 TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . 69 TWO-PLANE BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory List of Figures

Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: Figure 68: Figure 69: Figure 70: Figure 71: Figure 72: Figure 73: Figure 74: Figure 75: Figure 76: Figure 77: Figure 78: Figure 79: Figure 80: Figure 81: Figure 82: Figure 83: Figure 84: Figure 85: Figure 86: Figure 87: Figure 88: Figure 89: Figure 90: Figure 91: Figure 92: Figure 93: Figure 94: Figure 95: ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PROGRAM for INTERNAL DATA MOVE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PROGRAM for INTERNAL DATA MOVE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TWO-PLANE ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TWO-PLANE ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TWO-PLANE PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TWO-PLANE PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TWO-PLANE PROGRAM for INTERNAL DATA MOVE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TWO-PLANE PROGRAM for INTERNAL DATA MOVE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Interleaved PROGRAM for INTERNAL DATA MOVE with Status Register Monitoring . . . . . . . . 78 AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SERIAL ACCESS Cycle After READ (EDO Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 TWO-PLANE/MULTIPLE-DIE READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 READ Operation with CE# Dont Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PAGE READ CACHE MODE Operation, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PAGE READ CACHE MODE Operation, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Program Operation with CE# Dont Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PROGRAM PAGE CACHE MODE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PROGRAM PAGE CACHE MODE Operation Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 48-Pin TSOP OCPL Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 52-Pad ULGA/VLGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 63-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory List of Tables List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operational Example for MT29F4G08xxx (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Array Addressing for MT29F4G16xxx (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Array Addressing: MT29F4G08xxx (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Array Addressing for MT29F4G16xxx (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block-Lock Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Two-Plane Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device ID and Configuration Codes for Address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Device ID and Configuration Codes for Address 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ONFI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Block Lock Address Cycle Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Block Lock Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Features Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Feature Address 01h: Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Feature Address 80h: Programmable I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Feature Address 81h: Programmable R/B# Pull-down Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Error Management Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DC and Operating Characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DC and Operating Characteristics (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AC Characteristics: Command, Data, and Address Input (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AC Characteristics: Command, Data, and Address Input (1.8V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AC Characteristics: Normal Operation (1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 AC Characteristics: Normal Operation (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory General Description
General Description
NAND Flash technology provides a cost-effective solution for applications requiring high-density, solid-state storage. The MT29F4Gxxxxx is a 4Gb NAND Flash memory device. The MT29F8Gxxxxxxx is a two-die stack that operates as two separate 4Gb devices. Micron NAND Flash devices include standard NAND Flash features as well as new features designed to enhance system-level performance. Micron NAND Flash devices use a highly multiplexed 8-bit bus (I/O[7:0]) or 16-bit bus (I/O[15:0]) to transfer data, addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#) implement the NAND Flash command bus interface protocol. Additional pins control hardware write protection (WP#) and monitor the device ready/busy (R/B#) state. This hardware interface creates a low-pin-count device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities without board redesign. The MT29F4G and MT29F8G devices contain two planes per die. Each plane consists of 2,048 blocks. Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes. The pages are further divided into a 2,048-byte data storage region with a separate 64-byte area. The 64-byte area is typically used for error management functions. The contents of each page can be programmed in tPROG (TYP), and an entire block can be erased in tBERS (TYP). On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. PROGRAM/ERASE endurance is specified at 100,000 cycles using appropriate error correction code (ECC) and error management.
Figure 3:
Pin Assignment (Top View) 48-Pin TSOP OCPL Type 1

x16
NC NC NC NC NC NC R/B# RE# CE# NC NC Vcc Vss NC NC CLE ALE WE# WP# NC NC NC NC NC
x8
NC NC NC NC NC NC R/B# RE# CE# NC NC Vcc Vss NC NC CLE ALE WE# WP# NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
x8
Vss2 DNU NC NC I/O7 I/O6 I/O5 I/O4 NC Vcc2 DNU Vcc Vss NC Vcc2 NC I/O3 I/O2 I/O1 I/O0 NC NC DNU Vss2
x16
Vss I/O15 I/O14 I/O13 I/O7 I/O6 I/O5 I/O4 I/O12 Vcc DNU Vcc Vss NC Vcc I/O11 I/O3 I/O2 I/O1 I/O0 I/O10 I/O9 I/O8 Vss
Notes: 1. For package dimensions, see Figure 93 on page 100. 2. These pins might not be bonded in the package. However, Micron recommends that the customer connect these pins to the designated external sources for ONFI compatibility.
Draft 4/ 20/ 2008
Preliminary

Figure 4: Pin Assignment (Top View) 52-Pad ULGA
0 1 2 3 4 5 6 7 8
OA
NC A
NC CLE CE# NC
NC
VSS
VCC
OB
NC C
ALE CLE-2
1
NC
CE2#
1
RE#
ALE-2
RE2#1
OC
DNU E
WE2# WE# R/B# R/B2#1
DNU
F
I/O0-21
WP#
VSS
I/O0
WP2#1
I/O7-21
H
I/O1-21
I/O1
I/O7
I/O2
I/O6
I/O6-21
OD
DNU/ VSS K
I/O2-21 I/O3 I/O5
DNU
VSS
I/O4
I/O5-21
OE
NC M
DNU/ VCC VSS VCC DNU/ VCC
DNU/ VSS
I/O3-21
I/O4-21
OF
NC
NC
Top View, Pads Down

Notes: 1. These signals are available only on 8Gb devices. These pads are NC for other configurations.
Draft 4/ 20/ 2008
Preliminary

Figure 5: Ball Assignment: 63-Ball VFBGA (x8)
10
NC
NC
NC
NC
NC
NC
NC
WP#
ALE
Vss
CE#
WE#
R/B#
Vcc
RE#
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
NC
NC
Vcc
LOCK
NC
NC
NC
NC
I/O0
NC
NC
NC
Vcc
NC
I/O1
NC
Vcc
I/O5
I/O7
Vss
I/O2
I/O3
I/O4
I/O6
Vss
NC
NC
NC
NC
NC
NC
NC
NC
Top View, Ball Down
Note:
For package dimensions, see Figure 95 on page 102.
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Preliminary

Figure 6: Ball Assignment: 63-Ball VFBGA (x16)
10
NC
NC
NC
NC
NC
NC
NC
WP#
ALE
Vss
CE#
WE#
R/B#
Vcc
RE#
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
NC
NC
Vcc
LOCK
I/O13
I/O15
NC
I/O8
I/O0
I/O10
I/O12
I/O14
Vcc
I/O9
I/O1
I/O11
Vcc
I/O5
I/O7
Vss
I/O2
I/O3
I/O4
I/O6
Vss
NC
NC
NC
NC
NC
NC
NC
NC
Top View, Ball Down
Note:
For package dimensions, see Figure 95 on page 102.
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Preliminary

Table 1: Signal Descriptions
Type Input Description Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register on the rising edge of WE#. When address information is not being loaded, ALE should be driven LOW. Chip enable: This gates transfers between the host system and the NAND Flash device. After the device starts a PROGRAM or ERASE operation, CE# can be deasserted. See Bus Operation on page 18 for additional operational details. Command latch enable: When CLE is HIGH, information is transferred from I/O[7:0] to the on-chip command register on the rising edge of WE#. When command information is not being loaded, CLE should be driven LOW. Read enable: This gates transfers from the NAND Flash device to the host system. Write enable: This gates transfers from the host system to the NAND Flash device. Write protect: This protects against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when WP# is LOW. Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs.
Symbol ALE, ALE2
CE#, CE2#
Input
CLE, CLE2
Input
RE#, RE#2 WE#, WE#2 WP#, WP#2 I/O[7:0] (x8) I/O[15:0] (x16) I/O[7-2:0-2] (MT29F8G) R/B#, RB#2
Input Input Input I/O
Output
VCC VSS NC DNU
Supply Supply
Ready/Busy: This is an open-drain, active-LOW output that uses an external pullup resistor. R/B# is used to indicate when the chip is processing a PROGRAM or ERASE operation. It is also used during READ operations to indicate when data is being transferred from the array into the serial data register. When these operations have completed, R/B# returns to the high-impedance state. VCC: This is the power supply. VSS: This is the ground connection. No connect: NCs are not internally connected. They can be driven or left unconnected. Do not use: DNUs must be left unconnected.
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. This provides a memory device with a low pin count. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder or a column decoder to select a row address or a column address, respectively. The data are transferred to or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data, whereas the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The NAND Flash memory array is programmed and read in page-based operations and is erased in block-based operations. During normal page operations, the data and cache registers are tied together and act as a single register. During cache operations the data and cache registers operate independently to increase data throughput. These devices also have a status register that reports the status of device operation.
Figure 7:
NAND Flash Functional Block Diagram

VCC VSS
I/Ox
I/O Control
Address Register Status Register
Command Register
CE# CLE ALE WE# RE# WP# Row Decode Column Decode
Control Logic
NAND Flash Array (2 planes)
Data Register R/B# Cache Register
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Addressing
Addressing
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using a 5-cycle sequence as shown in Table 4 on page 16 and Table 5 on page 17. See Figure 8 for additional memory mapping and addressing details.
Memory Mapping
Figure 8: Memory Map for MT29F4G08xxx (x8)
0 1 2 4,095
Blocks 4Gb: BA[17:6]
Pages PA[5:0]
63
Bytes CA[11:0]
2,047
2,111
Spare area
Table 2:
Block 0 0 0 4,095 4,095
Operational Example for MT29F4G08xxx (x8)

Page 0 1 2 62 63 Min Address in Page 0x0000000000 0x0000010000 0x0000020000 0x03FFFE0000 0x03FFFF0000 Max Address in Page 0x000000083F 0x000001083F 0x000002083F 0x03FFFE083F 0x03FFFF083F Out of Bounds Addresses in Page 0x00000008400x0000000FFF 0x00000108400x0000010FFF 0x00000208400x0000020FFF 0x03FFFE08400x03FFFE0FFF 0x03FFFF08400x03FFFF0FFF
Notes: 1. As shown in Table 4 on page 16, the high nibble of ADDRESS cycle 2 has no assigned address bits; however, these 4 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to them. 2. The 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are out of bounds, do not exist in the device, and cannot be addressed.
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Memory Mapping

Figure 9: Memory Map for MT29F4G16xxx (x16)
0 1 2 4,095
Blocks BA[17:6]
Pages PA[5:0]
63
Words CA[10:0]
1,023
1,055
Spare area
Table 3:
Block 0 0 0 4,095 4,095
Array Addressing for MT29F4G16xxx (x16)

Page 0 1 2 62 63 Min Address in Page 0x0000000000 0x0000010000 0x0000020000 0x03FFFE0000 0x03FFFF0000 Max Address in Page 0x000000041F 0x000001041F 0x000002041F 0x03FFFE041F 0x03FFFF041F Out of Bounds Addresses in Page 0x00000004200x0000000FFF 0x00000104200x0000010FFF 0x00000204200x0000020FFF 0x03FFFE04200x03FFFE0FFF 0x03FFFF04200x03FFFF0FFF
Notes: 1. As shown in Table 5 on page 17, the upper 5 bits of ADDRESS cycle 2 have no assigned address bits; however, these 5 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to them. 2. The 11-bit column address is capable of addressing from 0 to 2,047 words on x16 devices; however, only words 0 through 1,055 are valid. Words 1,056 through 2,048 of each page are out of bounds, do not exist in the device, and cannot be addressed.
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Array Organization
Array Organization
Figure 10: Array Organization for MT29F4G08xxx (x8)
2,112 bytes
Cache Register Data Register
2,112 bytes
I/O7
2,048 2,048
64 64
2,048 2,048
64 64
I/O0
1 page 2,048 blocks per plane 4,096 blocks per device 1 block
= (2K + 64 bytes) = (2K + 64) bytes x 64 pages = (128K + 4K) bytes = (128K + 4K) bytes x 2,048 blocks = 2,112Mb
1 block
1 block
1 plane
1 device = 2,112Mb x 2 planes = 4,224Mb Plane of Plane of even-numbered blocks odd-numbered blocks (0, 2, 4, 6, ..., 4,092, 4,094) (1, 3, 5, 7, ..., 4,093, 4,095)
Notes: 1. For the 8Gb MT29F8G, the 4Gb array organization shown applies to each chip enable (CE#, CE2#).
Table 4:
Cycle First Second Third Fourth Fifth
Array Addressing: MT29F4G08xxx (x8)

I/O7 CA7 LOW BA7 BA15 LOW I/O6 CA6 LOW BA6 BA14 LOW I/O5 CA5 LOW PA5 BA13 LOW I/O4 CA4 LOW PA4 BA12 LOW I/O3 CA3 CA11 PA3 BA11 LOW I/O2 CA2 CA10 PA2 BA10 LOW I/O1 CA1 CA9 PA1 BA9 BA17 I/O0 CA0 CA8 PA0 BA8 BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. If CA11 is 1, then CA[10:6] must be 0. 3. BA6 controls plane selection.
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Array Organization

Figure 11: Array Organization for MT29F4G16xxx (x16)
1,056 words
Cache Register Data Register
1,056 words
I/O15
1,024 1,024
32 32
1,024 1,024
32 32
I/O0
1 page 2,048 blocks per plane 4,096 blocks per device 1 block
= (1K + 32 words) = (1K + 32) words x 64 pages = (64K + 2K) words = (64K + 2K) words x 2,048 blocks = 2,112Mb = 2,112Mb x 2 planes = 4,224Mb
1 block
1 block
1 plane 1 device
Table 5:
Cycle First Second Third Fourth Fifth
Array Addressing for MT29F4G16xxx (x16)

I/O[15:8] LOW LOW LOW LOW LOW I/O7 CA7 LOW BA7 BA15 LOW I/O6 CA6 LOW BA6 BA14 LOW I/O5 CA5 LOW PA5 BA13 LOW I/O4 CA4 LOW PA4 BA12 LOW I/O3 CA3 LOW PA3 BA11 LOW I/O2 CA2 CA10 PA2 BA10 LOW I/O1 CA1 CA9 PA1 BA9 BA17 I/O0 CA0 CA8 PA0 BA8 BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. If CA10 = 1, then CA[9:5] must be 0. 3. BA6 controls plane selection.
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Plane of even-numbered blocks (0, 2, 4, 6, ..., 4,092, 4,094)
Plane of odd-numbered blocks (1, 3, 5, 7, ..., 4,093, 4,095)
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Bus Operation
Bus Operation
The bus on the MT29Fxxxxxxx device is multiplexed. Data I/O, addresses, and commands all share the same pins. The 8Gb device has two independent data I/O and command pads. These are I/O[7:0], CE#, WE#, RE#, CLE, ALE, WP#, I/O[7-2:0-2], CE2#, WE2#, RE2#, CLE2, ALE2, and WP2#. Addresses and commands are always supplied on I/O[7:0]. I/O[15:8] are used only for data in the x16 configuration. The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS INPUT cycles, and one or more DATA cycleseither READ or WRITE.
Control Signals
CE#, WE#, RE#, CLE, ALE, and WP# control NAND Flash device READ and WRITE operations. On the 8Gb MT29F8G device, CE# and CE2# control an independent 4Gb array. CE2# functions the same as CE# for its own array; all operations described for CE# also apply to CE2#. CE# is used to enable the device. When CE# is LOW and the device is not in the busy state, the NAND Flash memory will accept command, address, and data information. When the device is not performing an operation, the CE# pin is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption. See Figure 78 on page 90 and Figure 86 on page 96 for examples of CE# Dont Care operations. The CE# Dont Care operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus. A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring.
Commands
Commands are written to the command register on the rising edge of WE# when: CE# and ALE are LOW, and CLE is HIGH, and The device is not busy As exceptions, the device accepts the READ STATUS, TWO-PLANE/MULTIPLE-DIE READ STATUS, and RESET commands when busy. Commands are transferred to the command register on the rising edge of WE# (see Figure 70 on page 86). Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written with zeroes when a command is issued.
Address Input
Addresses are written to the address register on the rising edge of WE# when: CE# and CLE are LOW, and ALE is HIGH Addresses are input on I/O[7:0]. Bits not part of the address space must be LOW. For devices with a x16 interface, I/O[15:8] must be written with zeroes when an address is issued (see Figure 71 on page 86). The number of ADDRESS cycles required for each command varies. Refer to the command descriptions to determine addressing requirements (see Table 7 on page 23).
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Bus Operation Data Input
Data is written to the data register on the rising edge of WE# when: CE#, CLE, and ALE are LOW, and the device is not busy Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices. See Figure 72 on page 87 for additional data input details.
READs
After a READ command is issued, data is transferred from the memory array to the data register on the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after the transfer is complete. When data is available in the data register, it is clocked out of the part by RE# going LOW. See Figure 77 on page 89 for detailed timing information. The READ STATUS (70h) command, TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command, or the R/B# signal can be used to determine when the device is ready. If a controller is using a timing of 30ns or longer for tRC, use Figure 73 on page 87 for proper timing.
Ready/Busy#
The R/B# output provides a hardware method of indicating the completion of PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for proper operation. The signal is typically HIGH, and transitions to LOW after the appropriate command is written to the device. The signal pins open-drain driver enables multiple R/B# outputs to be OR-tied. The READ STATUS command can be used in place of R/B#. Typically, R/B# is connected to an interrupt pin on the system controller (see Figure 12 on page 20). On 8Gb MT29F8G devices, R/B# indicates the 4Gb section enabled by CE#, and R/B2# indicates the 4Gb section enabled by CE2#. R/B# and R/B2# can be tied together or they can be used separately to provide independent indicators for each 4Gb section. The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# pin. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10- to 90-percent points on the R/B# waveform, rise time is approximately two time constants (TC). TC = R C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load. The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# pin and the total load capacitance and may be changed if R/B# pull-down strength is not set to full. Refer to Figure 14 on page 21, which depicts approximate Rp values using a circuit load of 100pF. The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and VCC.
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Preliminary
V CC ( MAX ) V OL ( MAX ) 3.2V Rp ( MIN, 3.3V part ) = --------------------------------------------------------------- = ---------------------------8mA + I L I OL + I L Where I L is the sum of the input currents of all devices tied to the R/B# pin.
V CC ( MAX ) V OL ( MAX ) 1.85V Rp ( MIN, 1.8V part ) = --------------------------------------------------------------- = -------------------------I OL + I L 3mA + I L Where I L is the sum of the input currents of all devices tied to the R/B# pin.
Figure 12:
READY/BUSY# Open Drain
Rp VCC
R/B# Open drain output
IOL GND Device
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Preliminary

Figure 13:
t
Fall and tRise

3.50 3.00 2.50 2.00 V 1.50 1.00 0.50 0.00 -1 0 2 4 TC 0 2 4 6
Vcc 3.3 Vcc 1.8
tFall
tRise
Figure 14:
IOL vs. Rp
3.50 3.00 2.50 2.00
I (mA)
1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 8,000 10,000 12,000
Rp ()
IOL at 3.60V (mA) IOL at 1.95V (mA)
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Notes: 1. 2. 3. 4.
t t
Fall and tRise are calculated at 10 percent and 90 percent points. Rise is primarily dependent on external pull-up resistor and external capacitive loading. tFall: 7ns at 1.8V and 10ns at 3.3V. See TC values in Figure 15 on page 22 for approximate Rp value and TC.
Preliminary

Figure 15: TC vs. Rp
1.20s 1.00s 800ns
T
600ns 400ns 200ns 0ns 0 2k 4k 6k 8k 10k 12k
Rp
IOL at VCC (MAX) RC = TC C = 100pF
Table 6:
CLE H L H L L L X X X X X
Mode Selection
ALE L H L H L L X X X X X CE# L L L L L L X X X X H H H X X X X H X X X X WE# RE# H H H H H WP# X X H H H X X H H L 0V/Vcc1 Data input Sequential read and data output During read (busy) During program (busy) During erase (busy) Write protect Standby Write mode Mode Read mode Command input Address input Command input Address input
Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby. 2. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL.
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions
Command Definitions
Table 7: Command Set
Command Cycle 1 00h 00h 31h 3Fh 00h 05h 90h EDh ECh 70h 78h 80h 80h 85h 85h 60h FFh A0h A5h AFh EEh EFh Number of Address Cycles 5 5 5 2 1 1 1 5 5 5 2 3 5 5 5 1 1 Data Cycles Required1 No No No No No No No No No No No Yes Yes Optional Yes No No Yes No No No 4 Command Cycle 2 30h 31h 35h E0h 10h 15h 10h D0h 10h 10h 30h Valid During Busy No No No No No No No No No Yes Yes No No No No No Yes No No No No No
Command PAGE READ PAGE READ CACHE MODE RANDOM PAGE READ CACHE MODE SEQUENTIAL PAGE READ CACHE MODE LAST READ for INTERNAL DATA MOVE RANDOM DATA READ READ ID READ UNIQUE ID READ PARAMETER PAGE READ STATUS READ STATUS ENHANCED PROGRAM PAGE PROGRAM PAGE CACHE MODE PROGRAM for INTERNAL DATA MOVE RANDOM DATA INPUT BLOCK ERASE RESET OTP DATA PROGRAM OTP DATA PROTECT OTP DATA READ GET FEATURES SET FEATURES
Notes
2 3
2 4
Notes: 1. Indicates required data cycles between command cycle 1 and command cycle 2. 2. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and PROGRAM for INTERNAL DATA MOVE. See Table 4 on page 16 for plane address boundary definitions. 3. RANDOM DATA READ command limited to use within a single page. 4. RANDOM DATA INPUT command limited to use within a single page.
Table 8:
Block-Lock Command Set

Command Cycle 1 23h 2Ah 2Ch 7Ah Number of Address Cycles 3 3 Command Cycle 2 24h Number of Address Cycles 3 Valid During Busy No No No No
Command UNLOCK BLOCK LOCK BLOCK LOCK-TIGHT BLOCK LOCK READ STATUS
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Preliminary

Table 9: Two-Plane Command Set
Command Cycle 1 00h 00h 06h 78h 80h 80h 85h 60h Number of Number of Valid Address Command Address Command During Cycles Cycle 2 Cycles Cycle 3 Busy Notes 5 5 5 3 5 5 5 3 00h 00h E0h 11h-80h 11h-80h 11h-85h D1h-60h 5 5 5 5 5 3 30h 35h 10h 15h 10h D0h No No No Yes No No No No 1 4 1 2 3
Command TWO-PLANE PAGE READ TWO-PLANE READ for INTERNAL DATA MOVE TWO-PLANE RANDOM DATA READ TWO-PLANE/MULTIPLE-DIE READ STATUS TWO-PLANE PROGRAM PAGE TWO-PLANE PROGRAM PAGE CACHE MODE TWO-PLANE PROGRAM for INTERNAL DATA MOVE TWO-PLANE BLOCK ERASE
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Notes: 1. Do not cross plane address boundaries when using TWO-PLANE READ for INTERNAL DATA MOVE or TWO-PLANE PROGRAM for INTERNAL DATA MOVE. See Table 4 on page 16 and Table 5 on page 17 for plane address boundary definitions. 2. The TWO-PLANE RANDOM DATA READ command is limited to use with the TWO-PLANE PAGE READ command. 3. The TWO-PLANE/MULTIPLE-DIE READ STATUS command can be used to check status with two-plane operations, excluding the TWO-PLANE PAGE READ (00h-00h-30h) command. 4. D1h command can be omitted.
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions READ Operations
PAGE READ 00h-30h At power-on, the device defaults to READ mode. To enter READ mode while in operation, write the 00h command to the command register, then write 5 ADDRESS cycles, and conclude with the 30h command. To determine the progress of the data transfer from the NAND Flash array to the data register (tR), monitor the R/B# signal; or alternatively, issue a READ STATUS (70h) command. If the READ STATUS command is used to monitor the data transfer, the user must re-issue the READ (00h) command to receive data output from the data register. See Figure 82 on page 94 and Figure 83 on page 95 for examples. After the READ command has been reissued, pulsing the RE# line will result in outputting data, starting from the initial column address. A serial page read sequence outputs a complete page of data. After 30h is written, the page data is transferred to the data register, and R/B# goes LOW during the transfer. When the transfer to the data register is complete, R/B# returns HIGH. At this point, data can be read from the device. Starting from the initial column address to the end of the page, read the data by repeatedly pulsing RE# at the maximum tRC rate (see Figure 16).
CLE
CE#
WE#
ALE tR R/B#
RE#
I/Ox
00h
Address (5 cycles)
30h
Data output (Serial access)
Dont Care
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Figure 16:
PAGE READ Operation
Preliminary

RANDOM DATA READ 05h-E0h The RANDOM DATA READ command enables the user to specify a new column address so the data at single or multiple addresses can be read. The random read mode is enabled after a normal PAGE READ (00h-30h) sequence. Random data can be output after the initial page read by writing an 05h-E0h command sequence along with the new column address (2 cycles). The RANDOM DATA READ command can be issued without limit within the page. Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially (see Figure 17).
Figure 17:
RANDOM DATA READ Operation

tR
R/B#
RE#
I/Ox
00h
Address (5 cycles)
30h
Data output
05h
Address (2 cycles)
E0h
Data output
PAGE READ CACHE MODE Operations Micron NAND Flash devices have a cache register that can be used to increase the READ operation speed. Data can be output from the device's cache register while a page is concurrently moved from the NAND Flash array to the data register. To begin a PAGE READ CACHE MODE command sequence, issue the PAGE READ (00h30h) command to read a page from the NAND Flash array to the cache register. R/B# goes LOW during tR (status register bits 6 and 5 = 00). After tR (R/B# is HIGH and status register bits 6 and 5 = 11), issue either: the PAGE READ CACHE MODE SEQUENTIAL (31h) command to begin copying the next sequential page from the NAND Flash array to the data register, or the PAGE READ CACHE MODE RANDOM (00h-31h) command to begin copying the page specified in this command from the NAND Flash array to the data register. After the PAGE READ CACHE MODE SEQUENTIAL or PAGE READ CACHE MODE RANDOM command has been issued, R/B# goes LOW (status register bits 6 and 5 = 00) for tDCBSYR1 while the device begins to copy the next page into the data register. After tDCBSYR1, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is available. At this point, data can be output from the cache register by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device. After the desired number of bytes are output from the cache register, it is possible to either begin an additional PAGE READ CACHE MODE (31h or 00h-31h) operation or issue the PAGE READ CACHE MODE LAST (3Fh) command. If an additional PAGE READ CACHE MODE (31h or 00h-31h) operation is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for tDCBSYR2 while the data register is copied to the cache register and the device begins to copy the next page into the data regisNDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fm - Rev. 1.5 4/08 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
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Preliminary

ter. After tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is available. At this point, data can be output from the cache register by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device. If the PAGE READ CACHE MODE LAST (3Fh) command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for tDCBSYR2 while the data register is copied into the cache register. After tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 11, indicating that the cache register is available and the NAND Flash array is ready for another command. At this point, data can be output from the cache register by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device. During busy times (tDCBSYR1 and tDCBSYR2), the only valid commands are READ STATUS (70h and 78h) and RESET (FFh). Until status register bit 5 = 1, the only valid commands during PAGE READ CACHE MODE operations are READ STATUS (70h and 78h), PAGE READ CACHE MODE (31h and 00h-31h), RANDOM DATA READ (05h-E0h), and RESET (FFh). PAGE READ CACHE MODE SEQUENTIAL 31h The PAGE READ CACHE MODE SEQUENTIAL (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. To issue this command, write 31h to the command register. When this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for either tDCBSYR1 or tDCBSYR2. After tDCBSYR1 or tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is available. At this point, data can be output from the cache register by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device. PAGE READ CACHE MODE RANDOM 00h-31h The PAGE READ CACHE MODE RANDOM (00h-31h) command reads the specified page into the data register while the previous page is output from the cache register. To issue this command, write 00h to the command register. Then write 5 address cycles to the address register. Conclude the sequence by writing 31h to the command register. The column address in the address specified is ignored. When this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for either tDCBSYR1 or tDCBSYR2. After tDCBSYR1 or tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 10, indicating that the cache register is available. At this point, data can be output from the cache register by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device. PAGE READ CACHE MODE LAST 3Fh The PAGE READ CACHE MODE LAST (3Fh) command copies a page from the data register to the cache register without beginning a new cache read. To issue this command, write 3Fh to the command register. When this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for tDCBSYR2. After tDCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 11, indicating that the cache register is available and the NAND Flash array is ready for another
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command. At this point, data can be output from the cache register by toggling RE# beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output by the device.
Figure 18:
CLE
PAGE READ CACHE MODE Operations
CE# WE#
ALE
tR tDCBSYR1
R/B# RE# I/Ox

00h Address (5 cycles) 30h 31h PAGE READ CACHE MODE SEQUENTIAL operation Data output
Repeat as many times as necessary
CLE CE# WE# ALE

tDCBSYR2 tDCBSYR2
R/B# RE# I/Ox 1

00h Address (5 cycles) 31h Data output 3Fh Data output
PAGE READ CACHE MODE RANDOM operation

Repeat as many times as necessary
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Preliminary

READ ID 90h The READ ID command is used to read the 5 bytes of identifier code programmed into the NAND Flash devices. The READ ID command reads a 5-byte table that includes manufacturer ID, device configuration, and part-specific information (see Table 10 on page 30). Writing 90h to the command register puts the device into the read ID mode. The command register stays in this mode until the next command cycle is issued (see Figure 19).
Figure 19:
CLE
READ ID Operation
CE#
WE# tAR ALE
RE# tWHR I/Ox 90h 00h (or 20h) Address, 1 cycle tREA Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Note:
See Table 10 on page 30 for byte definitions.
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Preliminary

Table 10: Device ID and Configuration Codes for Address 00h
Options Manufacturer ID Micron Device ID 4Gb, x8, 1.8V 4Gb, x16, 1.8V 4Gb, x8, 3.3V 4Gb, x8, 3.3V 4Gb, x16, 3.3V 1 SLC 2 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2Ch ACh BCh DCh DCh CCH 00b 00b 01b I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value1
Address = 00h Byte 0 Byte 1 MT29F4G08ABC MT29F4G16ABC MT29F4G08AAC MT29F4G08EAACC3 MT29F4G16AAC Byte 2 Number of die per CE Cell type Number of simultaneously programmed pages Interleaved operations between multiple die Cache programming Byte value Byte 3 Page size Spare area size (bytes) Block size (w/o spare) Organization Serial access (MIN) Byte value 1.8V 3.3V
Supported MT29F4GxxAAC 2KB 64B 128KB x8 x16 35ns 25ns MT29F4G08ABC MT29F4G16ABC MT29F4G08AAC MT29F4G08EAAC3 MT29F4G16AAC
1 1
0 0
0 1
1b 90h 01b 1b 01b 0b 0xxx0b 1xxx0b 15h 55h 95h 95h D5h 00b 01b 101b 0b 54h
1 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1
0 1 0 0 1
0 0 0 0 0
1 1 1 1 1
1 1 1 1 1
0 0 0 0 0 0
1 1 1 1 1 0
Byte 4 Reserved Planes per CE# Plane size Reserved Byte value 2 2Gb MT29F4GxxAAC 0 0 0 1 1 0 0 1 1 0 1 0 0 1
Notes: 1. b = binary; h = hex.
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Not supported
0b
Preliminary

Table 11: Device ID and Configuration Codes for Address 20h
Options O N F I Undefined Notes: 1. h = hex. I/O7 0 0 0 0 X I/O6 1 1 1 1 X I/O5 0 0 0 0 X I/O4 0 0 0 0 X I/O3 1 1 0 1 X I/O2 1 1 1 0 X I/O1 1 1 1 0 X I/O0 1 0 0 1 X Value1 Notes 4Fh 4Eh 46h 49h XXh
Address = 20h Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
READ UNIQUE ID (EDh) Micron offers the UNIQUE ID command feature to provide a method for uniquely identifying a NAND Flash device. The UNIQUE ID operation uses standard command and address timing. The format of the ID is arbitrary; however, this ID is guaranteed to be unique for every NAND Flash device manufactured. Many controllers use proprietary error correction code (ECC) schemes; thus, it is not possible for Micron to protect unique ID data with factory-programmed ECC. However, to ensure data integrity, Micron programs the noted NAND Flash devices with a 16-byte unique ID, beginning at byte 0 of the page, then follows with 16 bytes of complement ID. These 32 bytes of data are then repeated a total of 16 times, such that the last byte of the last copy of complement unique ID resides at byte 511 in the page. The user can simply XOR the first copy of the unique ID and its complement. If the result is 0, the unique ID is good. In the unlikely event that the result is non-zero, the user can repeat the XOR operation on a subsequent copy of the unique ID data. Figure 20 shows timing for the device.
Figure 20:
READ UNIQUE ID Operation

CLE WE# ALE RE#
I/O[7:0] R/B#
EDh
00h
Byte 0
Byte 1
UNIQUE ID data
Byte 14
Byte 15
tR
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READ PARAMETER PAGE ECh The READ PARAMETER PAGE function retrieves the data structure that describes the device's organization, features, timings, and other behavioral parameters. The data structure is repeated at least five times. Figure 21 defines the READ PARAMETER PAGE behavior. The RANDOM DATA READ (05h-E0h) command is permitted during data output.
Figure 21:
READ PARAMETER PAGE Operation

CLE WE# ALE RE#
I/O[7:0] R/B#
ECh
00h
tR
P0
P1
P1022
P1023
Table 12:
Byte 03 4-5 6-7
ONFI Parameters
Description Parameter page signature Revision number Features Supported Value
MT29F4G08AAC MT29F4G08ABC MT29F4G16AAC MT29F4G16ABC
89 1031 3243 4463
Optional commands supported Reserved Device manufacturer Device model
MT29F4G08AAC MT29F4G08ABC MT29F4G16AAC MT29F4G16ABC
64 6566 6779 8083 8485 8689
Manufacturer ID Date code Reserved Number of data bytes per page Number of spare bytes per page Number of data bytes per partial page
4F, 4E, 46, 49 02, 00 18, 00 18, 00 19, 00 19, 00 3F, 00 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 4D, 49, 43, 52, 4F, 4E, 20, 20, 20, 20, 20, 20 4D, 54, 32, 39, 46, 34, 47, 30, 38, 41, 41, 43, 20, 20, 20, 20, 20, 20, 20, 20 4D, 54, 32, 39, 46, 34, 47, 30, 38, 41, 42, 43, 20, 20, 20, 20, 20, 20, 20, 20 4D, 54, 32, 39, 46, 34, 47, 31, 36, 41, 41, 43, 20, 20, 20, 20, 20, 20, 20, 20 4D, 54, 32, 39, 46, 34, 47, 31, 36, 41, 42, 43, 20, 20, 20, 20, 20, 20, 20, 20 2C 00,00 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 00, 08, 00, 00 40, 00 00, 02, 00, 00
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Table 12:
Byte 9091 9295 9699 100 101 102 103104 105106 107 108109 110 111 112 113 114 115127 128 129130
ONFI Parameters (continued)

Description Number of spare bytes per partial page Number of pages per block Number of blocks per unit Number of units Number of address cycles Number of bits per cell Bad blocks maximum per unit Block endurance Guaranteed valid blocks at beginning of target Block endurance for guaranteed valid blocks Number of programs per page Partial programming attributes Number of bits ECC bits Number of interleaved address bits Interleaved operation attributes Reserved I/O pin capacitance Timing mode support MT29F4G08AAC MT29F4G08ABC MT29F4G16AAC MT29F4G16ABC Program cache timing mode MT29F4G08AAC support MT29F4G08ABC MT29F4G16AAC MT29F4G16ABC tPROG Maximum page MT29F4G08AAC program time MT29F4G08ABC MT29F4G16AAC MT29F4G16ABC tBERS Maximum block erase time tR Maximum page read time tCCS Minimum change MT29F4G08AAC column set up time. MT29F4G08ABC (same as tWHR) MT29F4G16AAC MT29F4G16ABC Reserved Vendor-specific revision number Vendor specific Value 10, 00 40, 00, 00, 00 00, 10, 00, 00 01 23 01 50, 00 0A, 04 01 00, 00 04 00 01 01 0E 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 0A 1F, 00 07, 00 1F, 00 07, 00 1F, 00 07, 00 1F, 00 07, 00 58, 02 BC, 02 58, 02 BC, 02 B8, 0B 19, 00 46, 02 64, 02 46, 02 64, 02 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 01, 00 01, 02, 02, 02, 04, 80, 01, 81, 04, 01, 02, 01, 0A, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 Set at test
131132
133134
135136 137138 139140
141163 164165 166253
254255 256511 512767
Integrity CRC Value of bytes 0255 Value of bytes 0255
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Preliminary

Table 12:
Byte 768+
ONFI Parameters (continued)

Description Additional redundant parameter pages Value
READ STATUS 70h These NAND Flash devices have an 8-bit status register the software can read during device operation. On the x16 device, I/O[15:8] are 0 when the status register is being read. Table 13 on page 34 describes the status register. After a READ STATUS command, all READ cycles will be from the status register until a new command is issued. Changes in the status register will be seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to start a new READ STATUS cycle to see these changes. While monitoring the status register to determine when the tR (transfer from NAND Flash array to data register) is complete, the user must re-issue the READ (00h) command to make the change from status to read mode. After the READ command has been re-issued, pulsing the RE# line will result in outputting data, starting from the initial column address. Table 13:
SR Bit 0
1
Status Register Bit Definition

Program Page Pass/fail Program Page Cache Mode Pass/fail (N) Pass/fail (N-1) Ready/busy2 Ready/busy cache3 Write protect Page Read Ready/busy Ready/busy Page Read Cache Mode Ready/busy2 Block Erase Pass/fail Definition
1 2 3 4 5 6 7
Ready/busy Ready/busy Write protect
Ready/busy cache3 Write protect Write protect
0 = Successful PROGRAM/ERASE 1 = Error in PROGRAM/ERASE 0 = Successful PROGRAM 1 = Error in PROGRAM 0 0 0 Ready/busy 0 = Busy 1 = Ready Ready/busy 0 = Busy 1 = Ready Write protect 0 = Protected 1 = Not protected
Notes: 1. Status register bit 0 reports a 1 if a TWO-PLANE PROGRAM PAGE or TWO-PLANE BLOCK ERASE operation fails on one or both planes. Status register bit 1 reports a 1 if a TWOPLANE PROGRAM PAGE CACHE MODE operation fails on one or both planes. Use TWOPLANE/MULTIPLE-DIE READ STATUS (78h) to determine the plane to which the operation failed. 2. Status register bit 5 is 0 during the actual programming operation. If cache mode is used, this bit will be 1 when all internal operations are complete. 3. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6. See Figure 25 on page 38 and Figure 90 on page 98.
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Figure 22: Status Register Operation
CE# tCLR CLE WE# tREA RE# I/Ox 70h Status output
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4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions PROGRAM Operations
PROGRAM PAGE 80h-10h Micron NAND Flash devices are inherently page-programmed devices. Pages must be programmed consecutively within a block, from the least significant page address to most significant page address (i.e., 0, 1, 2, , 63). Random page address programming is prohibited. Micron NAND Flash devices also support partial-page programming operations. This means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of four programming operations are supported before an erase is required. SERIAL DATA INPUT 80h PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command into the command register, followed by 5 ADDRESS cycles, then the data. Serial data is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h) command is written after the data input is complete. The control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects 1s that are not successfully written to 0s. R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS (70h) command and the RESET (FFh) command are the only commands valid during the programming operation. Bit 6 of the status register will reflect the state of R/B#. When the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see Figure 23). The command register stays in read status register mode until another valid command is written to it. RANDOM DATA INPUT 85h After the initial data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuing the PAGE WRITE (10h) command. See Figure 24 for the proper command sequence.
Figure 23:
PROGRAM and READ STATUS Operation

tPROG R/B# I/Ox 80h Address (5 cycles) DIN 10h 70h Status
(or 78h) I/O 0 = 0 PROGRAM successful I/O 0 = 1 PROGRAM error
Figure 24:
RANDOM DATA INPUT

tPROG R/B# I/Ox 80h Address (5 cycles) DIN 85h Address (2 cycles) DIN 10h 70h (or 78h) Status
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PROGRAM PAGE CACHE MODE 80h-15h Cache programming is actually a buffered programming mode of the standard PROGRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT (80h) command to the command register, followed by 5 cycles of address, and a full or partial page of data. The data is initially copied into the cache register, and the CACHE PROGRAM (15h) command is then latched to the command register. Data is transferred from the cache register to the data register on the rising edge of WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data register and R/B# returns to HIGH, memory array programming begins. When R/B# returns to HIGH, new data can be written to the cache register by issuing another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be controlled by the actual programming time. The first time through equals the time it takes to transfer the cache register contents to the data register. On the second and subsequent programming passes, transfer from the cache register to the data register is held off until current data register content has been programmed into the array. The PROGRAM PAGE CACHE MODE command can cross block address boundaries. RANDOM DATA INPUT (85h) commands are permitted with PROGRAM PAGE CACHE MODE operations.
Bit 5 (R/B#) of the status register can be polled to determine when the actual programming of the array is complete for the current programming cycle. If just the R/B# pin is used to determine programming completion, the last page of the program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete (see Figure 25 on page 38). Bit 1 of the status register returns the pass/fail for the previous page when bit 6 of the status register is a 1 (ready state). The pass/fail status of the current PROGRAM operation is returned with bit 0 of the status register when bit 5 of the status register is a 1 (ready state) as shown in Figure 25.
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Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h) command to determine when the cache register is ready to accept new data. The R/B# pin always follows bit 6.
Preliminary

Figure 25: PROGRAM PAGE CACHE MODE Example
tCBSY
tCBSY tCBSY tLPROG1
R/B#
80h Address & data input 15h 80h Address & data input 15h 80h Address & data input 15h 80h Address & data input 10h
I/Ox
A: Without status reads
tCBSY
tLPROG1
R/B# I/Ox
80h Address & data input 15h 70h Status output2 80h Address & data input 10h 70h Status output2
B: With status reads
Notes: 1. See Table 33 on page 85, Note 4. 2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass/fail status. RE# can stay LOW or pulse multiple times after a 70h command.
An internal data move requires two command sequences. Issue a READ for INTERNAL DATA MOVE (00h-35h) command first, then the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. Data moves are only supported within the plane from which data is read. Moving data from odd to even blocks or from even to odd blocks is prohibited. READ FOR INTERNAL DATA MOVE 00h-35h The READ for INTERNAL DATA MOVE (00h-35h) command is used in conjunction with the PROGRAM for INTERNAL DATA MOVE (85h-10h) command. First, 00h is written to the command register, then the internal source address is written (5 cycles). After the address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the command register. This transfers a page from memory into the cache register. All 5 ADDRESS cycles are required when a READ for INTERNAL DATA MOVE command is issued. After a READ for INTERNAL DATA MOVE (00h-35h) command is issued and R/B# returns HIGH, signifying operation completion, the data transferred from the source page into the cache register may be read out by toggling RE#. Data is output sequentially from the column address originally specified with the READ FOR INTERNAL DATA MOVE (00h-35h) command. RANDOM DATA READ (05h-E0h) commands can be issued without limit after the READ FOR INTERNAL DATA MOVE command. The memory device is now ready to accept the PROGRAM for INTERNAL DATA MOVE command. Please refer to the description of this command in the following section.
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Internal Data Move
PROGRAM for INTERNAL DATA MOVE 85h-10h After the READ for INTERNAL DATA MOVE (00h-35h) command has been issued and R/B# goes HIGH, the PROGRAM for INTERNAL DATA MOVE (85h-10h) command can be written to the command register. This command transfers the data from the cache register to the data register and programming of the new destination page begins. The sequence: 85h, destination address (5 cycles), then 10h, is written to the device. After 10h is written, R/B# goes LOW while the control logic automatically programs the new page. The READ STATUS command can be used instead of the R/B# line to determine when the write is complete. When status register bit 6 = 1, bit 0 of the status register indicates if the operation was successful. The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for INTERNAL DATA MOVE command sequence to modify one or more bytes of the original data. First, data is copied into the cache register using the 00h-35h command sequence, then the RANDOM DATA INPUT (85h) command is written along with the address of the data to be modified next. New data is input on the external data pins. This copies the new data into the cache register. When 10h is written to the command register, the original data plus the modified data are transferred to the data register, and programming of the new page is started. The RANDOM DATA INPUT command can be issued as many times as necessary before starting the programming sequence with 10h (see Figures 26 and 27 on page 40). Because INTERNAL DATA MOVE operations do not use external memory, ECC cannot be used to check for errors before programming the data to a new page. This can lead to a data error if the source page contains a bit error due to charge loss or charge gain. In the case that multiple INTERNAL DATA MOVE operations are performed, these bit errors may accumulate without correction. For this reason, it is highly recommended that systems using INTERNAL DATA MOVE operations also use a robust ECC scheme that can correct 2 or more bits per sector.
NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fmRev. 1.5 4/08 EN
39
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Preliminary

Figure 26: INTERNAL DATA MOVE
tR tPROG
Address (5 cycles)
35h
Data output
05h
Address (2 cycles)
E0h
Data output
85h
Address (5 cycles)
10h
70 (or
Unlimited number of repetitions
Optional
Figure 27:
INTERNAL DATA MOVE with Optional RANDOM DATA OUTPUT and RANDOM DATA INPUT
tR tPROG
Address (5 cycles)
35h
Data output
85h
Address (2 cycles)
Data
10h
70h (or 78h)
Unlimited number of repetitions Optional
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4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions BLOCK ERASE Operation
BLOCK ERASE 60h-D0h Erasing occurs at the block level. For example, the MT29F4G device and MT29F8G device have 4,096 and 8192 blocks respectively. They are organized into 64 pages per block, 2,112 bytes per page (2,048 + 64 bytes). Each block is 132K bytes (128K + 4K bytes). The BLOCK ERASE command operates on one block at a time (see Figure 28). Three cycles of addresses BA[18:6] and PA[5:0] are required. Although page addresses PA[5:0] are loaded, they are a Dont Care and are ignored for BLOCK ERASE operations. See Table 4 on page 16 and Table 5 on page 17 for addressing details. The actual command sequence is a two-step process. The ERASE SETUP (60h) command is first written to the command register. Then 3 cycles of addresses are written to the device. Next, the ERASE CONFIRM (D0h) command is written to the command register. At the rising edge of WE#, R/B# goes LOW and the control logic automatically controls the timing and erase-verify operations. R/B# stays LOW for the entire tBERS erase time. The READ STATUS (70h) command can be used to check the status of the BLOCK ERASE operation. When bit 6 = 1, the ERASE operation is complete. Bit 0 indicates a pass/fail condition where 0 = pass (see Figure 28 and Table 13 on page 34).
Figure 28:
CLE
BLOCK ERASE Operation
CE#
WE#
ALE tBERS R/B#
RE#
I/Ox
60h
Address input (3 cycles)
D0h
70h
Status
I/O 0 = 0 ERASE successful I/O 0 = 1 ERASE error
Dont Care
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions Block Lock Feature (1.8V only)
The block lock feature of this NAND Flash device provides the ability to protect the entire device or ranges of blocks from PROGRAM and ERASE operations. Using this block lock feature offers increased functionality and flexibility over using just the WP# pin to prevent PROGRAM and ERASE operations. Block lock features are enabled and disabled at power-on through the use of the LOCK pin. At power-on, if LOCK is LOW, all block lock commands are disabled. However, at power-on, if LOCK is HIGH, the block lock commands are enabled and, by default, all of the blocks on the device are protected, or locked, from PROGRAM and ERASE operations, even if WP# is HIGH. Before the contents of the device can be modified, the device must first be unlocked. Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE operations complete successfully only in the block ranges that have been unlocked. Blocks, once unlocked, can be locked again to protect them from further PROGRAM and ERASE operations. Blocks that are locked can be protected further, or locked tight. When locked tight, the devices blocks can no longer be locked or unlocked until WP# is pulled LOW for more than 100ns. After WP# goes LOW for this period, the entire device is locked from PROGRAM and ERASE operations until unlocked again. WP# and Block Lock When the block lock feature is enabled, it interacts with WP# as follows: The WP# pin must be driven HIGH and remain HIGH when UNLOCK and LOCKTIGHT commands are issued. Holding WP# LOW locks all blocks. If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command must be issued to unlock blocks. UNLOCK 23h-24h By default at power-on if LOCK is HIGH, all of the blocks in the NAND Flash device are locked, meaning that they are protected from PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no protection and can be programmed or erased. The UNLOCK command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. When the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. When the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the upper boundary block address. Figures 29 and 30 on page 43 show examples of how the lower and upper boundary address registers work with the invert area bit. To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate ADDRESS cycles that indicate the lower boundary block address. Then issue the 24h command followed by the appropriate ADDRESS cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to 1 if setting the invert area bit; otherwise, it should be 0. The other page address bits should be 0 (see Figure 31 on page 44). Only one range of blocks can be specified in the lower and upper boundary block address registers. If after unlocking a range of blocks the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous unlocked block address range is not retained.
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Preliminary

Figure 29: Flash Array Protected: Inverted Area Bit = 0
Protected area
Block 4095 Block 4094 Block 4093 Block 4092 Block 4091 Block 4090 Block 4089 Block 4088 Block. 4087 . . . . . . . . . . . . . Block 0002 Block 0001 Block 0000
FFCh
Upper block boundary
Unprotected area
FF8h
Lower block boundary Protected area
Figure 30:
Flash Array Protected: Invert Area Bit = 1

Unprotected Area
Block 4095 Block 4094 Block 4093 Block 4092 Block 4091 Block 4090 Block 4089 Block 4088 Block. 4087 . . . . . . . . . . . . . Block 0002 Block 0001 Block 0000
FFCh
Upper block boundary
Protected area
FF8h
Lower block boundary
Unprotected area
Notes: 1. I/O[15:8] is applicable only for x16 devices. 2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.
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Preliminary

Table 14:
ALE Cycle First Second Third
Block Lock Address Cycle Assignments

I/O[15:8]1 LOW LOW LOW I/O7 BA7 BA15 LOW I/O6 BA6 BA14 LOW I/O5 LOW BA13 LOW I/O4 LOW BA12 LOW I/O3 LOW BA11 LOW I/O2 LOW BA10 LOW I/O1 LOW BA9 BA17 I/O0 Invert area bit2 BA8 BA16
Notes: 1. I/O[15:8] is applicable only for x16 devices. 2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.
Figure 31:
UNLOCK Operation
WP#
CLE
CE#
WE#
ALE
RE#
Block add 1 Block add 2 Block add 3 Block add 1 Block add 2 Block add 3
I/Ox
23h Unlock
24h
Lower boundary
Upper boundary
R/B#
LOCK 2Ah By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are locked, meaning that they are protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The LOCK command locks all of the blocks in the device. Locked blocks are write-protected from PROGRAM and ERASE operations. To lock all of the blocks in the device, issue the LOCK (2Ah) command.
t
When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for LBSY. The PROGRAM or ERASE operation does not complete. Any READ STATUS command reports bit 7 as 0, indicating that the block is protected. The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is locked tight (see LOCK-TIGHT 2Ch on page 45).
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Preliminary

Figure 32: LOCK Operation
CLE
CE#
WE#
I/Ox
2Ah LOCK command
LOCK-TIGHT 2Ch The LOCK-TIGHT (2Ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level of protection against inadvertent PROGRAM and ERASE operations to locked blocks. To implement lock-tight in all of the locked blocks in the device, verify that WP# is HIGH and then issue the LOCK-TIGHT (2Ch) command. When a PROGRAM or ERASE operation is issued to a locked block that has also been locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as 0, indicating that the block is protected. PROGRAM and ERASE operations complete successfully to blocks that were not locked at the time the LOCK-TIGHT command was issued. After the LOCK-TIGHT command is issued, the command cannot be disabled via a software command. The only ways to disable the lock-tight status are to hold WP# LOW for longer than 100ns, or power cycle the device. When the lock-tight status is disabled, all of the blocks become locked, the same as if the LOCK (2Ah) command had been issued. The LOCK-TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.
Figure 33:
LOCK-TIGHT Operation
LOCK WP# CLE CE# WE# I/Ox 2Ch LOCK-TIGHT command R/B#
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Preliminary

Figure 34: PROGRAM/ERASE Issued to Locked Block
tLBSY R/B#
I/Ox
PROGRAM or ERASE
Address/data input Locked block
CONFIRM
70h READ STATUS
60h
Figure 35:
LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation

LOCK
CE#
WP#
BLOCK LOCK READ STATUS 7Ah The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The ADDRESS cycles have the same format as shown in Table 14 on page 44; the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output the block lock status register which contains the information on the protection status of the block. Table 15 shows how to interpret the block lock status register bits. Table 15: Block Lock Status Register Bit Definitions
I/O[7:3] X X X X I/O2 (Lock#) 0 0 1 1 I/O1 (LT#) 0 1 0 1 I/O0 (LT) 1 0 1 0
Block Lock Status Register Definitions Block is locked-tight Block is locked Block is unlocked, and device is locked-tight Block is unlocked, and device is not locked-tight
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> 100ns
Preliminary

Figure 36: BLOCK LOCK READ STATUS
CLE
CE#
WE# tWHR ALE
RE#
I/Ox
7Ah
BLOCK LOCK READ STATUS
Add 1
Add 2
Add 3
Status
Block address
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Preliminary

Figure 37: BLOCK LOCK Flow Chart
Power-up
Power-up with LOCK HIGH Power-up with LOCK LOW (default) BLOCK LOCK function disabled
Entire NAND Flash array locked

LOCK-TIGHT Cmd with WP# and LOCK HIGH
Entire NAND Flash array locked tight

WP# LOW >100ns
UNLOCK Cmd with invert area bit = 0
Unlocked range
LOCK Cmd
Locked range
LOCK Cmd UNLOCK Cmd with invert area bit = 1
Locked range Unlocked range
Unlocked range Locked range
Unlocked range Locked-tight range Unlocked range
Locked-tight range Unlocked range Locked-tight range
WP# LOW > 100ns
WP# LOW > 100ns
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions One-Time Programmable (OTP) Area
This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Ten full pages (2,112 bytes per page) of OTP data is available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. In Micron NAND Flash devices, the OTP area leaves the factory in a non-written state (all bits are 1). Programming or partial-page programming enables the user to program only 0 bits in the OTP area. The OTP area cannot be erased, even if it is not protected. Protecting the OTP area simply prevents further programming of the OTP area. While the OTP area is referred to as one-time programmable, Micron provides a unique way to program and verify databefore permanently protecting it and preventing future changes. OTP programming and protection are accomplished in two discrete operations. First, using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed entirely in one operation, or in up to four partial-page programming sequences. Programming can occur on other pages within the OTP area in a similar manner. Second, the OTP area is permanently protected from further programming using the OTP DATA PROTECT (A5h-10h) command. The pages within the OTP area can always be read using the OTP DATA READ (AFh-30h) command, whether or not it is protected. To determine whether or not the device is busy during an OTP operation, either monitor R/B# or use the READ STATUS (70h) command. Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited during and following OTP operations. OTP DATA PROGRAM A0h-10h The OTP DATA PROGRAM (A0h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time, or a page can be partially programmed up to four times. There is no ERASE operation for the OTP pages. The OTP DATA PROGRAM command allows programming into an offset of an OTP page, using the 2 bytes of column address (CA[11:0] for x8 devices, and CA[10:0] for x16 devices). The OTP DATA PROGRAM command will not execute if the OTP area has been protected. If the OTP area is protected, the busy time for the OTP DATA PROGRAM operation is tOBSY and not tPROG. To use the OTP DATA PROGRAM command, issue the A0h command. Issue 5 ADDRESS cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Next, write from 1 to 2,112 bytes of data. After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. Program verification only detects 1s that are not successfully written to 0s. R/B# goes LOW during the duration of the array programming time (tPROG). The READ STATUS (70h) command is the only command valid during the OTP DATA PROGRAM operation. Bit 5 of the status register will reflect the state of R/B#. If bit 7 is 0, then the OTP area has been protected; otherwise, it will be a 1. When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 13 on page 34). It is possible to program each OTP page a maximum of four times.
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RANDOM DATA INPUT 85h After the initial OTP data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuance of the OTP PAGE WRITE (10h) command. See Figure 39 on page 51 for the proper command sequence. Figure 38: OTP DATA PROGRAM
CLE
CE#
tWC
WE#
tWB
tPROG
ALE
RE#
50
I/Ox
A0h
OTP DATA INPUT command
Col Col add 1 add 2
OTP page1
00h
00h
DIN N
DIN M
10h
PROGRAM command
70h1
READ STATUS command
Status
1 up to m bytes serial input
R/B#
x8 device: m = 2,112 bytes OTP data written (following "good" status confirmation)
Dont Care
Notes: 1. The OTP page must be within the 02h0Bh range.
Preliminary
Draft 4/ 20/ 2008
Preliminary

Figure 39: OTP PROGRAM with RANDOM DATA INPUT
WC
tWB
tPROG
Col add 1 NPUT d
Col add 2
OTP page1
00h
00h
DIN DIN N M 1 up to m bytes serial input
Col Col add 2 add 1 RANDOM New column address DATA in selected OTP page INPUT command 85h
DIN P
DIN Q
10h PROGRAM command
7 READ com
x8 device: m = 2,158 bytes x16 device: m = 1,079 bytes
OTP da (fol "good" stat
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Preliminary

OTP DATA PROTECT A5h-10h The OTP DATA PROTECT (A5h-10h) command is used to protect all the data in the OTP area. After the data is protected it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected. To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the following 5 ADDRESS cycles: 00h-00h-01h-00h-00h. Finally, issue the 10h command. R/B# goes LOW while the OTP area is being protected. The protect command duration is similar to a normal page programming operation, tPROG. The READ STATUS (70h) command is the only command valid during the OTP DATA PROTECT operation. Bit 5 of the status register will reflect the state of R/B#. When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 13 on page 34). Figure 40:
CLE
OTP DATA PROTECT
tWC WE# tWB ALE tPROG
RE#
I/Ox
A5h OTP DATA PROTECT command
Col 00h
Col 00h
01h
00h
00h
10h PROGRAM command
70h READ STATUS command
Status
R/B# OTP data protected1
Dont Care
Notes: 1. OTP data is protected following good status confirmation.
OTP DATA READ AFh-30h The OTP DATA READ (AFh-30h) command is used to read data from a page within the OTP area. An OTP page within the OTP area is available for reading data whether or not the area is protected. To use the OTP DATA READ command, issue the AFh command. Next, issue 5 ADDRESS cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0Bh-00h-00h. Finally, issue the 30h command.
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CE#
R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command and the RESET (FFh) command are the only commands valid during the OTP DATA READ operation. Bit 5 of the status register will reflect the state of R/B#. For details, refer to Table 13 on page 34. Normal READ operation timings apply to OTP read accesses (see Figure 41). Additional pages within the OTP area can be selected by repeating the OTP DATA READ command. The RANDOM DATA READ command enables the user to specify a new column address within the OTP page so the data at single or multiple column addresses can be read. The random read mode is enabled after a normal OTP DATA READ (AFh-30h) sequence. Random data can be output after the initial page read by writing an 05h-E0h command sequence along with the new column address (2 cycles). The RANDOM DATA READ command can be issued without limit within the OTP page. Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially (see Figure 42 on page 54).
Figure 41:
OTP DATA READ Operation

CLE
CE#
53
WE#
ALE tR RE#
I/Ox
AFh
Col add 1
Col add 2
OTP page1
00h
00h
30h
DOUT N
DOUT N+1
DOUT M
Busy R/B# Dont Care
Preliminary
Notes: 1. The OTP page must be within the 02h0Bh range.
Draft 4/ 20/ 2008
Preliminary

Figure 42: OTP DATA READ with RANDOM DATA READ
tR
Busy
Notes: 1. The OTP page must be within the range 02h0Bh.
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Col add 1
Col add 2
OTP page1
00h
00h
30h
DOUT N
DOUT N+1
DOUT M
05h
Col add 1
Col add 2
E0h
DOUT P
Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions Features Operations
The GET FEATURES (EEh) and SET FEATURES (EFh) commands are used to alter the NAND Flash device behavior from the default power-on behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified. Each feature (in the range of 0 to 255) is defined in the features table (Table 16). The GET FEATURES (EEh) command (see GET FEATURES EEh on page 57) simply reads the parameter in the features table (4 bytes). The SET FEATURES (EFh) command (see SET FEATURES EFh on page 58) places parameters in the features table (4 bytes). When a feature is set, by default it remains active until the device is power cycled. It is volatile. Unless otherwise specified in the features table, once a device is set it remains set, even if a RESET (FFh) command is issued. Table 16: Features Table
Feature Address 00h 01h 02h7Fh 80h 81h 82hFFh Description Reserved Timing mode Reserved Vendor-specific parameter: Programmable I/O drive strength Vendor-specific parameter: Programmable R/B# pull-down strength Reserved
Table 17:
Feature Address 01h: Timing Mode

Subfeature Parameter Options P1 Timing mode Mode 0 (default) Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) P3 Reserved (0) P4 Reserved (0) 00h 00h 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 00h 01h 02h 03h 04h 05h 00h 1,2 2 3 3 3 4 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
P2
Notes: 1. The timing-mode feature address is used to change the default timing mode. The timing mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. The five supported settings for the timing mode are shown. The default timing mode is mode 0. The device returns to mode 0 when the device is power cycled. Supported timing modes are reported in the parameter page. 2. Supported for both 1.8V and 3.3V. 3. Supported for 3.3V only. 4. Not supported.
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Preliminary

Table 18:
Subfeature Parameter P1 I/O drive strength Full (default) Three-quarters One-half One-quarter Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) 0 0 1 1 0 1 0 1 00h 01h 02h 03h 00h 00h 00h 1
Feature Address 80h: Programmable I/O Drive Strength

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
P2 Reserved P3 Reserved P4 Reserved
Table 19:
Subfeature Parameter P1
Feature Address 81h: Programmable R/B# Pull-down Strength

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
R/B# pull-down strength
Full (default) Three-quarters One-half One-quarter
Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0)
0 0 1 1
0 1 0 1
00h 01h 02h 03h 00h 00h 00h
P2 Reserved P3 Reserved P4 Reserved
Notes: 1. The programmable R/B# pull-down strength feature address is used to change the default R/B# pull-down strength. R/B# pull-down strength should be selected based on expected loading of R/B#. The four supported pull-down strength settings are shown. The default pull-down strength is full strength. The device returns to the default pull-down strength when the device is power cycled.
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Notes: 1. The PROGRAMMABLE DRIVE STRENGTH feature address is used to change the default I/O drive strength. Drive strength should be selected based on expected loading of the memory bus. This table shows the four supported output drive-strength settings. The default drive strength is full strength. The device returns to the default drive strength mode when the device is power cycled. AC timing parameters may need to be relaxed if I/O drive strength is not set to full.
Preliminary

GET FEATURES EEh The GET FEATURES command is used to determine the current settings for the specified feature address. This command returns the parameter settings, including modifications made previously with the SET FEATURES function. Figure 43 defines GET FEATURES behavior and timing.
Figure 43:
Get Features EEh

CLE
CE#
WE#
ALE
RE#
I/Ox
EEh
FA
Feature address, 1 cycle
P11 tFEAT
P2
P3
P4
R/B#
Notes: 1. P1P4 are the parameters for the specified feature address (FA).
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Preliminary

SET FEATURES EFh The SET FEATURES command is used to set the parameters at a specified feature address. These parameters are stored in the device until power is cycled. They are applied to all die on the CE# to which this command is issued. Figure 44: Set Features EFh
CLE CE#
WE# ALE RE# I/Ox EFh FA

Feature address, 1 cycle
P11
P2
P3
P4 tFEAT
R/B#
Notes: 1. P1P4 are the parameters for the specified feature address (FA).
TWO-PLANE Operations
This NAND Flash device is divided into two physical planes. Each plane contains a 2,112-byte data register, a 2,112-byte cache register, and a 2,048-block NAND Flash array. Two-plane commands make better use of the Flash arrays on these physical planes by performing PROGRAM, READ, or ERASE operations simultaneously, significantly improving system performance. Two-Plane Addressing Two-plane commands require two addresses, one address per plane. These two addresses are subject to the following requirements: The least significant block address bit, BA6, must be different for the two addresses. The page address bits, PA[5:0], must be identical for both addresses. TWO-PLANE PAGE READ 00h-00h-30h The TWO-PLANE PAGE READ (00h-00h-30h) operation is similar to the PAGE READ (00h-30h) operation. It transfers two pages of data from the NAND Flash array to the data registers. Each page must be from a different plane on the same die. To enter the TWO-PLANE PAGE READ mode, write the 00h command to the command register, then write 5 ADDRESS cycles for plane 0 (BA6 = 0). Next, write the 00h command to the command register, then write 5 ADDRESS cycles for plane 1 (BA6 = 1). Finally, issue the 30h command. The first-plane and second-plane addresses must meet the two-plane addressing requirements, and, in addition, they must have identical column addresses.
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After the 30h command is written, page data is transferred from both planes to their respective data registers in tR. During these transfers, R/B# goes LOW. When the transfers are complete, R/B# goes HIGH. To read out the data from the plane 0 data register, pulse RE# repeatedly. After the data cycle from the plane 0 address completes, issue a TWO-PLANE RANDOM DATA READ (06h-E0h) command to select the plane 1 address, then repeatedly pulse RE# to read out the data from the plane 1 data register. Alternatively, the READ STATUS (70h) command can monitor data transfers. When the transfers are complete, status register bit 6 is set to 1. To read data from the first of the two planes, the user must first issue the TWO-PLANE RANDOM DATA READ (06h-E0h) command (see TWO-PLANE RANDOM DATA READ 06h-E0h) and pulse RE# repeatedly. When the data cycle is complete, issue a TWO-PLANE RANDOM DATA READ (06h-E0h) command to select the other plane. To output the data beginning at the specified column address, pulse RE# repeatedly. Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited during and following a TWOPLANE PAGE READ operation. TWO-PLANE RANDOM DATA READ 06h-E0h The TWO-PLANE RANDOM DATA READ (06h-E0h) command is similar to the RANDOM DATA READ (05h-E0h) command, except that it requires 5 ADDRESS cycles rather than 2. The command selects a plane and a column address from which to read data after a TWO-PLANE PAGE READ (00h-00h-30h) command. To issue a TWO-PLANE RANDOM DATA READ command, issue the 06h command, then 5 ADDRESS cycles, and follow with the E0h command. Pulse RE# repeatedly to read data from the new plane, beginning at the specified column address. The primary purpose of the TWO-PLANE RANDOM DATA READ command is to select a new plane and a column address within that plane. If a new plane does not need to be selected, then it is possible to use the RANDOM DATA READ (05h-E0h) command instead (see RANDOM DATA READ 05h-E0h on page 26).
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Figure 45:
CLE
TWO-PLANE PAGE READ
WE#
ALE
RE#
Page address M Page address M Row add 3
I/Ox
00h
Col add 1
Col add 2
Row add 1
Row add 2
00h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
30h
Column address J R/B#
Plane 0 address
Column address J
Plane 1 address
tR
1
CLE
60
WE#
ALE
RE#
I/Ox
DOUT 0
DOUT 1 Plane 0 data
DOUT
06h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
E0h
DOUT 0
DOUT 1 Plane 1 data
DOUT
Plane 1 address
R/B#
1
Notes: 1. Column and page addresses must be the same. 2. The least significant block address bit, BA6, must not be the same for the first- and second-plane addresses.
Preliminary
Draft 4/ 20/ 2008
Preliminary

Figure 46: TWO-PLANE PAGE READ with RANDOM DATA READ
tR
00h
Address (5 cycles) Plane 0 address
00h
30h
Data output Plane 0 data
05h
Address (2 cycles)
E0h
06h
E0h
05h
Address (2 cycles)
E0h
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Preliminary

TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h The TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h) operation is similar to the PROGRAM PAGE (80h-10h) operation. It programs two pages of data from the data registers to the Flash arrays. The pages must be programmed to different planes on the same die. Within a block, the pages must be programmed consecutively from the least significant to most significant page address. Random page programming within a block is prohibited. The first-plane address and the second-plane address must meet the two-plane addressing requirements (see Two-Plane Addressing on page 58). To begin the TWO-PLANE PROGRAM PAGE operation, write the 80h command to the command register; write 5 ADDRESS cycles for the first plane; then write the data. Serial data is loaded on consecutive WE# cycles starting at the given address. Next, write the 11h command. The 11h command is a dummy command that informs the control logic that the first set of data for the first plane is complete. No programming of the NAND Flash array occurs. R/B# goes LOW for tDBSY, then returns HIGH. The READ STATUS (70h) command also indicates that the device is ready when status register bit 6 is set to 1. The only valid commands during tDBSY are READ STATUS (70h) and RESET (FFh). After tDBSY, write the 80h command to the command register; write 5 ADDRESS cycles for the second plane; then write the data. The PROGRAM (10h) command is written after the second-plane data input is complete. After the 10h command is written, the control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operations to both planes. WRITE verification only detects 1s that are not successfully written to 0s. R/B# goes LOW for the duration of the array programming time (tPROG). When programming and verification are complete, R/B# returns HIGH. The READ STATUS (70h) command also indicates that the device is ready when status register bit 6 is set to 1. The only valid commands during tPROG are READ STATUS (70h), TWO-PLANE/ MULTIPLE-DIE READ STATUS (78h), and RESET (FFh). When the device is ready, if the READ STATUS (70h) command indicates an error in the operation (status register bit 0 = 1), use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twiceonce for each planeto determine which plane operation failed. During serial data input for either plane, the RANDOM DATA INPUT (85h) command can be used any number of times to change the column address within that plane. For details on this command, see RANDOM DATA INPUT 85h on page 36. Figure 47 shows TWO-PLANE PROGRAM PAGE operation.
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Figure 47: TWO-PLANE PROGRAM PAGE
tDBSY tPROG
R/B#
I/Ox
80h
Address (5 cycles) 1st-plane address
Data
input
11h
80h
Address (5 cycles) 2nd-plane address
Data
input
10h
70h
Status
Figure 48:
TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT

tDBSY
R/B#
I/Ox
80h
Address (5 cycles) 1st-plane address
Data
input
85h
Address (2 cycles) Different column address than previous 5 address cycles, for 1st plane only
Data
input
11h
80h
Address (5 cycles) 2nd-plane address
Data
input
tPROG R/B#
I/Ox
85h
Address (2 cycles) Different column address than previous 5 address cycles, for 2nd plane only
Data
input
10h
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Preliminary

TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h The TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h) operation is similar to the PROGRAM PAGE CACHE MODE (80h-15h) operation. It programs two pages of data from the data registers to the NAND Flash arrays. The pages must be programmed to different planes on the same die. Within a block, the pages must be programmed consecutively from the least significant to the most significant page address. Random page programming within a block is prohibited. The first-plane and second-plane addresses must meet the two-plane addressing requirements (see Two-Plane Addressing on page 58). To enter the two-plane program page cache mode, write the 80h command to the command register, write 5 ADDRESS cycles for the first plane, then write the data. Serial data is loaded on consecutive WE# cycles starting at the given address. Next, write the 11h command. The 11h command is a dummy command that informs the control logic that the first set of data for the first plane is complete. No programming of the NAND Flash array occurs. R/B# goes LOW for tDBSY, then returns HIGH. The READ STATUS (70h) command also indicates that the device is ready when status register bit 6 is set to 1. The only valid commands during tDBSY are READ STATUS (70h) and RESET (FFh). After tDBSY, write the 80h command to the command register, write 5 ADDRESS cycles for the second plane, then write the data. The CACHE WRITE (15h) command is written after the second-plane data input is complete. Data is transferred from the cache registers to the data registers on the rising edge of WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data registers and R/B# returns HIGH, memory array programming to both planes begins. When R/B# returns HIGH, new data can be written to the cache registers by issuing another TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h) sequence. The time that R/B# stays LOW (tCBSY) is determined by the actual programming time of the previous operation. For the first cache operation, the duration of tCBSY is the time it takes for the data to be copied from the cache registers to the data registers. On the second and subsequent TWO-PLANE PROGRAM PAGE CACHE MODE operations, transfer from the cache registers to the data registers is delayed until the current data register contents have been programmed into the arrays. If the R/B# pin is used to determine programming completion, the last operation of the program sequence must use the TWO-PLANE PROGRAM PAGE (80h-11h-80h-10h) command instead of the TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h15h) command. If the TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h-80h-15h) command is used for the last operation, then use READ STATUS (70h) to monitor operation progress; status register bit 5 indicates when programming is complete. See Table 13 on page 34 for details of the status register. To determine when the current TWO-PLANE PROGRAM PAGE CACHE MODE (80h-11h80h-10h) operation has completed, issue the READ STATUS (70h) command and check status register bits 5 and 6. When the device is ready, use status register bit 0 to determine if the current operation passed and status register bit 1 to determine if the previous operation passed. If either bit 0 or bit 1 = 1, indicating a failed operation, then use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twiceonce for each planeto determine which current or previous plane operation failed. For more information on status register bit definitions, see Table 13 on page 34. During the serial data input for either plane, the RANDOM DATA INPUT (85h) command can be used any number of times to change the column address within that plane. For details on this command, see RANDOM DATA INPUT 85h on page 36. See Figure 48 on page 63 for an example.
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Preliminary

Figure 49: TWO-PLANE PROGRAM PAGE CACHE MODE
tDBSY R/B# tCBSY
I/Ox
80h
Address/data input 1st plane
11h
80h
Address/data input 2nd plane
15h
tDBSY R/B#
tCBSY
I/Ox
80h
11h
80h
15h
tDBSY R/B#
tLPROG
I/Ox
80h
11h
80h
10h
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TWO-PLANE INTERNAL DATA MOVE 00h-00h-35h/85h-11h-85h-10h A TWO-PLANE INTERNAL DATA MOVE operation is similar to an INTERNAL DATA MOVE operation, and requires two sequences. Issue a TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command first, then the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) command. Data moves are only supported within the planes from which data is read. The first-plane and second-plane addresses must meet the two-plane addressing requirements for both the TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) and TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) commands (see Two-Plane Addressing on page 58). TWO-PLANE READ for INTERNAL DATA MOVE 00h-00h-35h The TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command is used in conjunction with the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h85h-10h) command. First, write 00h to the command register, then write the first-plane internal source address (5 cycles). Again, write 00h to the command register, followed by the second-plane internal source address (5 cycles). Finally, write 35h to the command register. After the 35h command, R/B# goes LOW for tR while 2 pages are read into their respective cache registers.
A TWO-PLANE RANDOM DATA READ (06h-E0h) command can be used to select the data transferred from the source pages of each plane. This command will change the starting column address on only the plane being selected. The column address on the plane moved from will remain unchanged from its previous location. To read out data after the TWO-PLANE READ for INTERNAL DATA MOVE command, either TWO-PLANE RANDOM DATA READ (06h-E0h) commands without limit or a combination of TWO-PLANE/MULTIPLE-DIE READ STATUS and RANDOM DATA READ (05h-E0h) commands can be issued. The memory device is now ready to accept the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) command. Alternatively, two READ for INTERNAL DATA MOVE (00h-35h) commands can be issued, each addressing different planes on the same die, prior to issuing the TWOPLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) command. TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-85h-10h After the TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command has been issued and R/B# goes HIGH (or the status register bit 6 is 1), the TWO-PLANE PROGRAM for INTERNAL DATA MOVE (85h-11h-85h-10h) command is used. Pages must be read from and programmed to the same plane. First, write 85h to the command register, then write the first-plane destination address (5 cycles), then write 11h to the command register. The 11h command is a dummy command that informs the control logic that the first set of data for the first plane is complete. No programming of the NAND Flash array occurs. R/B# goes LOW for tDBSY, then returns HIGH. The READ STATUS (70h) command also indicates that the device is ready when status register bit 6 is set to 1. The only valid commands during tDBSY are READ STATUS (70h) and RESET (FFh).
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After a TWO-PLANE READ for INTERNAL DATA MOVE (00h-00h-35h) command is issued, the data transferred from the source pages into the cache registers may be read out by toggling RE#. Data is output sequentially from the column address originally specified by the TWO-PLANE READ FOR INTERNAL DATA MOVE (00h-00h-35h) command, starting with plane 0.
Preliminary

After tDBSY, write the 85h command to the command register, then write the secondplane destination address (5 cycles), then write 10h to the command register. Data is transferred from the cache registers to the data registers on the rising edge of WE#, and programming begins on both planes. R/B# goes LOW for the duration of array programming time, tPROG. When programming and verification are complete, R/B# returns HIGH. The READ STATUS (70h) command also indicates that the device is ready when status register bit 6 is set to 1. The only valid commands during tPROG are READ STATUS (70h), TWO-PLANE/MULTIPLEDIE READ STATUS (78h), and RESET (FFh). If the READ STATUS (70h) command indicates an error in the operation (status register bit 0 = 1), use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twice once for each planeto determine which plane operation failed. During the serial data input for either plane, the RANDOM DATA INPUT (85h) command can be used any number of times to change the column address within that plane. For details on this command, see RANDOM DATA INPUT 85h on page 36. See Figure 52 on page 69 for an example.
tR R/B#
tDBSY
I/Ox
00h
Address (5 cycles) 1st-plane source
00h
Address (5 cycles) 2nd-plane source
35h
85h
Address (5 cycles) 1st-plane destination
11h
1
tPROG R/B#
I/Ox
85h
Address (5 cycles) 2nd-plane destination
10h
70h
Status
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Figure 50:
TWO-PLANE INTERNAL DATA MOVE
Preliminary

Figure 51: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ
tR R/B#
RE#
I/Ox
00h Address (5 cycles) 00h Address (5 cycles) 1st-plane source 2nd-plane source
35h
Data output Data from 1st-plane source
06h
Address (5 cycles)
E0h
2nd-plane source address
R/B#
RE#
I/Ox
Data output
05h
Address (2 cycles) 2nd-plane source column address
E0h
Data output Data from 2nd-plane source from new column address
Data from 2nd-plane source
Optional
tDBSY R/B#
tPROG
RE#
I/Ox 85h Address (5 cycles) 1st-plane destination 11h 85h Address (5 cycles) 2nd-plane destination 10h 70h Status
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Figure 52:
TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT

tR R/B#
I/Ox
00h
Address (5 cycles) 1st-plane source
00h
Address (5 cycles) 2nd-plane source
35h
85h
Address (5 cycles)
Data
85h
Address (2 cycles) Unlimited number of repetitions
Data
11h
1st-plane destination Optional
tDBSY R/B#
tPROG
I/Ox
85h
Address (5 cycles)
Data
85h
Address (2 cycles) Unlimited number of repetitions
Data
10h
70h
Status
2nd-plane destination Optional
69
1
TWO-PLANE BLOCK ERASE 60h-D1h-60h-D0h The TWO-PLANE BLOCK ERASE (60h-D1h-60h-D0h) operation is similar to the BLOCK ERASE (60h-D0h) operation. It erases two blocks instead of one. The blocks to be erased must be on different planes on the same die. The first-plane and second-plane addresses must meet the two-plane addressing requirements (see Two-Plane Addressing on page 58). To begin the TWO-PLANE BLOCK ERASE operation, write the 60h command to the command register, followed by 3 ADDRESS cycles of the first-plane block address. Next, write the D1h command. The D1h command is a dummy command. R/B# goes LOW for tDBSY, then returns HIGH. The READ STATUS (70h) command also indicates that the device is ready when the status register bit 6 is set to 1. The only valid commands during tDBSY are READ STATUS (70h) and RESET (FFh). After tDBSY, write the 60h command to the command register, followed by 3 ADDRESS cycles for the second plane. Finally, issue the D0h command. R/B# goes LOW for the duration of block erase time, tBERS. When block erasure is complete, R/B# returns HIGH. A READ STATUS command also indicates that the device is ready when status register bit 6 is set to 1. The only valid commands during tBERS are READ STATUS (70h, 78h) and RESET (FFh).
Preliminary
Draft 4/ 20/ 2008
Preliminary

If the READ STATUS (70h) command indicates an error in the operation (status register bit 0 = 1), then use the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command twiceonce for each planeto determine which plane operation failed. Alternatively, the D1h command may be omitted. In this case, there is no tDBSY time.
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Figure 53: TWO-PLANE BLOCK ERASE Operation
tDBSY
tBERS
60h
Address input (3 cycles) 1st plane
D1h
60h
Address input (3 cycles) 2nd plane
D0h
70h or 78h
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Optional
Preliminary

TWO-PLANE/MULTIPLE-DIE READ STATUS 78h In Micron NAND Flash devices that have two planes, and possibly more than one die in a package that share the same CE# pin, it is possible to independently poll the status register of a particular plane and die using the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command. This command can be used to check the status register during and after two-plane operations (with the exception of TWO-PLANE PAGE READ). After the 78h command is issued, the device requires 3 ADDRESS cycles containing the block and page addresses, BA[18:6] and PA[5:0]. The least significant block address bit in the first ADDRESS cycle, BA6, selects the proper plane. After the 78h command and the 3 ADDRESS cycles, the status register is output on I/O[7:0] when RE# is LOW. Changes in the status register will be seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to issue a new TWO-PLANE/MULTIPLE-DIE READ STATUS command to see these changes. The status register bit definitions are identical to those reported by the READ STATUS (70h) command (see Table 13 on page 34). Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited during and following power-on RESET and OTP commands.
Figure 54:
TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle

CE#
CLE
WE# tAR ALE
RE# tWHR I/Ox 78h Address (3 cycles) tREA Status output
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4Gb, 8Gb: x8, x16 NAND Flash Memory Command Definitions RESET Operation
RESET FFh The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data register and cache register contents are marked invalid. The status register contains the value E0h when WP# is HIGH; otherwise it is written with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the command register (see Figure 55 and Table 20). The RESET command must be issued to all CE#s as the first command after power-on. The device will be busy for a maximum of 1ms. Use of the TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) command is prohibited during and following the initial RESET command and OTP operations. Figure 55:
CLE
RESET Operation
CE#
tWB
WE#
tRST
R/B#
I/Ox
FFh RESET command
Table 20:
Condition WP# HIGH WP# LOW
Status Register Contents After RESET Operation

Status Ready Ready and write protected Bit 7 1 0 Bit 6 1 1 Bit 5 1 1 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 Hex E0h 60h
WRITE PROTECT Operation

It is possible to enable and disable PROGRAM and ERASE commands using the WP# pin. Figures 56 through 59 illustrate the setup time (tWW) required from WP# toggling until a PROGRAM or ERASE command is latched into the command register. After command cycle 1 is latched, the WP# pin must not be toggled until the command is complete and the device is ready (status register bit 5 is 1).
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Figure 56: ERASE Enable
WE# tWW I/Ox WP# R/B# 60h D0h
Figure 57:
ERASE Disable
WE# tWW I/Ox WP# R/B# 60h D0h
Figure 58:
PROGRAM Enable
WE# tWW I/Ox WP# R/B# 80h 10h (or 15h)
Figure 59:
PROGRAM Disable
WE# tWW I/Ox WP# R/B# 80h 10h (or 15h)
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Figure 60: PROGRAM for INTERNAL DATA MOVE Enable
WE# tWW I/Ox WP# R/B# 85h 10h
Figure 61:
PROGRAM for INTERNAL DATA MOVE Disable

WE# tWW I/Ox WP# R/B# 85h 10h
Figure 62:
TWO-PLANE ERASE Enable

WE# tWW I/Ox WP# R/B# 60h 60h D0h
Figure 63:
TWO-PLANE ERASE Disable

WE# tWW I/Ox WP# R/B# 60h 60h D0h
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Figure 64:
WE# tWW I/Ox WP# R/B# 80h 11h 80h 10h or 15h
TWO-PLANE PROGRAM Enable
Figure 65:
WE#
TWO-PLANE PROGRAM Disable
tWW I/Ox WP# R/B# 80h 11h 80h 10h or 15h
Figure 66:
WE#
TWO-PLANE PROGRAM for INTERNAL DATA MOVE Enable
tWW I/Ox WP# R/B# 85h 11h 80h 10h
Figure 67:
WE# I/Ox WP# R/B#
TWO-PLANE PROGRAM for INTERNAL DATA MOVE Disable
tWW 85h 11h 80h 10h
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4Gb, 8Gb: x8, x16 NAND Flash Memory Error Management
Error Management
This NAND Flash device is specified to have the minimum number of valid blocks (NVB) of the total available blocks per die shown in Table 21. This means the devices may have blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide bad-block management and error-correction algorithms. This ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array. NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by attempting to program the bad-block mark into every location in the first page of each invalid block. It may not be possible to program every location in an invalid block with the bad-block mark. However, the first spare area location in each bad block is guaranteed to contain the bad-block mark. This method is compliant with ONFI Factory Defect Mapping requirements. See Table 21 for the bad-block mark. System software should initially check the first spare area location for non-FFh data on the first page of each block prior to performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: Check status after each PROGRAM and ERASE operation. Under typical conditions, use the minimum required ECC shown in Table 21. Use bad-block management and wear-leveling algorithms.
The first block (physical block address 00h) for each CE# is guaranteed to be valid with ECC when shipped from the factory. Table 21: Error Management Details
Description Minimum number of valid blocks (NVB) Total available blocks per die Minimum required ECC First spare area location Bad-block mark Requirement 4,016 4,096 1-bit ECC per 528 bytes of data x8: byte 2,048 x16: word 1,024 x8: 00h x16: 0000h
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics
Electrical Characteristics
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 22: Absolute Maximum Ratings
Voltage on any pin relative to VSS Parameter/Condition Voltage input VCC supply voltage 1.8V 3.3V 1.8V 3.3V Symbol VIN VIN VCC VCC TSTG Min 0.6 0.6 0.6 0.6 65 Max +2.4 +4.6 +2.4 +4.6 +150 5 Unit V V V V C mA
Storage temperature Short circuit output current, I/Os
Table 23:
Recommended Operating Conditions

Parameter/Condition Operating temperature Extended temperature VCC supply voltage Ground supply voltage Symbol TA VCC VCC VSS Min 0 40 1.65 2.7 0 Typ 1.8 3.3 0 Max +70 +85 1.95 3.6 0 Unit C C V V V
Figure 68:
I/Ox
Interleaved PROGRAM for INTERNAL DATA MOVE with Status Register Monitoring
85h Address Data 10h 78h Address Status 78h Address Status
85h Address Data 10h
Die 1 R/B# (die 1 internal) R/B# (die 2 internal) R/B# (external)
Die 2
Die 1
Die 2
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Electrical Characteristics VCC Power Cycling
Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. (The WP# signal permits additional hardware protection during power transitions.) When VCC reaches 2.5V for a 3.3V device or 1.5V for a 1.8V device, a minimum of 100s should be allowed for the Flash device to initialize before any commands are executed (see Figure 69 for signal states during VCC power cycling). Both of the following conditions must be satisfied before R/B# will be valid: 50s have elapsed since Vcc started its ramp. 10s have elapsed since Vcc reached 2.5V for 3.3V or 1.5V for 1.8V The RESET command must be issued to all CE#s as the first command after the NAND Flash device is powered on. Each CE# will be busy for a maximum of 1ms after a RESET command is issued. Each NAND die will draw no more than IST prior to execution of the first RESET command after the device is powered on. Figure 69: AC Waveforms During Power Transitions
3V device: 2.5V 1.8V device: 1.5V
VCC
3V device: 2.5V 1.8V device: 1.5V
CLE
tCS
CE#
WP#
WE#
100s
(MIN)
ALE
RE#
I/Ox
FFh
1ms
R/B#
10s
(MAX)
(MAX)
50s
(MAX)
Dont Care
Undefined
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Preliminary

Table 24:
Parameter Sequential READ current PROGRAM current ERASE current Standby current (TTL) Standby current (CMOS) Input leakage current Output leakage current Input high voltage
t t
DC and Operating Characteristics (3.3 V)

Conditions RC = RC (MIN); CE# = VIL; IOUT = 0mA CE# = VIH; WP# = 0V/VCC CE# = VCC - 0.2V; WP# = 0V/VCC VIN = 0V to VCC VOUT = 0V to VCC I/O[7:0], I/O[15:0], CE#, CLE, ALE, WE#, RE#, WP#, R/B# IOH = 100A IOL = 100A VOL = 0.2V Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH Min 0.8 x VCC Typ 25 25 25 10 Max 35 35 35 1 50 10 10 VCC + 0.3 Unit mA mA mA mA A A A V Notes
Notes: 1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full. 2. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to full.
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Input low voltage, all inputs Output high voltage Output low voltage Output low current
VIL VOH VOL IOL (R/B#)
0.3 2.4 8
10
0.2 x VCC 0.4
V V V mA 1 1 2
Preliminary

Table 25:
Parameter Sequential READ current PROGRAM current ERASE current Standby current (TTL) Standby current (CMOS) Input leakage current Output leakage current Staggered power-up current Input high voltage Input low voltage (all inputs) Output high voltage Output low voltage Output low current (R/B#)
t t
DC and Operating Characteristics (1.8 V)

Conditions RC = RC (MIN); CE# = VIL; IOUT = 0mA CE# = VIH; WP# = 0V/VCC CE# = VCC 0.2V; WP# = 0V/VCC VIN = 0V to VCC VOUT = 0V to VCC Rise time = 1ms Line capacitance = 0.1F I/Ox, CE#, CLE, ALE, WE#, RE#, WP# IOH = 400A IOL = 2.1mA VOL = 0.4V Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO IST VIH VIL Min 0.8 x VCC 0.3 Typ 20 20 20 10 10 Max 40 40 40 1 50 10 10 10 per die VCC + 0.3 0.2 x VCC 0.4 Unit mA mA mA mA A A A mA V V Notes 1 1 1
Notes: 1. This is for single-die operations. It can be greater for interleaved die operations. 2. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC (MIN). 3. Test conditions for VOH and VOL. 4. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full. See Table 19 on page 56 for additional details.
Table 26:
Valid Blocks
Parameter Valid block number Symbol NVB Device MT29F4G08AAC Min 4,016 Max 4,096 Unit blocks Notes 1, 2
Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the factory.
Table 27:
Capacitance
Description Input capacitance Input/output capacitance (I/O) Symbol CIN CIO Max 10 10 Unit pF pF Notes 1, 2 1, 2
Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: Tc = 25C; f = 1 MHz; VIN = 0V.
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VOH 0.67 x VCC VOL IOL (R/B#) 8
V V mA
3 3 4
Preliminary

Table 28: Test Conditions
Parameter Input pulse levels Input rise and fall times Input and output timing levels Output load Value 0.0V to VCC 5ns VCC/2 1 TTL GATE and CL = 30pF (1.8V) 1 TTL GATE and CL = 50pF (3.3V) Notes
Notes: 1. Verified in device characterization, not 100 percent tested.
Table 29:
AC Characteristics: Command, Data, and Address Input (3.3V)

Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# setup time Symbol
tADL tALH tALS tCH tCLH tCLS tCS tDH tDS tWC tWH tWP tWW
Min 70 5 10 5 5 10 15 5 10 25 10 12 100
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1
Notes: 1. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input.
Table 30:
AC Characteristics: Command, Data, and Address Input (1.8V)

Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# setup time Symbol
tADL t
Min1 100 10 15 10 5 15 25 5 15 35 15 17 100
Max1
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1 1 1 1 1 1 1 1 1 1, 2 1, 2 1, 2 1
ALH t ALS tCH tCLH tCLS t CS t DH tDS tWC tWH t WP tWW
Notes: 1. Operating-mode timings meet ONFI timing mode 4 parameters. 2. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input.
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Preliminary

Table 31: AC Characteristics: Normal Operation (1.8V)
Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Cache busy in page read cache mode (first 31h) Cache busy in page read cache mode (next 31h and 3Fh) Output High-Z to RE# LOW Data transfer from Flash array to data register READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH to RE# LOW Symbol
tAR t
Min 10 10 15
t
Max 30 45 3 25 25 25 100 5/10/500 100
Unit ns ns ns ns ns s s ns s ns ns ns ns ns ns ns ns s ns ns
Notes 1 1 1, 2 1 1 1 1 1 1 1 1 1 1 1 1, 2 1 1 1, 3 1, 4 1
CEA t CHZ tCLR t COH t DCBSYR1

t t
DCBSYR2 IR
DCBSYR1 0 35 15 15 100 17 20 80
tR tRC tREA tREH tRHOH tRHW tRHZ tRP tRR tRST tWB tWHR
Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested 3. The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5s. 4. Do not issue a new command during tWB, even if R/B# is ready.
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Preliminary

Table 32: AC Characteristics: Normal Operation (3.3V)
Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Cache busy in page read cache mode (first 31h) Cache busy in page read cache mode (next 31h and 3Fh) Output High-Z to RE# LOW Data transfer from Flash array to data register READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH to RE# LOW Symbol
tAR t
Min 10 10 15
t
Max 25 30 3 25 25 20 100 5/10/500 100
Unit ns ns ns ns ns s s ns s ns ns ns ns ns ns ns ns ns s ns ns
Notes 1 1 1, 2 1 1 1 1 1 1 1 1 1 1 1 1, 2 1 1 1 1, 3 1, 4 1
CEA t CHZ tCLR t COH t DCBSYR1

t t
DCBSYR2 IR
DCBSYR1 0 25 10 15 100 5 12 20 60
tR tRC tREA tREH tRHOH tRHW tRHZ tRLOH tRP tRR tRST tWB tWHR
Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. 3. The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5s. 4. Do not issue a new command during tWB, even if R/B# is ready.
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Preliminary

Table 33:
Symbol NOP t BERS t CBSY
t
PROGRAM/ERASE Characteristics
Parameter Number of partial-page programs BLOCK ERASE operation time Busy time for PROGRAM CACHE operation Typ 2 3 3 0.5 300 220 Max 4 3 700 600 1 1 30 700 600 Unit cycles ms s s s s s s s Notes 1 2 3 3
DBSY
tFEAT t t
LPROG OBSY tPROG
1.8V 3.3V Busy time for TWO-PLANE PROGRAM PAGE or TWO-PLANE BLOCK ERASE operation Busy time for SET FEATURES and GET FEATURES operations LAST PAGE PROGRAM operation time Busy time for OTP DATA PROGRAM operation if OTP is protected PROGRAM PAGE operation time 1.8V 3.3V Notes: 1. 2. 3. 4.
4 2 2
Four total partial-page programs to the same page. Typical tPROG and tBERS time may increase for two-plane operations. tCBSY MAX time depends on timing between internal program completion and data-in. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) address load time (last page) - data load time (last page).
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Timing Diagrams
Timing Diagrams
Figure 70: COMMAND LATCH Cycle
CLE tCLS tCS CE# tWP WE# tALS ALE tALH tCLH tCH
tDS I/Ox
tDH
COMMAND
Dont Care
Note:
I/O[15:8] on the x16 device must be set to 0.
Figure 71:
ADDRESS LATCH Cycle

CLE tCLS tCS CE# tWC tWP WE# tALS tALH ALE tDS tDH I/Ox Col add 1 Col add 2 Row add 1 Row add 2 Dont Care Row add 3 Undefined tWH
Note:
I/O[15:8] on the x16 device must be set to 0.
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Preliminary

Figure 72:
CLE tCLH
INPUT DATA LATCH Cycle
CE# tALS ALE tWC tWP WE# tWH tDS tDH I/Ox tDS tDH tDS tDH tWP tWP tCH
DIN 0
DIN 1
DIN Final1
Dont Care
Notes: 1. DIN Final = 2,111 (x8).
Figure 73:
SERIAL ACCESS Cycle After READ

tCEA
CE# tREA tRP RE# tRHZ tRHZ tRHOH I/Ox tRR R/B# Dont Care tREH tREA tREA tCOH tCHZ
DOUT
tRC
DOUT
DOUT
Note:
Use this timing diagram for tRC 30ns.
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Preliminary

Figure 74: SERIAL ACCESS Cycle After READ (EDO Mode)
CE# tRC tRP RE# tREA tCEA I/Ox tREA tRLOH tRHZ tRHOH tREH tCHZ tCOH
DOUT
DOUT
DOUT
tRR R/B#
Note:
Use this timing diagram for tRC < 30ns.
Figure 75:
READ STATUS Operation

tCLR
CLE tCLS tCLH
tCS CE# tWP WE# tCEA tWHR RE# tRP tCH
tCHZ tCOH
tRHZ tRHOH tDS tDH tIR tREA Status output
I/Ox
70h
Dont Care
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Dont Care
Preliminary

Figure 76: TWO-PLANE/MULTIPLE-DIE READ STATUS Operation
tCS
CE#
tCLS tCLH
CLE
tWP tWC tWP tWH tCH tCEA tALH tALS tALH tAR tCHZ tCOH
WE#
ALE
RE#
tDS tDH 78h Row add 1 Row add 2 Row add 3 tWHR tREA
tRHZ tRHOH Status output
I/Ox
Dont Care
Figure 77:
CLE
PAGE READ Operation
tCLR
CE#
tWC
WE#
tWB tAR
ALE
tR tRC tRHZ
RE#
tRR tRP DOUT N DOUT N+1 DOUT M
I/Ox
00h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
30h
Busy
R/B# Dont Care
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Preliminary
Data output
Dont Care
READ Operation with CE# Dont Care
CLE
CE#
RE#
ALE
R/B#
Figure 78:
WE#
I/Ox
00h
Address (5 cycles)
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tCOH I/Ox RE# Out CE# tREA tCHZ
tR
30h
tCEA
Preliminary
tCLR
tWHR
tREA
E0h
DOUT M
05h
Column address M
Col add 1
Col add 2
Dont Care
DOUT M+1
RANDOM DATA READ Operation
Row add 1
00h
Column address N
Col add 1
Col add 2
Figure 79:
WE#
R/B#
CLE
CE#
ALE
RE#
I/Ox
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Busy
tRHW
tAR
tWB
tR
tRR Row add 2 Row add 3 30h
DOUT N
tRC
DOUT N+1
Figure 80:
CLE
PAGE READ CACHE MODE Operation, Part 1 of 2
tCLS tCLH
tCS
tCH
CE#
tWC
WE#
tCEA tRHW
ALE
tRC
RE#
tDS tDH
tWB
tR tREA tRR
I/Ox
00h
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
30h
31h
DOUT 0
DOUT 1 Page address M
DOUT
31h
DOUT 0 Page address M+1
Column address 00h
Page address M
tDCBSYR1
tDCBSYR2
92
R/B#
Column address 0 Column Address 0
Continued to 1 of next page
Dont Care
Preliminary
Draft 4/ 20/ 2008
Figure 81:
CLE
PAGE READ CACHE MODE Operation, Part 2 of 2
tCLS tCS
tCLH tCH
CE#
WE#
tCEA tRHW tRHW
ALE
tRC
RE#
tWB tDS tDH
tRR
tREA DOUT 0 DOUT 1 DOUT

31h
I/Ox
DOUT
31h tDCBSYR2
DOUT 0 tDCBSYR2
DOUT 1
DOUT
3Fh tDCBSYR2
DOUT 0
DOUT 1
DOUT
Page address M+1
Page address M+2
Page address M+x
R/B#
Column address 0 Column address 0 Column address 0
93
1
Continued from 1 of previous page
Dont Care
Preliminary
Draft 4/ 20/ 2008
Preliminary

Figure 82: PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2
CLH
CH
tWC
tCEA
tRHW
tRC
DH
Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 30h 70h Status 31h 70h Status 00h
tREA DOUT 0 DOUT 1 Page address M DOUT

31h 70h Status 00
Column address 0
Colum
1
Continued to 1 of next page
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Column address 00h
Page address M
I/O 5 = 0, Busy = 1, Ready
I/O 6 = 0, Cache busy = 1, Cache ready
I/O 6 = 0, Cache busy = 1, Cache read
Preliminary

Figure 83: PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2
CLS
tCLH
CS
tCH
tCEA
tRHW
tRC
tDS tDH 31h 70h Status
tREA 00h DOUT 0 DOUT 1 Page address M+1 DOUT 31h 70h Status 00h DOUT 0 DOUT 1 Page address M+2 DOUT 3Fh 70h Status 00h DOUT 0 DO 1 Page M
Column address 0
Column address 0
Column address 0
om 1 page
Figure 84:
CLE
READ ID Operation
CE#
WE# tAR ALE
RE# tWHR I/Ox 90h 00h (or 20h) Address, 1 cycle tREA Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Note:
See Table 10 on page 30 for actual values.
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Preliminary

Figure 85:
CLE
PROGRAM PAGE Operation
CE# tWC WE# tWB ALE tPROG tWHR tADL
RE#
I/Ox
80h SERIAL DATA INPUT command
Col add 1
Col add 2
Row add 1
Row add 2
Row add 3
DIN N
DIN M
10h PROGRAM command
Status
1 up to m Byte serial input
R/B# x8 device: m = 2,112 bytes
Dont Care
Figure 86:
CLE
Program Operation with CE# Dont Care
CE#
WE#
ALE
I/Ox
80h
Address (5 cycles)
Data
input
Data
input
10h
tCS
CE#
tCH
tWP
WE#
Dont Care
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Figure 87:
PROGRAM PAGE Operation with RANDOM DATA INPUT

CLE
CE# tWC WE# tWB ALE tPROG tWHR tADL tADL
RE# I/Ox
80h
SERIAL DATA INPUT command Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 DIN N DIN N+1
85h
Col add 1
Col add 2
DIN N
DIN N+1 Serial input
10h
PROGRAM command
70h
READ STATUS command
Status
RANDOM DATA Column address Serial input INPUT command
R/B# Dont Care
97 Figure 88:
INTERNAL DATA MOVE Operation
CLE
CE#
tWC tADL
WE#
tWB tWB tPROG tWHR
ALE
RE# I/Ox
00h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 35h
tR
85h Col Col Row Row Row add 1 add 2 add 1 add 2 add 3 Data 1 Data N 10h 70h Status
Busy
Busy
READ STATUS
R/B#
INTERNAL DATA MOVE
Preliminary
Dont Care
Draft 4/ 20/ 2008
Preliminary

Note: INTERNAL DATA MOVE operations are only supported within the plane from which data is read.
Figure 89:
CLE
PROGRAM PAGE CACHE MODE Operation
CE#
tWC tADL
WE#
tWBtCBSY tWB tLPROG tWHR
ALE
RE# I/Ox
80h Col Col Row Row Row add 1 add 2 add 1 add 2 add 3
SERIAL DATA INPUT
DIN DIN 15h N M Serial input PROGRAM
80h
Col Col Row Row Row add 1 add 2 add 1 add 2 add 3
DIN N
DIN 10h M PROGRAM
70h
Status
R/B#
Last page - 1 Last page
Dont Care
Figure 90:
PROGRAM PAGE CACHE MODE Operation Ending on 15h
tADL
tADL
tWHR
tW
Row Row Row Col Col dd 1 add 2 add 1 add 2 add 3
DIN DIN 15h 70h N M Serial input PROGRAM
Status
80h
Col Row Row Row Col add 1 add 2 add 1 add 2 add 3
DIN N
DIN M
15h
PROGRAM
70h
Status
70h
Last page 1
Last page
Poll status until: I/O6 = 1, Ready
To verify successful completio I/O5 = 1, Ready I/O0 = 0, Last page PRO I/O1 = 0, Last page 1 P
98
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Preliminary

Figure 91:
CLE
BLOCK ERASE Operation
CE#
tWC
WE#
tWB tWHR
ALE
RE#
tBERS
I/Ox
60h
Row add 1
Row add 2
Row add 3
D0h ERASE command Busy
Status
Row address
R/B#
AUTO BLOCK ERASE SETUP command
I/O0 = 0, Pass I/O0 = 1, Fail
Dont Care
Figure 92:
CLE
RESET Operation
CE#
tWB
WE#
tRST
R/B#
I/Ox
FFh RESET command
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Package Dimensions
Package Dimensions
Figure 93: 48-Pin TSOP OCPL Type 1
0.25 for reference only 0.50 for reference only 48 1 Mold compound: Epoxy novolac Plated lead finish: 100% Sn Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side.
20.00 0.25 18.40 0.08
12.00 0.08
0.27 MAX 0.17 MIN
24
25
0.10 0.15 +0.03 -0.02 See detail A 1.20 MAX 0.25 Gage plane 0.10 +0.10 -0.05 0.50 0.1 0.80
Detail A
Note:
All dimensions are in millimeters.
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Preliminary

Figure 94: 52-Pad ULGA/VLGA Package
Seating plane See Detail A 0.1 A A See Note 1 Detail A Not to scale2 40X 0.71 12X 11
8 7 6
6 4 2
5
3 0.7 Pad A1 ID
3 2 1 0
Substrate material: plastic laminate Mold compound: epoxy novolac Pad A1 ID
OA
A B
7.8
17 0.1
OB C
OC E F
13 12
1 2 TYP
G H J OD K L OE M N OF
6.5 2 TYP
2 TYP 6 0.05 10 12 0.1 5
0.65 MAX
Notes: 1. Pads are non-solder-mask defined (NSMD) and are plated with 5-16 microns of nickel followed by a minimum of 0.50 microns of soft-wire-bondable gold (99.99% pure).
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
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8.5 0.05
Preliminary

2. Primary datum A (seating plane) is defined by the bottom terminal surface. Metallized test terminal lands or interconnect terminals need not extend below the package bottom surface. 3. All dimensions are in millimeters.
Figure 95:
63-Ball VFBGA Package

0.65 0.05
Seating plane 0.10 A A 7.20 63X 0.45 Dimensions apply to solder balls post reflow. Pre-reflow ball is 0.42 on a 0.4 SMD ball pad. Ball A10 0.80 TYP 0.80 TYP Ball A1 ID
Solder ball material: 96.5% Sn, 3%Ag, 0.5% Cu Substrate material: Plastic laminate Mold compound: Epoxy novolac Ball A1 ID
Ball A1
8.80
C L
13.00 0.10
4.40 6.50 0.05
C L 3.60 10.50 0.10 5.25 0.05 1.00 MAX
Note:
All dimensions are in millimeters.
102
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Revision History Revision History
Rev. 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/20/07 Updated ONFI parameter page on Table 12 on page 32 Changed the datasheet status to preliminary. Rev. 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/29/07 Updated ONFI parameter page on Table 12 on page 32. Table 10, Device ID and Configuration Codes for Address 00h, on page 30: Corrected 1.8V serial access (MIN) to 35ns. Rev. 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/29/07 Features on page 1: Removed Random READ; updated 1.8V sequential READ to 35ns (MIN); removed READ ID2. Table 10, Device ID and Configuration Codes for Address 00h, on page 30: Corrected 1.8V serial access (MIN) to 35ns. Error Management on page 77: Updated section and added Table 21, Error Management Details, on page 77. Vcc Power Cycling on page 79: Updated section content. Table 29, AC Characteristics: Command, Data, and Address Input (3.3V), on page 82, Table 30, AC Characteristics: Command, Data, and Address Input (1.8V), on page 82 and Table 31, AC Characteristics: Normal Operation (1.8V), on page 83: Updated values as necessary. Rev. 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/07 Modified pat numbers throughout document to support all part numbers for x8 and x16 respectively. Options on page 1: Changed value of extended operating temperature. Table 8, Block-Lock Command Set, on page 23: Added table. Table 10, Device ID and Configuration Codes for Address 00h, on page 30: Corrected I/O7 values for byte 3 serial access, and content in the Values column for the same two rows. Block Lock Feature (1.8V only) on page 42: added (1.8V only). Vcc Power Cycling on page 79: Updated second bullet from 10s to 100s. Table 29, AC Characteristics: Command, Data, and Address Input (3.3V), on page 82: Added missing parenthesis in title and updated tWC MIN to 25. Table 30, AC Characteristics: Command, Data, and Address Input (1.8V), on page 82: Updated values. Table 31, AC Characteristics: Normal Operation (1.8V), on page 83: Updated values. Table 32, AC Characteristics: Normal Operation (3.3V), on page 84: Updated values. Rev. 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/07 Title on page 1: Added MT29F8G08EACC3 part number. Figure 1 on page 1: Removed ULGA from title. Features on page 1: Added 1.8V Program Page to WRITE performance; reworded First block description; removed contact factory from Advanced command set; added Block lock feature. Options on page 1: Added Extended temperature.
NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fm - Rev. 1.5 4/08 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Revision History

Figure 2 on page 2: Added E classification; added C3 and HC to Package Code. Figure 3 on page 8: Added figure for 1.8V pin assignments. General Description on page 8: Added two-die description; reworded first paragraph. Figure 4 on page 9 Added figure to show 52-Pad ULGA pin assignment. Note 1 on page 9: Changed to 8GB; changed description of ONFI specification. Figure 5 on page 10, Figure 6 on page 11: Added ball diagrams. Table 1 on page 12: Added symbols to Symbol column. Figure 7 on page 13: Added Note 1. Figures 8 and Table 2 on page 14: Changed figure heading from AAC to xxx. Figure 9 and Table 3 on page 15: Changed figure heading from AAC to xxx. Table 4 on page 16: Removed footnotes numbers from body of the table. Table 5 on page 17: Removed footnotes numbers from body of the table. Bus Operation on page 18: Revised description. Control Signals on page 18: Revised first paragraph. Ready/Busy# on page 19: Added new second paragraph. Note 1 on 24: Added reference to Table 5 on page 17. Table 10 on page 30: Added note, corrected values on serial access lines. Table 11 on page 31: Changed figure title; added Note 1. Table 12 on page 32: Changed figure title; updated values; added values for each device model. BLOCK ERASE Operation on page 41: Added MT29F8G: replaced with 1.8V description.; added reference to Table 5 on page 17. Table 14 on page 44: Removed Note 3. BLOCK LOCK READ STATUS 7Ah on page 46: Changed first cross-reference to Table 14 on page 44. Table 17 on page 55: Added notes 2, 3, and 4 describing 1.8V and 3.3V features. Vcc Power Cycling on page 79: Added 1.8V values. RESET FFh on page 73: Reworded first sentence of fourth paragraph. Table 22 on page 78: Added 1.8V and 3.3V values. Tables 22 and 23 on page 78: Swapped table title names. : Vcc Power Cycling on page 79: changed timing value for VCC in second bullet. Figure 69 on page 79: Replaced figure with figure 67 of M51A and added 1.8V values. Table 25 on page 81: Added headings; renumbered footnotes. Table 29 on page 82: Added tCCS and tRC values; updated tWC value; deleted footnote. Table 30 on page 82: Updated 1.8V values. Table 31 on page 83: Updated 1.8V values; removed duplicate lines; renumbered footnotes. Table 32 on page 84: Renumbered footnotes. Table 33 on page 85: Added 1.8V typical value for tPROG; renumbered footnotes. Figure 94 on page 101: Added 52-Pad ULGA/VLGA package diagram. Figure 95 on page 102: Added 63-ball package diagram. Rev. 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/22/07 Added text, tables, and figures to incorporate the x16 MT29F4G16AAC device. Rev 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/19/07
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Preliminary
4Gb, 8Gb: x8, x16 NAND Flash Memory Revision History

Figure 2: Part Number Chart on page 2: Updated package code from WP to WC and design revision from A to C. Figure 3: Pin Assignment (Top View) 48-Pin TSOP OCPL Type 1 on page 8: Changed pin 38 from NC to DNU. Table 7: Command Set on page 23: Added READ STATUS ENHANCED command. PROGRAM PAGE CACHE MODE 80h-15h on page 37: Corrected last paragraph bit 0 to bit 1. Table 12: ONFI Parameters on page 32: Added ONFI parameters table. Features Operations on page 55: Clarified description. Rev. 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/04/07 Initial release.
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Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory Features

NAND Flash Memory

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__1.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

Part Numbering Information

Operating Temperature Range

Blank 1 2 Common Separate

Operating Voltage Range

Valid Part Number Combinations

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__1.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Reserved for Future Use

Micron Confidential and Proprietary

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory Table of Contents

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50aTOC.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50aLOF.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory List of Figures

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50aLOF.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50aLOT.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory General Description

Pin Assignment (Top View) 48-Pin TSOP OCPL Type 1

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory General Description

Top View, Pads Down

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory General Description

Top View, Ball Down

For package dimensions, see Figure 95 on page 102.

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory General Description

Top View, Ball Down

For package dimensions, see Figure 95 on page 102.

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory General Description

Symbol ALE, ALE2

Input Input Input I/O

VCC VSS NC DNU

NDA PDF: 09005aef8284fb62 / Source: 09005aef8284f890 nda_4gb_8gb_nand_m50a__2.fm - Rev. 1.5 4/08 EN

Draft 4/ 20/ 2008

Micron Confidential and Proprietary

4Gb, 8Gb: x8, x16 NAND Flash Memory Architecture

NAND Flash Functional Block Diagram

Address Register Status Register

NAND Flash Array (2 planes)

Data Register R/B# Cache Register