`timescale 1ns/1ps

`include "mips_16_defs.v"
module foward
(
//input clk
input [2:0] ex_mem_foward_dest,
input [2:0] mem_wb_foward_dest,
input [2:0] id_ex_rs,
input [2:0] id_ex_rt,
input ex_mem_write_back_en,
input mem_wb_write_back_en,
output reg [1:0] foward_a,
output reg [1:0] foward_b
);

always @ (*) begin

foward_a = 2'b00;
foward_b = 2'b00;

if( ( ex_mem_write_back_en == 1 ) && ( ex_mem_foward_dest !=0 && id_ex_rs !

= 0) && ( id_ex_rs == ex_mem_foward_dest))
foward_a = 2'b10; // EX_hazard
if (( ex_mem_write_back_en == 1 ) && ( ex_mem_foward_dest !=0 && id_ex_rt !=
0 )&& ( id_ex_rt == ex_mem_foward_dest))
foward_b = 2'b10;// EX_hazard
if (( ex_mem_write_back_en == 1 ) && ( ex_mem_foward_dest !=0 && id_ex_rs !=
0) && ( id_ex_rs == ex_mem_foward_dest)&& (mem_wb_write_back_en == 1) && ( id_e
x_rs != ex_mem_foward_dest) &&( mem_wb_write_back_en !=0 && id_ex_rs != 0) && (
id_ex_rs == mem_wb_foward_dest))
foward_a = 2'b01; // Mem_hazard
if(( ex_mem_write_back_en == 1 ) && ( ex_mem_foward_dest !=0 && id_ex_rt !=
0 )&& ( id_ex_rt == ex_mem_foward_dest) && (mem_wb_write_back_en == 1) && ( id_e
x_rt != ex_mem_foward_dest) &&(mem_wb_write_back_en !=0 && id_ex_rt != 0) && ( i
d_ex_rs == mem_wb_foward_dest))
foward_b = 2'b01; // Mem_hazard

end

endmodule