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Hng dn s dng Quartus II thit k mch

V hm trc katsu c thy bi hi ca 1 thnh vin trong din n v cch s dng Quartus II li tin lc katsu ang hc lp Thit k mch s dng Icarus Verilog v Quartus nn katsu vit bi hng dn ny. Nu c g sai st th cc bn ch cho.

Ni dung ca bi vit ny ch n gin gii thiu v cc bc tin hnh ln lt nhm to 1 mch in t vi Quartus sau khi cc bn thit k c mch vi ngn ng Verilog v hon thnh kim tra phn code ri. Thit b chnh dng kim tra c s dng l DE01 Board. < ="-" ="text/; =utf-8">< name="ProgId" ="Word.">< name="Generator" ="Microsoft Word 12">< name="Originator" ="Microsoft Word 12">

Cc bc tin hnh:

1. M Quartus II bng cch click i vo biu tng ca Quartus trn mn hnh Desktop.

2. Sau khi chy cc file h thng, Quartus II s m ra mn hnh khi ng ca mnh

Chn Create a New Project to mt Project mi hoc chn Open Existing Project chn m Project m bn thc hin. Quartus cng hin th ch bn mt s Project m bn thc hin trong thi gian gn y phn Open Recent Project (th t ca cc Project c sp xp theo ln cui cng bn m Project).

3. Nu bn chn Create a New Project. Ca s New Project Wizard s hin ra, bn chn Next.

4. ca s tip theo, bn ch ng dn ti folder cho Project mi ca bn. Thng th katsu s to mt folder mi trong my, ly tn ty theo mch mun thit k. Sau c mt bc quan trng l copy file code Verilog( bin son bng Notepad++ hoc bt k mt trnh editor no c h tr ngn ng Verilog) vo trong folder ny.

Trong 2 tip theo, Quartus yu cu bn nh vo tn ca Project mi, ch ly tn ca project trng vi tn ca module m bn bin son trong Verilog. V d katsu s dng code ca bi thit k cho Led 7 on hin th cc s t 0-9 sau:

/*********************************************************** * Author: Hoang Minh Vu * Module: led7seg * Description: ***********************************************************/ Class: 06ECE

module led7seg ( SW, Led_Out); input [3:0] SW;

output

[0:6] Led_Out;

//reg

[6:0] Led_Out;

// the function of output assign Led_Out[0] = (!SW[3])&&(!SW[2])&& (!SW[1]) && (SW[0]) || SW[0]); assign Led_Out[1] = (!SW[3])&& SW[2] && (!SW[1]) && SW[0] || (!SW[3]) && SW[2] && SW[1] && (! (!SW[3])&& SW[2]&&(!SW[1])&&(!

SW[0]); assign assign

Led_Out[2] =(!SW[3]) && (!SW[2]) && SW[1] && (!SW[0]); Led_Out[3] =(!SW[3])&&(!SW[2])&& (!SW[1]) && (SW[0]) || (!SW[3])&& SW[2]&&(!SW[1])&&(!

SW[0])

SW[0];

||

(!SW[3])&& SW[2] && SW[1] &&

endmodule

module led7seg_tb;

parameter DELAY = 10; .....

// constant value

V tn ca module thc thi l led7seg nn trong 2 di ca ca s Project Wizard, katsu cng s nh vo l led7seg.

5. Sau khi nhn Next, Quartus s i bn thm file code cho Project. Bn chn ng dn ti file code Verilog nm trong folder project m bn mi to trn. Sau nhn Add. ngay di , bn s thy file code ca bn (ging nh trong hnh l file led7seg.v, loi file l Verilog HDL file).

6. Bc 6 l chn loi thit b m bn mun s dng test. Trong v d ny, katsu s s dng b DE1 Board, l bng mch dng th nghim ti phng lab ca Chng trnh tin tin ECE.

Cc thng s c chn nh trong hnh v. Lu cc thng s ny c chn ty thuc vo loi thit b m bn dng th nghim, trc khi thc hin bc ny cn xem v kim tra k cc thng s trc khi bn nhn Finish.

7. Sau khi nhn Finish, bn hon thnh thit lp nhng thng s u tin cho Project ca mnh.

Sau khi Quartus m cc file cn thit, ti ca s Project Navigator, cc bn chn tab Files, v m file code (file .v) ra bng cch click i vo file .

8. Trong ca s mi hin ra c cha ton b phn code ca bn, xa ton b phn code dnh cho cc module Tester hoc module Testbench(nhng module ny khng phi l phn code ca mch m bn vit, chng ch c dng thit lp mt s trng thi v iu kin kim tra s hot ng ca mch. Khi kim tra bng thit b thc s, bn khng cn ti cc module ny na).

Sau , bn nhn nt Start Compilation Quartus bt u bin dch phn code ca bn.

9. Trong qu trnh bin dch, nu pht hin li, Quartus s bo qu trnh bin dch khng thnh cng cng s li. Nhng dng ch mu tab Processing bn di s th hin cho cc bn nhng li m bn mc phi. Click i vo cc dng s dn bn ti v tr trong phn code m bn c li. Sau khi hon tt sa li (debugging), Quartus s bo bin dch thnh cng. (Trong thc t, Quartus s bo c bao nhiu warning (cnh bo) trong chng trnh ca bn. Nhng tm thi bn cha cn ch ti cc cnh bo ny)

10. Sau khi hon tt bin dch, bn c th xem c s mch m bn thit k bng cch chn Tools/Netlist Viewers/RTL Viewer. Bn c th kim tra xem cc cng trong mch bn thit k c hin th ra trong Quartus ng theo bn mong mun hay khng.

nh c thu nh .Click vo thanh ny thy nh size nguyn gc. (648 x 393)

11. Ti y, chng trnh ca bn c sn sng thc hin ti thit k mch xung v kim tra bng thit b thc s. Chn Assignments/Assignment Editor. Trong mc Category, bn chn PIN. Trong mc Edit, bn da trn cc ch dn thng s ca thit b nhp s PIN vo ty thuc vo tn hiu u ra hay u vo v ty thuc vo bn mun tn hiu ra c hin th bng g.

Vi v d v on m cho Led 7 on, input ca katsu s c gn vi 4 chn PIN ca 4 cng tc (toggle switch), output s c gn vi chn PIN ca 1 n Led 7 on.

nh c thu nh .Click vo thanh ny thy nh size nguyn gc. (628 x 318)

12. Sau khi hon tt gn chn PIN, bn nhn Start Compilation mt ln na Quartus ly cc thng s chn PIN. Sau nhn chn Programer. Trong ca s Programmer mi xut hin, nhn Start bt u ti chng trnh xung thit b.

nh c thu nh .Click vo thanh ny thy nh size nguyn gc. (655 x 408)

Sau khi ti chng trnh xung, bn c th bt u kim tra mch bn thit k ngay trn thit b bng cch gt cc cng tc, nhn cc nt(ty vo bn chn)...