5

4

3

2

1

VCC
D

VCC

R2
1

T1
1

6

2
D1
TISP4C180

5

2

R5
68k

R4

Q1
2N7002

INT0

R6

C3
330n

TLV2372
U1B

100

3
470k

VCC
VCC
VQ

LS1
C6
680p
3

R9

499k
C

VCC

RELAY DPDT
R13
560

6

7
5

VCC

D8
LL4148

U2B
TLV2372

8

C7
680p

R17

200k

100k

R14
240k

C8
1n

R20

4

D5
LL4148

R12

D9
LED

VCC

42k2

3

1

14k

VQ

R19
84k5

C9
100n

Q2
2N7002

2
R18

R16
160k

8

D6
LL4148
R15
470k

4

EXT

LL4148

VCC D7
6

EXT_O
EXT
EXT_C

68k

470k

+

5

R8
R11

-

EXT_O

R10
470k

+

4
7

D4
LL4148

-

EXT_C

1
8

B

6
5

C4

100n

C

1
2
3
4
5
6
7
8

+

470k

4

2

J2

-

R3
4

D3
LL4148

8

3
C5
100n

R7
600

D2
MB2S

7
TY-145P

J1
SS-6466-NF

470k

100n

+

6
5
4
3
2
1

R1
470k

4

C2
C1
100n

-

D

C10
1n

AN3

TLV2372
U2A

VCC
B

VCC

R21

VCC

RC4

VCC

HEADER 8
VQ

+

3

-

2

R23
330
R24
470k

C11
100n

D10

4

VQ

U1A
TLV2372
1

R22
470k

8

100

VCC
J3
1
2
3

VIN 3.3VDC
A

JACK

+
D11
LL4148

D12
MMSZ4V3

C12
100u

C13
100n

A

VCC

LINE INTERFACE

VCC

TODO: Add fuse

Title
C14
100n

(c) doragasu, 2011. e-mail: doragasu@hotmail.com
Distributed under GPL v3 License (http://www.gnu.org/licenses)
5

C15
100n

BALSAMO, by doragasu
Size
A4
Date:

4

3

2

Document Number
1
Saturday, April 21, 2012

Rev
1.0
Sheet

1
1

of

2

5

4

3

2

1

VCC
VCC

VCC

C16
100n
VCC

R27 C18
15k
1u

J5
TIN

C21

1u

100n

CN22 76
CN23 77

1
2
3
4
5
6
7
8
9
10
11
12
13
14

B

SS2
SDO2

INT1
INT2
J11
INTS

1
2

SCK2

RG0
RG1

75
74
47
46
SCK2 6
SDI2
7
SDO2 8
SS2
10
79
80
78
1

SDI2
INT2

J12
I2C

1
2

1
2
3
4

J9
MICRO SD
MICRO SD PINS
===============
2: SD_STE
3: SD_SIMO
4: VCC
5: SD_CLK
6: GND
7: SD_SOMI
8: NC
9: SD_DETECT
10, 11, 12, 13, 14: GND
9: SD_DETECT

13
14
52
53

J13
DCI

VDD
VDD
VDD
VDD

C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SD1/RF7
EMUD3/SDO1/RF8

CN22/RA6
CN23/RA7
INT1/RA12
INT2/RA13
INT3/RA14
INT4/RA15
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15
dsPIC30F6014

SOSCO

RC4

RD8
RD9
RD10

OSC2

50

R42

330

C

R33
100
R34
NP

Q3
MMBF2201

1
2
INT0

C23

J10
UART2
18p

Y1
32768Hz

RX
CTS

13
8

R1IN
R2IN

U1TX
RF8

11
10

T1IN
T2IN

C22

100n 1
3
100n 4
5
100n 2
6

VCC C24
C25

C27

18p

C28

22p

Y2
C30
3.579545MHz

22p

C1+
C1C2+
C2V+
V-

C29
100n

OSC1

49

R1OUT
R2OUT

12
9

U1RX
INT1

T1OUT
T2OUT

14
7

TX
RTS
VCC
C26
100n

U4
MAX3232

B

VCC
R38
NP

SW3

R39
NP

R40
NP

R41
NP

SW4

SW5

SW6

SW7

C31
100n

C32
100n

C33
100n

C34
100n

RF0
VCC
D14

VCC

9

R36 100k

D13
330

RTS

VCC
RF7
RF0
RF1
U1RX
U1TX

R37
NP

R43

CTS

8

For use with straight cable

100k
59

7

J8
NHD-0216HZ-FSW-FBW-3V3C

72
73
42
41
39
40
45
44 RF7
43 RF8
R35
60

SOSCI

6

CN23

C20

0

1
LCD PINS
=========
TX
2
1: VSS
2: VDD
RX 3
3: VO
4: RS
4
5: R/W
6: E
5
7 - 14: DB0 - DB7
15: LED+
R28
16: LED10

VCC

CN22

R31

AVDD
AVSS
VREF-/RA9
VREF+/RA10

58
61
62
63
66
67
68
69
54
55
56
57
64
65
37
38

1
2
3
RD8
4
RD9
5
RD10
6
7
8
9
10
11
12
13
14
15
VCC
16
R32 100
R29 500

1
2
3

16

SW2
SW DIP-6
NP

EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15

2
3
4
5

VCC

VQ

R30

T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4

GND

VCC

MCLR
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15

D

J7

CN12

C

9
20
19
18
VCC
17
AN3
CN6 16
CN7 15
1
21
2
22
VQ 27
28
29
30
33
34
35
CN12 36
VCC
25
26
23
24

100n

CN7

J4
ICD_CON
J6
ANI

U3

VSS
VSS
VSS
VSS

C17
100n

MCLR
VCC
GND
PGD
PGC

11
31
51
70

1
2
3
4
5

470

12
32
48
71

D

C19

15

R26

SW1

CN6

R25
10k

C35
100n

RF1
C36

C37

C38

C39

100n

100n

100n

100n

D15

A

R44

330

R45

330

RG0

A

PROCESSOR

D16

Title

RG1

BALSAMO, by doragasu
Size
A4

(c) doragasu, 2011. e-mail: doragasu@hotmail.com
Distributed under GPL v3 License (http://www.gnu.org/licenses)
5

Date:
4

3

2

Document Number
1
Saturday, April 21, 2012

Rev
1.0
Sheet

2
1

of

2

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