RAZIKA ARSY

09632025
library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity arsy is
port (clk : in std_logic;
a,b,c,d,e,f,g : out std_logic);
attribute pin_numbers of arsy: entity is
"clk:1"
& " a:23 b:22 c:21 d:20 e:19 f:18 g:17 " ;
end entity arsy;
architecture behav of arsy is
signal q : std_logic_vector(2 downto 0);
Begin
process (clk)
begin
if clk'event and clk = '1' then
q <= q+1;
end if;
end process;
process (q)
begin
case (q) is
-- led = "6543210"
-- led = "gfedcba"
when "000" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '1'; g <= '0';
when "001" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '0'; g <= '1';
when "010" => a <= '1'; b <= '0'; c <= '0'; d <= '1'; e <= '1'; f <= '0'; g <= '0';
when "011" => a <= '0'; b <= '0'; c <= '0'; d <= '1'; e <= '0'; f <= '0'; g <= '0';
when "100" => a <= '1'; b <= '1'; c <= '0'; d <= '1'; e <= '0'; f <= '1'; g <= '0';
when "101" => a <= '1'; b <= '1'; c <= '1'; d <= '0'; e <= '0'; f <= '0'; g <= '0';
when "110" => a <= '1'; b <= '1'; c <= '0'; d <= '0'; e <= '0'; f <= '1'; g <= '0';
when others => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '0'; f <= '0'; g <= '0';
end case;
end process;
end architecture behav;