library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ---Switching matrix test program reconfiguration for all phases ; ---Switch matrix and single line testing -- File: st.vhd entity ST is port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT ); end ST; architecture str of ST is COMPONENT ST1 port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end COMPONENT; COMPONENT ST2 port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end COMPONENT; COMPONENT ST3 port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end COMPONENT;

COMPONENT ST4 port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end COMPONENT; COMPONENT ST5 port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end COMPONENT; COMPONENT ST6 port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end COMPONENT; COMPONENT COMPARATOR3 port ( A: in BIT_VECTOR (2 downto 0); B: in BIT_VECTOR (2 downto 0); Y: out BIT); end COMPONENT; COMPONENT AND3 port ( A: in BIT; B: in BIT; C: in BIT; Y: out BIT); end COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT); end COMPONENT; SIGNAL OUT1,OUT2,OUT3,OUT4,OUT5,OUT6:BIT_VECTOR(2 DOWNTO 0); SIGNAL COMP_OUT1,COMP_OUT2,COMP_OUT3:BIT;

SIGNAL TEMP :BIT; Begin ASSIGN1:ST1 PORT MAP (CK,COUNT,OUT1); ASSIGN2:ST2 PORT MAP (CK,COUNT,OUT2); ASSIGN3:ST3 PORT MAP (CK,COUNT,OUT3); ASSIGN4:ST4 PORT MAP (CK,COUNT,OUT4); ASSIGN5:ST5 PORT MAP (CK,COUNT,OUT5); ASSIGN6:ST6 PORT MAP (CK,COUNT,OUT6); COMP1:COMPARATOR3 PORT MAP(OUT1,OUT2,COMP_OUT1); COMP2:COMPARATOR3 PORT MAP(OUT3,OUT4,COMP_OUT2); COMP3:COMPARATOR3 PORT MAP(OUT5,OUT6,COMP_OUT3); NA1:AND3 PORT MAP (COMP_OUT1,COMP_OUT2,COMP_OUT3,TEMP); D1:D_FF PORT MAP (TEMP,CK,OUTPUT); --<<enter your statements here>> end str;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity AND3 is port ( A: in BIT; B: in BIT; C: in BIT; Y: out BIT); end AND3; architecture Behavioral of AND3 is begin Y <= A and B and C;

end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity COMPARATOR3 is port ( A: in BIT_VECTOR (2 downto 0); B: in BIT_VECTOR (2 downto 0); Y: out BIT); end COMPARATOR3; architecture Behavioral of COMPARATOR3 is begin p1:process(A,B) begin if A=B then Y<='0'; elsif A > B then Y<='1'; else Y<='0'; end if; end process; end Behavioral; library IEEE; --library IEEE,book_lib; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use std.textio.all; --use std.utils_pkg.all; --use std.att_mvl.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

ENTITY COUNT2 IS PORT( ck,count: IN BIT; Q:INOUT BIT_VECTOR( 1 DOWNTO 0 ) ); END COUNT2;

ARCHITECTURE behavioral OF COUNT2 IS BEGIN upcount: PROCESS( ck ) BEGIN IF( ck'event AND ck= '1' ) THEN IF count = '1' THEN Q <= "00"; ELSE Q(0) <= NOT Q(0); Q(1) <= Q(0) XOR Q(1); --Q(2) <= ( Q(0) AND Q(1) ) XOR Q(2); --Q(3) <= ( Q(0) AND Q(1) AND Q(2) ) XOR Q(3); -- IF count = "0000" THEN -- reset_alert <= '1'; -- ELSE -- reset_alert <= '0'; -- END IF; -- IF count = "0000" END IF; -- IF load = '1'

END IF; -- IF( clock'event AND clock = '1' ) END PROCESS upcount; END behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity d_ff is port ( D: in BIT; CLK: in BIT; Q: out BIT ); end d_ff; architecture Behavioral of d_ff is begin process(clk) begin if(clk'event and clk = '1') then Q <= D; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

-- File: ST1.vhd ---Switching matrix test program reconfiguration phase 1; ---Switch matrix and single line testing entity ST1 is port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end ST1; architecture AB of ST1 is COMPONENT SW port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT SW1 port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT ); END COMPONENT; COMPONENT COUNT2 port ( count: in BIT; ck: in BIT; Q: inout BIT_VECTOR (1 downto 0)); END COMPONENT;

COMPONENT NOT1 port ( A: in BIT; B: out BIT); END COMPONENT; COMPONENT XNOR2 port ( A: in BIT; B: in BIT; Q: out BIT); END COMPONENT; COMPONENT NA2 port ( I1: in BIT; I2: in BIT; O1: BUFFER BIT); END COMPONENT; --FOR X3,X6,X9:NA2 USE ENTITY WORK.NAND2(CON); --INPUT SIGNALS TO THE SWITCHES SIGNAL S1_IP,S2_IP,S3_IP,S4_IP,S5_IP,S6_IP,S7_IP,S8_IP,S9_IP:BIT_VECTOR(3 DOWNTO 0); --OUTPUT SIGNALS TO THE SWITCHES SIGNAL S1_OP_1,S1_OP_2,S1_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S2_OP_1,S2_OP_2,S2_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S3_OP_1,S3_OP_2,S3_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S4_OP_1,S4_OP_2,S4_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S5_OP_1,S5_OP_2,S5_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S6_OP_1,S6_OP_2,S6_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S7_OP_1,S7_OP_2,S7_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S8_OP_1,S8_OP_2,S8_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S9_OP_1,S9_OP_2,S9_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL T1,T2,T3,T4,T5,T6:BIT; SIGNAL OP_TEMP1,OP_TEMP2:BIT_VECTOR(2 DOWNTO 0); SIGNAL B1:INTEGER:=1; SIGNAL B2:INTEGER:=2; SIGNAL B3:INTEGER:=3; begin ASIGN1:COUNT2 PORT MAP (COUNT,CK,S1_IP(1 DOWNTO 0)); ASIGN2:COUNT2 PORT MAP (COUNT,CK,S3_IP(1 DOWNTO 0)); ASIGN3:COUNT2 PORT MAP (COUNT,CK,S4_IP(1 DOWNTO 0)); ASIGN4:COUNT2 PORT MAP (COUNT,CK,S1_IP(3 DOWNTO 2));

ASIGN5:COUNT2 PORT MAP (COUNT,CK,S3_IP(3 DOWNTO 2)); ASIGN6:COUNT2 PORT MAP (COUNT,CK,S4_IP(3 DOWNTO 2)); ---SWITCH ASSIGNMENT ---CENTER CHAIN S1:SW PORT MAP (B1,S1_IP,S1_OP_1,S1_OP_2,S1_OP_3); PROCESS (S1_OP_1,S1_OP_2,S1_OP_3) BEGIN S2_IP <= S1_OP_1; END PROCESS; S2:SW PORT MAP (B3,S2_IP,S2_OP_1,S2_OP_2,S2_OP_3); PROCESS (S2_OP_1,S2_OP_2,S2_OP_3) BEGIN S5_IP <= S2_OP_3; END PROCESS; S3:SW PORT MAP (B1,S5_IP,S5_OP_1,S5_OP_2,S5_OP_3); PROCESS (S5_OP_1,S5_OP_2,S5_OP_3) BEGIN S6_IP <= S5_OP_1; END PROCESS; S4:SW PORT MAP (B3,S6_IP,S6_OP_1,S6_OP_2,S6_OP_3); PROCESS (S6_OP_1,S6_OP_2,S6_OP_3) BEGIN S9_IP <= S6_OP_3; END PROCESS; S5:SW PORT MAP (B1,S9_IP,S9_OP_1,S9_OP_2,S9_OP_3); X1:XNOR2 PORT MAP (S9_OP_1(0),S9_OP_1(2),T1); X2:XNOR2 PORT MAP (S9_OP_1(1),S9_OP_1(3),T2); X3:NA2 PORT MAP (T1,T2,OP_TEMP1(1)); ---UPPER CHAIN S6:SW PORT MAP (B1,S3_IP,S3_OP_1,S3_OP_2,S3_OP_3); X4:XNOR2 PORT MAP (S3_OP_1(0),S3_OP_1(2),T3); X5:XNOR2 PORT MAP (S3_OP_1(1),S3_OP_1(3),T4); X6:NA2 PORT MAP (T3,T4,OP_TEMP1(0));

---LOWER CHAIN S7:SW PORT MAP (B3,S4_IP,S4_OP_1,S4_OP_2,S4_OP_3); PROCESS (S4_OP_1,S4_OP_2,S4_OP_3) BEGIN S7_IP <= S4_OP_3; END PROCESS; S8:SW PORT MAP (B1,S7_IP,S7_OP_1,S7_OP_2,S7_OP_3); PROCESS (S7_OP_1,S7_OP_2,S7_OP_3) BEGIN S8_IP <= S7_OP_1; END PROCESS; S9:SW PORT MAP (B3,S8_IP,S8_OP_1,S8_OP_2,S8_OP_3); X7:XNOR2 PORT MAP (S8_OP_3(0),S8_OP_3(2),T5); X8:XNOR2 PORT MAP (S8_OP_3(1),S8_OP_3(3),T6); X9:NA2 PORT MAP (T5,T6,OP_TEMP1(2)); N2:NOT1 PORT MAP (OP_TEMP1(0),OP_TEMP2(0)); N3:NOT1 PORT MAP (OP_TEMP1(1),OP_TEMP2(1)); N4:NOT1 PORT MAP (OP_TEMP1(2),OP_TEMP2(2)); GEN:FOR I IN 0 TO 2 GENERATE D1:D_FF PORT MAP (OP_TEMP2(I),CK,OUTPUT(I)); END GENERATE; -- <<enter your statements here>> end AB; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ---Switching matrix test program reconfiguration phase 2; ---Switch matrix and single line testing --File: ST2.vhd entity ST2 is

port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end ST2; architecture STR of ST2 is COMPONENT SW port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT SW1 port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT ); END COMPONENT; COMPONENT COUNT2 port ( count: in BIT; ck: in BIT; Q: inout BIT_VECTOR (1 downto 0)); END COMPONENT; COMPONENT NOT1 port (A: in BIT;B: out BIT); END COMPONENT; COMPONENT XNOR2 port (

A: in BIT; B: in BIT; Q: out BIT); END COMPONENT; COMPONENT NA2 port ( I1: in BIT; I2: in BIT; O1: BUFFER BIT); END COMPONENT; --FOR X3,X6,X9:NA2 USE ENTITY WORK.NAND2(CON); --INPUT SIGNALS TO THE SWITCHES SIGNAL S1_IP,S2_IP,S3_IP,S4_IP,S5_IP,S6_IP,S7_IP,S8_IP,S9_IP:BIT_VECTOR(3 DOWNTO 0); --OUTPUT SIGNALS TO THE SWITCHES SIGNAL S1_OP_1,S1_OP_2,S1_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S2_OP_1,S2_OP_2,S2_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S3_OP_1,S3_OP_2,S3_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S4_OP_1,S4_OP_2,S4_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S5_OP_1,S5_OP_2,S5_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S6_OP_1,S6_OP_2,S6_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S7_OP_1,S7_OP_2,S7_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S8_OP_1,S8_OP_2,S8_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S9_OP_1,S9_OP_2,S9_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL T1,T2,T3,T4,T5,T6:BIT; SIGNAL OP_TEMP1,OP_TEMP2:BIT_VECTOR(2 DOWNTO 0); SIGNAL B1:INTEGER:=1; SIGNAL B2:INTEGER:=2; SIGNAL B3:INTEGER:=3; Begin ASIGN1:COUNT2 PORT MAP (COUNT,CK,S1_IP(1 DOWNTO 0)); ASIGN2:COUNT2 PORT MAP (COUNT,CK,S2_IP(1 DOWNTO 0)); ASIGN3:COUNT2 PORT MAP (COUNT,CK,S7_IP(1 DOWNTO 0)); ASIGN4:COUNT2 PORT MAP (COUNT,CK,S1_IP(3 DOWNTO 2)); ASIGN5:COUNT2 PORT MAP (COUNT,CK,S2_IP(3 DOWNTO 2)); ASIGN6:COUNT2 PORT MAP (COUNT,CK,S7_IP(3 DOWNTO 2)); ---SWITCH ASSIGNMENT

---CENTER CHAIN S1:SW PORT MAP (B3,S1_IP,S1_OP_1,S1_OP_2,S1_OP_3); PROCESS (S1_OP_1,S1_OP_2,S1_OP_3) BEGIN S4_IP <= S1_OP_3; END PROCESS; S2:SW PORT MAP (B1,S4_IP,S4_OP_1,S4_OP_2,S4_OP_3); PROCESS (S4_OP_1,S4_OP_2,S4_OP_3) BEGIN S5_IP <= S4_OP_1; END PROCESS; S3:SW PORT MAP (B3,S5_IP,S5_OP_1,S5_OP_2,S5_OP_3); PROCESS (S5_OP_1,S5_OP_2,S5_OP_3) BEGIN S8_IP <= S5_OP_3; END PROCESS; S4:SW PORT MAP (B1,S8_IP,S8_OP_1,S8_OP_2,S8_OP_3); PROCESS (S8_OP_1,S8_OP_2,S8_OP_3) BEGIN S9_IP <= S8_OP_1; END PROCESS; S5:SW PORT MAP (B3,S9_IP,S9_OP_1,S9_OP_2,S9_OP_3); X1:XNOR2 PORT MAP (S9_OP_3(0),S9_OP_3(2),T1); X2:XNOR2 PORT MAP (S9_OP_3(1),S9_OP_3(3),T2); X3:NA2 PORT MAP (T1,T2,OP_TEMP1(1)); ---LOWER CHAIN S6:SW PORT MAP (B3,S7_IP,S7_OP_1,S7_OP_2,S7_OP_3); X4:XNOR2 PORT MAP (S7_OP_3(0),S7_OP_3(2),T3); X5:XNOR2 PORT MAP (S7_OP_3(1),S7_OP_3(3),T4); X6:NA2 PORT MAP (T3,T4,OP_TEMP1(2)); --- UPPER CHAIN S7:SW PORT MAP (B1,S2_IP,S2_OP_1,S2_OP_2,S2_OP_3); PROCESS (S2_OP_1,S2_OP_2,S2_OP_3) BEGIN S3_IP <= S2_OP_1;

END PROCESS; S8:SW PORT MAP (B3,S3_IP,S3_OP_1,S3_OP_2,S3_OP_3); PROCESS (S3_OP_1,S3_OP_2,S3_OP_3) BEGIN S6_IP <= S3_OP_3; END PROCESS; S9:SW PORT MAP (B1,S6_IP,S6_OP_1,S6_OP_2,S6_OP_3); X7:XNOR2 PORT MAP (S6_OP_1(0),S6_OP_1(2),T5); X8:XNOR2 PORT MAP (S6_OP_1(1),S6_OP_1(3),T6); X9:NA2 PORT MAP (T5,T6,OP_TEMP1(0)); N2:NOT1 PORT MAP (OP_TEMP1(0),OP_TEMP2(0)); N3:NOT1 PORT MAP (OP_TEMP1(1),OP_TEMP2(1)); N4:NOT1 PORT MAP (OP_TEMP1(2),OP_TEMP2(2)); GEN:FOR I IN 0 TO 2 GENERATE D1:D_FF PORT MAP (OP_TEMP2(I),CK,OUTPUT(I)); END GENERATE; -- <<enter your statements here>> end STR; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ---Switching matrix test program reconfiguration phase 3; ---Switch matrix and single line testing --File: ST3.vhd entity ST3 is port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0) ); end ST3; architecture STR of ST3 is

COMPONENT SW port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT SW1 port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT ); END COMPONENT; COMPONENT COUNT2 port ( count: in BIT; ck: in BIT; Q: inout BIT_VECTOR (1 downto 0)); END COMPONENT; COMPONENT NOT1 port ( A: in BIT; B: out BIT); END COMPONENT; COMPONENT XNOR2 port ( A: in BIT; B: in BIT; Q: out BIT); END COMPONENT; COMPONENT NA2

port ( I1: in BIT; I2: in BIT; O1: BUFFER BIT); END COMPONENT; --FOR X3,X6,X9:NA2 USE ENTITY WORK.NAND2(CON); --INPUT SIGNALS TO THE SWITCHES SIGNAL S1_IP,S2_IP,S3_IP,S4_IP,S5_IP,S6_IP,S7_IP,S8_IP,S9_IP:BIT_VECTOR(3 DOWNTO 0); --OUTPUT SIGNALS TO THE SWITCHES SIGNAL S1_OP_1,S1_OP_2,S1_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S2_OP_1,S2_OP_2,S2_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S3_OP_1,S3_OP_2,S3_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S4_OP_1,S4_OP_2,S4_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S5_OP_1,S5_OP_2,S5_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S6_OP_1,S6_OP_2,S6_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S7_OP_1,S7_OP_2,S7_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S8_OP_1,S8_OP_2,S8_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S9_OP_1,S9_OP_2,S9_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL T1,T2,T3,T4,T5,T6:BIT; SIGNAL OP_TEMP1,OP_TEMP2:BIT_VECTOR(2 DOWNTO 0); SIGNAL B1:INTEGER:=1; SIGNAL B2:INTEGER:=2; SIGNAL B3:INTEGER:=3; Begin ASIGN1:COUNT2 PORT MAP (COUNT,CK,S1_IP(1 DOWNTO 0)); ASIGN2:COUNT2 PORT MAP (COUNT,CK,S3_IP(1 DOWNTO 0)); ASIGN3:COUNT2 PORT MAP (COUNT,CK,S6_IP(1 DOWNTO 0)); ASIGN4:COUNT2 PORT MAP (COUNT,CK,S1_IP(3 DOWNTO 2)); ASIGN5:COUNT2 PORT MAP (COUNT,CK,S3_IP(3 DOWNTO 2)); ASIGN6:COUNT2 PORT MAP (COUNT,CK,S6_IP(3 DOWNTO 2)); ---SWITCH ASSIGNMENT ---CENTER CHAIN S1:SW PORT MAP (B3,S3_IP,S3_OP_1,S3_OP_2,S3_OP_3); PROCESS (S3_OP_1,S3_OP_2,S3_OP_3) BEGIN S2_IP <= S3_OP_3;

END PROCESS; S2:SW PORT MAP (B1,S2_IP,S2_OP_1,S2_OP_2,S2_OP_3); PROCESS (S2_OP_1,S2_OP_2,S2_OP_3) BEGIN S5_IP <= S2_OP_1; END PROCESS; S3:SW PORT MAP (B3,S5_IP,S5_OP_1,S5_OP_2,S5_OP_3); PROCESS (S5_OP_1,S5_OP_2,S5_OP_3) BEGIN S4_IP <= S5_OP_3; END PROCESS; S4:SW PORT MAP (B1,S4_IP,S4_OP_1,S4_OP_2,S4_OP_3); PROCESS (S4_OP_1,S4_OP_2,S4_OP_3) BEGIN S7_IP <= S4_OP_1; END PROCESS; S5:SW PORT MAP (B3,S7_IP,S7_OP_1,S7_OP_2,S7_OP_3); X1:XNOR2 PORT MAP (S7_OP_3(0),S7_OP_3(2),T1); X2:XNOR2 PORT MAP (S7_OP_3(1),S7_OP_3(3),T2); X3:NA2 PORT MAP (T1,T2,OP_TEMP1(1)); ---UPPER CHAIN S6:SW PORT MAP (B3,S1_IP,S1_OP_1,S1_OP_2,S1_OP_3); X4:XNOR2 PORT MAP (S1_OP_3(0),S1_OP_3(2),T3); X5:XNOR2 PORT MAP (S1_OP_3(1),S1_OP_3(3),T4); X6:NA2 PORT MAP (T3,T4,OP_TEMP1(0)); ---LOWER CHAIN S7:SW PORT MAP (B1,S6_IP,S6_OP_1,S6_OP_2,S6_OP_3); PROCESS (S6_OP_1,S6_OP_2,S6_OP_3) BEGIN S9_IP <= S6_OP_1; END PROCESS; S8:SW PORT MAP (B3,S9_IP,S9_OP_1,S9_OP_2,S9_OP_3); PROCESS (S9_OP_1,S9_OP_2,S9_OP_3) BEGIN S8_IP <= S9_OP_3; END PROCESS;

S9:SW PORT MAP (B1,S8_IP,S8_OP_1,S8_OP_2,S8_OP_3); X7:XNOR2 PORT MAP (S8_OP_1(0),S8_OP_1(2),T5); X8:XNOR2 PORT MAP (S8_OP_1(1),S8_OP_1(3),T6); X9:NA2 PORT MAP (T5,T6,OP_TEMP1(2)); N2:NOT1 PORT MAP (OP_TEMP1(0),OP_TEMP2(0)); N3:NOT1 PORT MAP (OP_TEMP1(1),OP_TEMP2(1)); N4:NOT1 PORT MAP (OP_TEMP1(2),OP_TEMP2(2)); GEN:FOR I IN 0 TO 2 GENERATE D1:D_FF PORT MAP (OP_TEMP2(I),CK,OUTPUT(I)); END GENERATE; -<<enter your statements here>> end STR; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; -----Switching matrix test program reconfiguration phase 4; ---Switch matrix and single line testing -- File: ST4.vhd -entity ST4 is port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end ST4; architecture STR of ST4 is COMPONENT SW port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0);

OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT SW1 port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT ); END COMPONENT; COMPONENT COUNT2 port ( count: in BIT; ck: in BIT; Q: inout BIT_VECTOR (1 downto 0)); END COMPONENT; COMPONENT NOT1 port ( A: in BIT; B: out BIT); END COMPONENT; COMPONENT XNOR2 port ( A: in BIT; B: in BIT; Q: out BIT); END COMPONENT; COMPONENT NA2 port ( I1: in BIT; I2: in BIT; O1: BUFFER BIT); END COMPONENT; --FOR X3,X6,X9:NA2 USE ENTITY WORK.NAND2(CON);

--INPUT SIGNALS TO THE SWITCHES SIGNAL S1_IP,S2_IP,S3_IP,S4_IP,S5_IP,S6_IP,S7_IP,S8_IP,S9_IP:BIT_VECTOR(3 DOWNTO 0); --OUTPUT SIGNALS TO THE SWITCHES SIGNAL S1_OP_1,S1_OP_2,S1_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S2_OP_1,S2_OP_2,S2_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S3_OP_1,S3_OP_2,S3_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S4_OP_1,S4_OP_2,S4_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S5_OP_1,S5_OP_2,S5_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S6_OP_1,S6_OP_2,S6_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S7_OP_1,S7_OP_2,S7_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S8_OP_1,S8_OP_2,S8_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S9_OP_1,S9_OP_2,S9_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL T1,T2,T3,T4,T5,T6:BIT; SIGNAL OP_TEMP1,OP_TEMP2:BIT_VECTOR(2 DOWNTO 0); SIGNAL B1:INTEGER:=1; SIGNAL B2:INTEGER:=2; SIGNAL B3:INTEGER:=3; Begin ASIGN1:COUNT2 PORT MAP (COUNT,CK,S9_IP(1 DOWNTO 0)); ASIGN2:COUNT2 PORT MAP (COUNT,CK,S2_IP(1 DOWNTO 0)); ASIGN3:COUNT2 PORT MAP (COUNT,CK,S3_IP(1 DOWNTO 0)); ASIGN4:COUNT2 PORT MAP (COUNT,CK,S9_IP(3 DOWNTO 2)); ASIGN5:COUNT2 PORT MAP (COUNT,CK,S2_IP(3 DOWNTO 2)); ASIGN6:COUNT2 PORT MAP (COUNT,CK,S3_IP(3 DOWNTO 2)); ---SWITCH ASSIGNMENT ---CENTER CHAIN S1:SW PORT MAP (B1,S3_IP,S3_OP_1,S3_OP_2,S3_OP_3); PROCESS (S3_OP_1,S3_OP_2,S3_OP_3) BEGIN S6_IP <= S3_OP_1; END PROCESS; S2:SW PORT MAP (B3,S6_IP,S6_OP_1,S6_OP_2,S6_OP_3); PROCESS (S6_OP_1,S6_OP_2,S6_OP_3) BEGIN S5_IP <= S6_OP_3; END PROCESS;

S3:SW PORT MAP (B1,S5_IP,S5_OP_1,S5_OP_2,S5_OP_3); PROCESS (S5_OP_1,S5_OP_2,S5_OP_3) BEGIN S8_IP <= S5_OP_1; END PROCESS; S4:SW PORT MAP (B3,S8_IP,S8_OP_1,S8_OP_2,S8_OP_3); PROCESS (S8_OP_1,S8_OP_2,S8_OP_3) BEGIN S7_IP <= S8_OP_3; END PROCESS; S5:SW PORT MAP (B1,S7_IP,S7_OP_1,S7_OP_2,S7_OP_3); X1:XNOR2 PORT MAP (S7_OP_1(0),S7_OP_1(2),T1); X2:XNOR2 PORT MAP (S7_OP_1(1),S7_OP_1(3),T2); X3:NA2 PORT MAP (T1,T2,OP_TEMP1(1)); ---LOWER CHAIN S6:SW PORT MAP (B1,S9_IP,S9_OP_1,S9_OP_2,S9_OP_3); X4:XNOR2 PORT MAP (S9_OP_1(0),S9_OP_1(2),T3); X5:XNOR2 PORT MAP (S9_OP_1(1),S9_OP_1(3),T4); X6:NA2 PORT MAP (T3,T4,OP_TEMP1(2)); --- UPPER CHAIN S7:SW PORT MAP (B3,S2_IP,S2_OP_1,S2_OP_2,S2_OP_3); PROCESS (S2_OP_1,S2_OP_2,S2_OP_3) BEGIN S1_IP <= S2_OP_3; END PROCESS; S8:SW PORT MAP (B1,S1_IP,S1_OP_1,S1_OP_2,S1_OP_3); PROCESS (S1_OP_1,S1_OP_2,S1_OP_3) BEGIN S4_IP <= S1_OP_1; END PROCESS; S9:SW PORT MAP (B3,S4_IP,S4_OP_1,S4_OP_2,S4_OP_3); X7:XNOR2 PORT MAP (S4_OP_3(0),S4_OP_3(2),T5); X8:XNOR2 PORT MAP (S4_OP_3(1),S4_OP_3(3),T6);

X9:NA2 PORT MAP (T5,T6,OP_TEMP1(0)); N2:NOT1 PORT MAP (OP_TEMP1(0),OP_TEMP2(0)); N3:NOT1 PORT MAP (OP_TEMP1(1),OP_TEMP2(1)); N4:NOT1 PORT MAP (OP_TEMP1(2),OP_TEMP2(2)); GEN:FOR I IN 0 TO 2 GENERATE D1:D_FF PORT MAP (OP_TEMP2(I),CK,OUTPUT(I)); END GENERATE; -- <<enter your statements here>> end STR; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ---Switching matrix test program reconfiguration phase 5; ---Switch matrix and single line testing --File: ST5.vhd entity ST5 is port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0) ); end ST5; architecture STR of ST5 IS COMPONENT SW port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT;

COMPONENT SW1 port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT ); END COMPONENT; COMPONENT COUNT2 port ( count: in BIT; ck: in BIT; Q: inout BIT_VECTOR (1 downto 0)); END COMPONENT; COMPONENT NOT1 port ( A: in BIT; B: out BIT); END COMPONENT; COMPONENT XNOR2 port ( A: in BIT; B: in BIT; Q: out BIT); END COMPONENT; COMPONENT NA2 port ( I1: in BIT; I2: in BIT; O1: BUFFER BIT); END COMPONENT; --FOR X3,X6,X9:NA2 USE ENTITY WORK.NAND2(CON); --INPUT SIGNALS TO THE SWITCHES

SIGNAL S1_IP,S2_IP,S3_IP,S4_IP,S5_IP,S6_IP,S7_IP,S8_IP,S9_IP:BIT_VECTOR(3 DOWNTO 0); --OUTPUT SIGNALS TO THE SWITCHES SIGNAL S1_OP_1,S1_OP_2,S1_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S2_OP_1,S2_OP_2,S2_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S3_OP_1,S3_OP_2,S3_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S4_OP_1,S4_OP_2,S4_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S5_OP_1,S5_OP_2,S5_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S6_OP_1,S6_OP_2,S6_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S7_OP_1,S7_OP_2,S7_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S8_OP_1,S8_OP_2,S8_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S9_OP_1,S9_OP_2,S9_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL T1,T2,T3,T4,T5,T6:BIT; SIGNAL OP_TEMP1,OP_TEMP2:BIT_VECTOR(2 DOWNTO 0); SIGNAL B1:INTEGER:=1; SIGNAL B2:INTEGER:=2; SIGNAL B3:INTEGER:=3; Begin ASIGN1:COUNT2 PORT MAP (COUNT,CK,S1_IP(1 DOWNTO 0)); ASIGN2:COUNT2 PORT MAP (COUNT,CK,S2_IP(1 DOWNTO 0)); ASIGN3:COUNT2 PORT MAP (COUNT,CK,S3_IP(1 DOWNTO 0)); ASIGN4:COUNT2 PORT MAP (COUNT,CK,S1_IP(3 DOWNTO 2)); ASIGN5:COUNT2 PORT MAP (COUNT,CK,S2_IP(3 DOWNTO 2)); ASIGN6:COUNT2 PORT MAP (COUNT,CK,S3_IP(3 DOWNTO 2)); ---SWITCH ASSIGNMENT ---LEFT CHAIN S1:SW PORT MAP (B2,S1_IP,S1_OP_1,S1_OP_2,S1_OP_3); PROCESS (S1_OP_1,S1_OP_2,S1_OP_3) BEGIN S4_IP <= S1_OP_2; END PROCESS; S2:SW PORT MAP (B2,S4_IP,S4_OP_1,S4_OP_2,S4_OP_3); PROCESS (S4_OP_1,S4_OP_2,S4_OP_3) BEGIN S7_IP <= S4_OP_2; END PROCESS; S3:SW PORT MAP (B2,S7_IP,S7_OP_1,S7_OP_2,S7_OP_3);

X1:XNOR2 PORT MAP (S7_OP_2(0),S7_OP_2(2),T1); X2:XNOR2 PORT MAP (S7_OP_2(1),S7_OP_2(3),T2); X3:NA2 PORT MAP (T1,T2,OP_TEMP1(2)); ---MIDDLE CHAIN S4:SW PORT MAP (B2,S2_IP,S2_OP_1,S2_OP_2,S2_OP_3); PROCESS (S2_OP_1,S2_OP_2,S2_OP_3) BEGIN S5_IP <= S2_OP_2; END PROCESS; S5:SW PORT MAP (B2,S5_IP,S5_OP_1,S5_OP_2,S5_OP_3); PROCESS (S5_OP_1,S5_OP_2,S5_OP_3) BEGIN S8_IP <= S5_OP_2; END PROCESS; S6:SW PORT MAP (B2,S8_IP,S8_OP_1,S8_OP_2,S8_OP_3); X4:XNOR2 PORT MAP (S8_OP_2(0),S8_OP_2(2),T3); X5:XNOR2 PORT MAP (S8_OP_2(1),S8_OP_2(3),T4); X6:NA2 PORT MAP (T3,T4,OP_TEMP1(1)); --- RIGHT CHAIN S7:SW PORT MAP (B2,S3_IP,S3_OP_1,S3_OP_2,S3_OP_3); PROCESS (S3_OP_1,S3_OP_2,S3_OP_3) BEGIN S6_IP <= S3_OP_2; END PROCESS; S8:SW PORT MAP (B2,S6_IP,S6_OP_1,S6_OP_2,S6_OP_3); PROCESS (S6_OP_1,S6_OP_2,S6_OP_3) BEGIN S9_IP <= S6_OP_2; END PROCESS; S9:SW PORT MAP (B2,S9_IP,S9_OP_1,S9_OP_2,S9_OP_3); X7:XNOR2 PORT MAP (S9_OP_2(0),S9_OP_2(2),T5); X8:XNOR2 PORT MAP (S9_OP_2(1),S9_OP_2(3),T6); X9:NA2 PORT MAP (T5,T6,OP_TEMP1(0)); N2:NOT1 PORT MAP (OP_TEMP1(0),OP_TEMP2(0)); N3:NOT1 PORT MAP (OP_TEMP1(1),OP_TEMP2(1));

N4:NOT1 PORT MAP (OP_TEMP1(2),OP_TEMP2(2)); GEN:FOR I IN 0 TO 2 GENERATE D1:D_FF PORT MAP (OP_TEMP2(I),CK,OUTPUT(I)); END GENERATE; -- <<enter your statements here>> end STR; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ---Switching matrix test program reconfiguration phase 6; ---Switch matrix and single line testing ---File: ST6.vhd entity ST6 is port ( CK: in BIT; COUNT: in BIT; OUTPUT: out BIT_VECTOR (2 downto 0)); end ST6; architecture STR of ST6 is COMPONENT SW port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0); OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT SW1 port ( VALUE: in INTEGER range 1 to 3; INPUT: in BIT_VECTOR (3 downto 0);

OUTPUT_1: inout BIT_VECTOR (3 downto 0); OUTPUT_2: inout BIT_VECTOR (3 downto 0); OUTPUT_3: inout BIT_VECTOR (3 downto 0)); END COMPONENT; COMPONENT D_FF port ( D: in BIT; CLK: in BIT; Q: out BIT ); END COMPONENT; COMPONENT COUNT2 port ( count: in BIT; ck: in BIT; Q: inout BIT_VECTOR (1 downto 0)); END COMPONENT; COMPONENT NOT1 port ( A: in BIT;B: out BIT); END COMPONENT; COMPONENT XNOR2 port ( A: in BIT; B: in BIT; Q: out BIT); END COMPONENT; COMPONENT NA2 port ( I1: in BIT; I2: in BIT; O1: BUFFER BIT); END COMPONENT; --FOR X3,X6,X9:NA2 USE ENTITY WORK.NAND2(CON); --INPUT SIGNALS TO THE SWITCHES SIGNAL S1_IP,S2_IP,S3_IP,S4_IP,S5_IP,S6_IP,S7_IP,S8_IP,S9_IP:BIT_VECTOR(3 DOWNTO 0); --OUTPUT SIGNALS TO THE SWITCHES

SIGNAL S1_OP_1,S1_OP_2,S1_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S2_OP_1,S2_OP_2,S2_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S3_OP_1,S3_OP_2,S3_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S4_OP_1,S4_OP_2,S4_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S5_OP_1,S5_OP_2,S5_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S6_OP_1,S6_OP_2,S6_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S7_OP_1,S7_OP_2,S7_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S8_OP_1,S8_OP_2,S8_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL S9_OP_1,S9_OP_2,S9_OP_3:BIT_VECTOR(3 DOWNTO 0); SIGNAL T1,T2,T3,T4,T5,T6:BIT; SIGNAL OP_TEMP1,OP_TEMP2:BIT_VECTOR(2 DOWNTO 0); SIGNAL B1:INTEGER:=1; SIGNAL B2:INTEGER:=2; SIGNAL B3:INTEGER:=3; Begin ASIGN1:COUNT2 PORT MAP (COUNT,CK,S1_IP(1 DOWNTO 0)); ASIGN2:COUNT2 PORT MAP (COUNT,CK,S4_IP(1 DOWNTO 0)); ASIGN3:COUNT2 PORT MAP (COUNT,CK,S7_IP(1 DOWNTO 0)); ASIGN4:COUNT2 PORT MAP (COUNT,CK,S1_IP(3 DOWNTO 2)); ASIGN5:COUNT2 PORT MAP (COUNT,CK,S4_IP(3 DOWNTO 2)); ASIGN6:COUNT2 PORT MAP (COUNT,CK,S7_IP(3 DOWNTO 2)); ---SWITCH ASIGNMENT ---TOP CHAIN S1:SW PORT MAP (B2,S1_IP,S1_OP_1,S1_OP_2,S1_OP_3); PROCESS (S1_OP_1,S1_OP_2,S1_OP_3) BEGIN S2_IP <= S1_OP_2; END PROCESS; S2:SW PORT MAP (B2,S2_IP,S2_OP_1,S2_OP_2,S2_OP_3); PROCESS (S2_OP_1,S2_OP_2,S2_OP_3) BEGIN S3_IP <= S2_OP_2; END PROCESS; S3:SW PORT MAP (B2,S3_IP,S3_OP_1,S3_OP_2,S3_OP_3); X1:XNOR2 PORT MAP (S3_OP_2(0),S3_OP_2(2),T1); X2:XNOR2 PORT MAP (S3_OP_2(1),S3_OP_2(3),T2); X3:NA2 PORT MAP (T1,T2,OP_TEMP1(0)); ---MIDDLE CHAIN

S4:SW PORT MAP (B2,S4_IP,S4_OP_1,S4_OP_2,S4_OP_3); PROCESS (S4_OP_1,S4_OP_2,S4_OP_3) BEGIN S5_IP <= S4_OP_2; END PROCESS; S5:SW PORT MAP (B2,S5_IP,S5_OP_1,S5_OP_2,S5_OP_3); PROCESS (S5_OP_1,S5_OP_2,S5_OP_3) BEGIN S6_IP <= S5_OP_2; END PROCESS; S6:SW PORT MAP (B2,S6_IP,S6_OP_1,S6_OP_2,S6_OP_3); X4:XNOR2 PORT MAP (S6_OP_2(0),S6_OP_2(2),T3); X5:XNOR2 PORT MAP (S6_OP_2(1),S6_OP_2(3),T4); X6:NA2 PORT MAP (T3,T4,OP_TEMP1(1)); --- BOTTOM CHAIN S7:SW PORT MAP (B2,S7_IP,S7_OP_1,S7_OP_2,S7_OP_3); PROCESS (S7_OP_1,S7_OP_2,S7_OP_3) BEGIN S8_IP <= S7_OP_2; END PROCESS; S8:SW PORT MAP (B2,S8_IP,S8_OP_1,S8_OP_2,S8_OP_3); PROCESS (S8_OP_1,S8_OP_2,S8_OP_3) BEGIN S9_IP <= S8_OP_2; END PROCESS; S9:SW PORT MAP (B2,S9_IP,S9_OP_1,S9_OP_2,S9_OP_3); X7:XNOR2 PORT MAP (S9_OP_2(0),S9_OP_2(2),T5); X8:XNOR2 PORT MAP (S9_OP_2(1),S9_OP_2(3),T6); X9:NA2 PORT MAP (T5,T6,OP_TEMP1(2)); N2:NOT1 PORT MAP (OP_TEMP1(0),OP_TEMP2(0)); N3:NOT1 PORT MAP (OP_TEMP1(1),OP_TEMP2(1)); N4:NOT1 PORT MAP (OP_TEMP1(2),OP_TEMP2(2)); GEN:FOR I IN 0 TO 2 GENERATE D1:D_FF PORT MAP (OP_TEMP2(I),CK,OUTPUT(I)); END GENERATE; --<<enter your statements here>> end STR;

Compilation report of single line faults

Single line faults RTL schematic

Simulation results for counter

Simulation results for single line (st)

Simulation results for single line (st1)