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Synthesizable Ip Core for 32|Views: 951|Likes: 2

Publicado porVarun Reddy

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https://es.scribd.com/doc/69151673/Synthesizable-Ip-Core-for-32

11/27/2012

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- 1.1Objective
- 1.2Methodology
- 1.3Conceptual Survey
- 1.4Organisation Thesis
- 2.1. Real Number System
- 2.2. Fixed-point Vs floating-point in digital signal processing
- 2.3. Floating point
- 2.4. General floating point format:
- 2.5.1Single Precision Format:
- 2.5.3. Double Precision Format:
- 2.6 Ranges of Floating-Point Numbers
- 2.7Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic:
- 2.8.1.1. Block diagram representation of floating point adder:
- 2.8.1.2. Addition of floating points using IEEE 754 format:
- 2.8.2.1. Block diagram representation of floating point subtraction:
- 2.8.2.2. Subtraction of floating points using IEEE 754 format:
- 2.8.2.3. Flow chart for floating point subtraction:
- 2.8.3.1. Multiplication using IEEE floating point standard:
- 2.8.3.2. Block diagram of floating point multiplication:
- 2.8.3.3. Flow chart for floating point multiplication
- 2.8.4.1. Block diagram for floating point division:
- 2.8.4.2 Floating point division using IEEE floating point standard
- 2.8.4.3. Flow chart for floating point division
- 2.9. Rounding Error
- 2.10. Normalization
- 2.11. Truncation
- 3.1 Floating Point Addition
- 3.2 Floating Point Subtraction
- 3.3 Floating Point Multiplication
- 3.4 Floating Point Division
- 4.1 Processor:
- 4.2 Digital Signal Processing
- 4.3. Difference between off-line processing and real time processing:
- 4.4. Architecture of digital signal processor:
- 4.5. Comparison between Fixed Point and Floating Point System:
- 4.6 Trends in DSP:
- 4.7 Accuracy of Floating Point DSP
- 5.2 IC DESIGN FLOW:
- 5.3.1 HISTORY:
- 5.3.2 CAPABILITIES
- 5.3.3 HARDWARE ABSTRACTION:
- 5.3.4 DATAFLOW STYLE OF MODELING:
- 5.3.5 BEHAVIORAL STYLE OF MODELING:
- 5.4.1. SIMULATION TOOL 5.4.1.1 Active HDL Overview:
- 5.4.2. Standards Supported
- 5.4.3 ACTIVE-HDL Macro Language:
- 5.4.4Simulation:
- 5.4.6.1 OVERVIEW OF XILINX ISE:
- 5.4.6.2 Design Entry:
- 5.4.6.3 Implementation:
- 5.4.6.4 Device Download and Program File Formatting:
- 6.1 simulation results of floating point addition
- 6.2 simulation results for floating point subtraction
- 6.3 simulation results for floating point multiplication
- 6.4 simulation results for floating point division
- 7.1 CONCLUSIONS
- 7.2 FUTURE SCOPE

TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

. DEPARTMENT OF ECE PAGE NO.-4

1: Binary Real Number System Because the size and number of registers that any computer can have is limited. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits. Figure 2. As shown at the bottom of Figure 1. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. As shown in Figure 1. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. only a subset of the real-number continuum can be used in real-number calculations.) to plus infinity (+ ).32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. the real-number system comprises the continuum of real numbers from minus infinity (. .-5 . The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers.1. DEPARTMENT OF ECE PAGE NO.

performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. Balancing these factors together. some specific assumption is made about where the radix point is located in the string. designers can identify the DSP that is best suited for an application. Software programmable for maximum flexibility and supported by easy-touse. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. the signed fraction format allows . the stored number can take on any integer value from 0 to 65. fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices.535. the 65. In fixed-point systems. DEPARTMENT OF ECE PAGE NO. low-cost development tools. Among the key factors to consider are the computational capabilities required for the application.-6 . Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic.768 to 32. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. although a different length can be used. while floating-point DSPs support either integer or real arithmetic. and ease of development. Lastly. but decimal fixed point is common in commercial applications. With unsigned fraction notation.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. DSPs enable designers to build innovative features and differentiating value into their products. In unsigned integer. 2. Fixed-point Vs floating-point in digital signal processing Fig 2. from -32. the digit string can be of any length. processor and system costs.2. In common mathematical notation. Fixed point DSPs usually represent each number with a minimum of 16 bits.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data.767. performance attributes.536 levels are spread uniformly between 0 and 1. the number is an integer). The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic.536 possible bit patterns can represent a number. Similarly. Digital Signal Processing can be divided into two categories. For instance. Motorola manufactures a family of fixed point DSPs that use 24 bits. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. There are four common ways that these 216 ' 65. signed integer uses two's complement to make the range include negative numbers.

" rather than just "Floating Point.3.In comparison. respectively. the SHARC devices are often referred to as "32-bit DSPs. but small gaps between small numbers.296 to be exact. The represented values are unequally spaced between these two extremes.754-1985). These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. equally spaced between -1 and 1. it depends on the internal architecture.967. All floating point DSPs can also handle fixed point numbers. The radix point is not explicitly included. It is measured in” FLOPS”. loops.-7 . the largest and smallest numbers are ±3. This results in many more bit patterns than for fixed point.294. it can be placed anywhere relative to the significant digits of the number. DEPARTMENT OF ECE PAGE NO.4. 2. a necessity to implement counters.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. The term” floating point” refers to the fact that the radix point can "float". but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. and executes them with equal efficiency. This position is indicated separately in the internal representation. which is capable of representing real and decimal numbers. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. and floating-point representation can thus be thought of as a computer realization of scientific notation. Floating point A floating-point number is the one. This is known as the significand. For this reason.However. The floating-point operations are incorporated into the design as functions. and signals coming from the ADC and going to the DAC.4 ×1038 and ±1. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. The logic for these is different from the ordinary arithmetic functions. For instance. or sometimes the mantissa (see below) or coefficient. 2324. A key feature of floating point notation is that the represented numbers are not uniformly spaced. that is. the SHARC DSPs are optimized for both floating point and fixed point operations. This is important because it places large gaps between large numbers. floating point DSPs typically use a minimum of 32 bits to store each value. The speed of floating-point operations is an important measure of performance for computers in many application domains. In the most common format (ANSI/IEEE Std." 2.2 ×1038.

also referred to as the characteristic or scale. DEPARTMENT OF ECE PAGE NO. These differed in the word sizes. with an average error of about 3%. These differing systems implemented different parts of the arithmetic in hardware and software. Prior to the IEEE-754 standard. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. 2. The floating-point format needs slightly more storage (to encode the position of the radix point). Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. 10 or 16. Symbolically. A signed integer exponent. or to the right of the rightmost digit. and the rounding behaviour of operations. so when stored in the same space. Significand is a real number. floating-point numbers achieve their greater range at the expense of precision. 1 for negative values. composed as integer. this final value is where s is the value of the significand (after taking into account the implied radix point).-8 . equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. (This is because the exponent field is in .32-BIT FLOATING POINT PROCESSOR TEC significant digit. which modifies the magnitude of the number.5. The significand is multiplied by the base raised to the power of the exponent. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. the format of the representations. and e is the exponent.Fraction. computers used many different forms of floating-point. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. b is the base. The length of the significand determines the precision to which numbers can be represented.

or 1023 plus the true exponent for double precision.) This can be exploited in some applications. The exponent field contains 127 plus the true exponent for single-precision.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. The first bit of the mantissa is typically assumed to be 1. to sum up: 1. 3. The Mantissa: The mantissa. and the mantissa. where f is the field of fraction bits. Flipping the value of this bit flips the sign of the number. The Sign Bit: The sign bit is as simple as it gets. 1 denotes a negative number. It is composed of an implicit leading bit and the fraction bits.-9 . even though there are infinitely many real numbers (even between 0 and 1).f. The sign bit is 0 for positive. IEEE-754 specifies binary representations for floating point numbers: Table 2.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. To do this. A float is represented using 32 bits. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. 4. There are many formats that are used for representation of floating point number. The exponent's base is two. 0 denotes a positive number. This means that at most 232 possible real numbers can be exactly represented. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. The Exponent: The exponent field needs to represent both positive and negative exponents. the exponent. and each possible combination of bits represents one real number. 1 for negative. such as volume ramping in digital sound processing. also known as the significand. a bias is added to the actual exponent in order to get the stored exponent. represents the precision bits of the number. 2. So. DEPARTMENT OF ECE .

S. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. which may be represented as numbered from 0 to 31. left to right.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2. then V=-Infinity If E=255 and F is zero and S is 0. then V=Infinity . exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude.5. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010). The number of bits for each field are shown (bit ranges are in square brackets): Table 2.5.5. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0).1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. 'E'.-10 . the next eight bits are the exponent bits. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. Table 2.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. DEPARTMENT OF ECE PAGE NO. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero.

then V=0 In particular. then V=(-1)**S * 2 ** (-126) * (0.101 = 6.F) where "1. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0. If E=0 and F is nonzero.-11 .3125 The biased exponent is -2+127=125= (01111101 • 1. then V=-0 If E=0 and F is zero and S is 0.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.101 = -6. DEPARTMENT OF ECE PAGE NO.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.0 The biased exponent is .F) These are "unnormalized" values. If E=0 and F is zero and S is 1.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.

40625 × 2 = 0.32-BIT FLOATING POINT PROCESSOR TEC • 37.1015625 × 2 = 0.203125 0.01012.8125 .0 0 1 0 1 1313.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0. = 1.5 The based exponent: 127+5= (10000100 .203125 × 2 = 0.1015625 0.010010000101012 × 210. DEPARTMENT OF ECE PAGE NO.3125 131310 = 101001000012 0.25 The biased exponent: 127+6=133=(10000101 • -1313. sign bit is 1.3125 0. • -78. .625 × 2 = 1.25 0.625 0.3125 is • 0.312510 = 10100100001.-12 . 10 + 127 = 137 = 100010012.40625 0. So -1313.5 × 2 = 1.8125 × 2 = 1.25 × 2 = 0.5 × 2 = 0.

0 1 0.3. left to right. 'E'. which may be represented as numbered from 0 to 63. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.25 0.32-BIT FLOATING POINT PROCESSOR 0.625 0.5.5 × 2 = 1. S.-13 .1015625 is 0 00111101 110100000000000000000000 TEC 2. DEPARTMENT OF ECE .3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.00011012 = 1.5 0 × 2 = 1.101562510 = 0.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001). the next eleven bits are the exponent bits. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0).25 1 × 2 = 0. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. then V=NaN ("Not a number") PAGE NO.5. The first bit is the sign bit. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.

32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. then V=(-1)**S * 2 ** (-1022) * (0. then V=-0 If E=0 and F is zero and S is 0. using a fixed number of digits. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1. 15 exponent bits and 112 significand bits. floating-point notation allows calculations over a wide range of magnitudes. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision. then V=-Infinity If E=2047 and F is zero and S is 0.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). while maintaining good precision.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. Table 2.-14 .5.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit .6.F) where "1.53 ~ 10308. . DEPARTMENT OF ECE PAGE NO. If E=0 and F is nonzero. If E=0 and F is zero and S is 1.F) These are "unnormalized" values.

53 ~10-323. P. There is a smallest positive normalized floating-point number.6. L. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand. Positive numbers less than 2-149 (positive underflow) . U) (where B is the base of the system.85 to ~1038. The number of normalized floating point numbers in a system F(B. P is the precision of the system to P numbers. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2. L is the smallest exponent represent able in the system. and the smallest possible value for the exponent.32-BIT FLOATING POINT PROCESSOR TEC Table 2. There is a largest floating point number. Zero 4. Normalized And Approximate Decimal Values. DEPARTMENT OF ECE PAGE NO.-15 . Approximate Decimal 2127 21023 ~10-44.3 to ~10308. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1).2: Effective Range of IEEE Floating Point Number with Denormalized.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. the range for negative numbers is given by the negation of the above values. Negative numbers greater than -2-149 (negative underflow) 3. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent.

If M = 0. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. When this occurs. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . However the CPU will have to perform extra arithmetic to read the number when stored in this format. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately.infinity.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . the number is exactly zero. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. DEPARTMENT OF ECE PAGE NO.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput.-16 . Recently. When this occurs.32-BIT FLOATING POINT PROCESSOR 5. Underflow occurs when the sum of the exponents is more negative than -126. the exponent is set to -127 (E = 0). 2. Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. the largest value which is defined in bias-127 exponent representation. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. the most negative value which is defined in bias-127 exponent representation. 2.

Multiplication 4.25x and b= 1. Hence the value of number ‘a’ becomes 0.. let us consider two numbers a= 2. Normalize the result.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. i. For example. Now as both the exponent values are same.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.e.0225x .8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. Division 2.-17 . Floating point addition is analogous to addition using scientific notation. DEPARTMENT OF ECE PAGE NO. both the numbers are added.1. .. Add the numbers with decimal points aligned.8. Addition 2. But by using floating point addition this can be avoided to a little extent. as the smaller number here is a=2. They are: 1. Subtraction 3.

then the following result may occur: 1.876543x and if the addition has to be performed. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value. then sign of greater number is considered.8.1.234567x and b= 9.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.-18 .2345670 x in which the remaining part (9876543) which is discarded also carries the result.234567x b= 0. signB as sign of number B.876543x after shifting becomes b= 0.. i. But the normalised result may sometimes carry the required result. ExpB as exponent of number B and ManB as mantissa of number B.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. If the numbers are represented with both positive and negative sign.e. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. then bit 1 is represented for sign.2. ExpA as exponent of number A . Now both the numbers are added. The mantissa of both numbers A and B are added. b= 9. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. Consider a example in which a =1.e. DEPARTMENT OF ECE PAGE NO.. ManA as mantissa of number A. 2.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .1.1. 2.1.00000009876543 x c= 1.8.8. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: . Thus this case can said to be having rounding errors. a =1.00000009876543 x 2.

2. Firstly. 5. If not. Thus. 6. If there is an underflow or overflow. 4. the numbers are represented in IEEE floating point format. If the exponents are stored in biased form.-19 . DEPARTMENT OF ECE PAGE NO. the exponent sum would have doubled the bias. the bias value must be subtracted from the sum 3. Addition of significands is done. 1.1.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2.8.2: Flow Chart for Floating Point Adder. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. . the significand is rounded to the appropriate number of bits required and again normalization is checked. exception is made. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.

25x and 1. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. Consider addition of the numbers 2.-20 . DEPARTMENT OF ECE PAGE NO.25 in IEEE Floating Point Standard is: The number 134. the result is converted back to signmagnitude form. The mantissa is always less than 2.25 becomes: The mantissas are added using integer addition: The result is already in normal form. If the sum overflows the position of the hidden bit.0625 in IEEE Floating Point Standard is: To align the binary points.32-BIT FLOATING POINT PROCESSOR TEC 7.2. Normalization in this case may require shifting by the total number of bits in the mantissa. Subtraction . resulting in a large loss of accuracy. Negative mantissas are handled by first converting to 2's complement and then performing the addition. After the addition is performed. cancellation may occur. The number 2.8. 2. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. resulting in a sum which is arbitrarily small. When adding numbers of opposite sign. so the hidden bits can sum to no more than 3 (11).340625x . Thus. then the mantissa must be shifted one bit to the right and the exponent incremented. or even zero if the numbers are equal in magnitude. 2.

if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if . The mantissa of both numbers A and B are subtracted.8.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. DEPARTMENT OF ECE PAGE NO.. i. The normalised result may contain the required number of digits discarding the unwanted part.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2. Subtract the numbers with decimal points aligned.. ExpA as exponent of number A .e.2. ManA as mantissa of number A.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.-21 .340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal. as the smaller number here is a=2. ExpB as exponent of number B and ManB as mantissa of number B. then sign is represented according to the number i..1. Now as both the exponent values are same. 2.e. Hence the value of number ‘a’ becomes 0. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.25x and b= 1.2. signB as sign of number B.8.1. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2. Normalize the result. both the numbers are added.0225x .

32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. DEPARTMENT OF ECE PAGE NO. If there is an underflow or overflow. Thus.-22 . The number 2.8.0625 in IEEE Floating Point Standard is: To align the binary points. the bias value must be subtracted from the sum 3. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. Consider subtraction of the numbers 2. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.25 in IEEE Floating Point Standard is: The number 134.2. exception is made. 6. Subtraction of significands is done.25x and 1.340625x .25 become: The mantissas are subtracted using integer subtraction: . the exponent sum would have doubled the bias. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 2. The numbers are represented in IEEE floating point format. If not. If the exponents are stored in biased form.2. 4. 5. Thus. 2. 2. the significand is rounded to the appropriate number of bits required and again normalization is checked.

then the significands of numbers X and Y are subtracted. If not then the result is normalized.e. If the sum overflows the position of the hidden bit.-23 . Z=Y. then the mantissa must be shifted one bit to the right and the exponent incremented. At this point. 2. If both the numbers X and Y are non zeros. then the following steps can be followed: Exponents of both the numbers are checked. If overflow occurs. If the significand is zero then it is returned if not significand overflow is checked. then number Y is checked. DEPARTMENT OF ECE PAGE NO. number X is checked.8. If it is ‘0’.2.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. If it is ‘0’ then the resultant solution Z would be Y i.8. In the first step. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. If number X is not ‘0’. then the result would be Z=X. If the exponents are same.2..3. If overflow occurred then overflow is reported and returned. Flow chart for floating point subtraction: Subtract significand si Fig 2. consider two numbers X and Y and the resultant be Z.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent .

-24 .10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers. 2.8 x 9. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.3. 2.8x times 9. If underflow occurred then it is reported if not the normalized result is given out.3. to multiply 1.8. if the significand is not zero then subtraction and further process is carried out. For example.1. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.5 ----17.5 in IEEE FPS format is: .32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked. If the exponents are not same.8.0 in IEEE FPS format is: The number 9. DEPARTMENT OF ECE PAGE NO.5x : Perform unsigned integer multiplication of the mantissas. 1. The number 18. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z.

-25 . Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form. If the position of the hidden bit overflows. When the fields are assembled in IEEE FPS format. Block diagram of floating point multiplication: . the mantissa must be shifted right and the exponent incremented. the result is: 2. the mantissa is: The biased-127 exponents are added.2. The sign of the result is the xor of the sign bits of the two numbers.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in ().8. DEPARTMENT OF ECE PAGE NO.3.

expA as exponent of number A . Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero.8. The exponents of both the numbers are added and subtracted from the bias 127.3. The mantissa of both numbers A and B are multiplied. Thus. Resultant mantissa is truncated and normalized to fit for the IEEE format. the exponent sum would have doubled the bias.-26 .8. XOR operation for sign bit can be given as follows: Table 2. expB as exponent of number B and manB as mantissa of number B.3. manA as mantissa of number A. Sign of the result is given by performing xor operation of signA and signB. then the exponents are added and a bias of 127 is subtracted from the result. At the first step.3. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. If both the numbers X and Y are not zero. If the exponents are stored in biased form.8. DEPARTMENT OF ECE PAGE NO.3. .2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. signB as sign of number B.

in general floating point division the exponents of both the numbers are subtracted and the significands are divided.8.5.3. 2.2 .e.3: Flow Chart For Floating Point Multiplication..5. The resultant sign bit would be the xor operation of sign bits of X and Y. Exponent of a is 2 and exponent of b is 3. Hence the result can be given as 1.3 0.8. So resultant exponent would be 2-3=-1.3 and b= 0. .32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned. DEPARTMENT OF ECE PAGE NO. When the division of both significands are done then the quotient would be 1. Division Consider an example of dividing a=0. i. 0. Fig 2.2 =1.4.-27 .5 .

-28 . If both the numbers are either positive or negative. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement.8. When divided by a 24 bit divisor. As in floating point multiplication. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. ManA as mantissa of number A.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .32-BIT FLOATING POINT PROCESSOR TEC 2.4. In the first step. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend.4. Normalize the result.4.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. The exponents are subtracted and biased using the bias value. Subtract the exponent of the divisor from the exponent of the dividend. Special . a 24 bit quotient is produced. The mantissa of both numbers A and B are divided. then the result is also negative is represented by bit ‘1’. then the resultant sign is also positive and is represented by bit ‘0’. DEPARTMENT OF ECE PAGE NO. 2. If anyone number of the two are negative. ExpA as exponent of number A .8. Set the sign of the result. signB as sign of number B.1. ExpB as exponent of number B and ManB as mantissa of number B.8. Block diagram for floating point division: Fig 2.

Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . For this. Considering a=0. 2.4. This value is called Not A Number. DEPARTMENT OF ECE PAGE NO. or NaN.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. . Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. Number X and Y are checked. in this case as larger number has to be subtracted from smaller number. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .2 can be represented as M 010000001(0)11000000000000000000000 0.3 0. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked.-29 .3 S E and b= 0. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2.Then the steps that occur are: 1.3.8. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.

Rounding Error In floating point arithmetic. this may be designated as +∞ or -∞..8. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit.4. rounding errors occur as a result of the limited precision of the mantissa . If not the mantissas are divided and truncated and normalized result is given out.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. DEPARTMENT OF ECE PAGE NO.-30 . digits may flow off the right end of the significand. 2. .9. Fig 2.g. In some systems. then those conditions are reported.This means that the number is too small to be represented. some form of rounding is required. and it may be reported as 0.127). If they are present. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e.200 is less than .32-BIT FLOATING POINT PROCESSOR TEC 3. • Significand underflow: In the process of aligning significands. As we shall discuss.

Same as truncation in sign-magnitude. For normalized floating point numbers. The least significant 24 bits are discarded. Same as truncation in 2's complement.10. To efficiently use the bits available for the significand. RN is generally preferred and introduces less systematic error than the other rules. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. The size of the absolute error is proportional to the magnitude of the number.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits.-31 . RP: Round toward Positive infinity. However. . relative errors increase as the magnitude of the number decreases toward zero. Normalization By normalization. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. highest precision can be achieved. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. RM: Round toward minus infinity. the relative error is approximately since For denormalized numbers (E = 0). DEPARTMENT OF ECE PAGE NO. For numbers in IEEE FPS format. Break ties by choosing the least significant bit = 0. RZ: Round toward Zero. The value can be kept unchanged by adjusting the exponent accordingly.

all extra bits during operation (called guard bits) are kept (e.11. a 4-bit exponent field and a 9-bit significand field): 2.. as the MSB of the significand is always 1.32-BIT FLOATING POINT PROCESSOR TEC Moreover. bits are used in final representation of a bits by one of the three methods. If we assume number. The first bit 1 before the decimal point is implicit. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. extra guard bits are kept during operation. to avoid possible confusion. Truncation To retain maximum accuracy. in the following the default normalization does not assume this implicit 1 unless otherwise specified.g. DEPARTMENT OF ECE PAGE NO. By the end of the operation.-32 . Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. it does not need to be shown explicitly. the bits need to be truncated to guard bit Chopping: simply drop all . resulting 1. multiplication). The actual value represented is However. Zero is represented by all 0's and is not (and cannot be) normalized.

-33 .e. otherwise do nothing. DEPARTMENT OF ECE PAGE NO. Two worst cases Both two cases can be summarized as i. 3. add 1 to LSB . Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. . . we say this truncation error is biased. the Von Neumann rounding error is unbiased.5 round up.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. Interpretation: Value represented by guard bits is greater than 0.. is always greater than 0. (no matter Von Neumann Rounding: If at least one of the guard bits is 1. set whether it is originally 0 or 1).

The rounding error of these cases can summarized as .5 either up or down with equal probability (50%). c) If the highest guard bit is 1 and the rest guard bits are all 0. DEPARTMENT OF ECE PAGE NO.5 round down. . drop all guard bits.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0. the rounding depends on the LSB : if . round up: Interpretation: Value represented by guard bits is 0. Interpretation: Value represented by guard bits is smaller than 0.-34 . round down: or if . it is randomly rounded .

the sign of the floating point number. Therefore zero is represented by 0111. the exponent obtained by balancing operations is added to 0111.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . The next eight bits are that of the exponent. The exponent in this IEEE standard is represented in excess-127 format.e. The logic for floating point addition. 1985 floating point standard representation before any sort of operations are conducted on them.e. The floating-point operations are incorporated into the design as functions.3 Floating Point Functions A floating-point number is the one. which is capable of representing real and decimal numbers. multiplication and division is presented in the following pages. DEPARTMENT OF ECE PAGE NO. 1111. The logic for these is different from the ordinary arithmetic functions. The above representation is the IEEE-784 1985 standard representation. The MSB is the sign-bit i. 1111. The numbers in contention have to be first converted into the standard IEEE 784. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number.-35 . . subtraction. I. 1111 and negative numbers are represented by binary values less than it. Positive numbers are represented by binary values greater than 0111.

1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. we have to first normalize their exponents.32-BIT FLOATING POINT PROCESSOR TEC 3. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. These numbers are distinct. • • . Once the exponents are normalized. DEPARTMENT OF ECE PAGE NO. These numbers are stored into the memory from which they are read and processed. namely Accumulator and the Temp register that loads the value appearing on the data bus. This is done till the lower exponent becomes equal to the higher one.-36 . So. The mantissas are then added to each other and the result is then stored in a temporary register. Now the numbers from the memory are loaded into two registers. So to add their mantissa’s.

So to add their mantissa’s. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. Once the exponents are normalized. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. we have to first normalize their exponents. .-37 . we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. namely Accumulator and the Temp register that loads the value appearing on the data bus. Now the numbers from the memory are loaded into two registers.32-BIT FLOATING POINT PROCESSOR 3. These numbers are stored into the memory from which they are read and processed.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. DEPARTMENT OF ECE PAGE NO. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. So. The mantissas are then subtracted and the result is stored in a temporary register. These numbers are distinct. This is done till the lower exponent becomes equal to the higher one.

The final output is obtained by concatenating the product of the mantissas. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. so that the result is restricted to not more than 24-bits. DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized.-38 . There is however a limitation to this operation. So each input should not exceed 12-bits in length. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. • • • .32-BIT FLOATING POINT PROCESSOR TEC 3. the resulting exponent and the sign of the result that is calculated separately.

4 Floating Point Division • • • • This is more complicated then Multiplication. till the quotient is full. The convention here is that the Numerator should be always less than the denominator. • • • • • . This is to ensure that whatever comes as the result is after the decimal point. We initiate a counter and carry this process for 24 times. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. The decimal is assumed to be before the MSB of the resulting quotient. Once the quotient is full. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits.-39 . If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. Apart from that the final sign of the division is calculated separately. And if it is zero.32-BIT FLOATING POINT PROCESSOR TEC 3. we put a zero in the quotient. we append it with the exponent value and the Sign of the division that are calculated separately. Now the first 24-bits from the MSB are compared with the divisor. The result is stored in Temp. Now since the greater of the two numbers is decided. First the exponents are directly added or subtracted depending on which is bigger. DEPARTMENT OF ECE PAGE NO. if the MSB or the 49th bit is one than we add a one in the quotient. Now both the numbers in the IEEE-784 standard format are compared. The logic for floating point division is as follows.

the program moves the data from . All microprocessors can perform both tasks. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. such as the size of the instruction set and how it interrupts are handled. 32 or 64 bits called registers. These devices have seen tremendous growth in the last decade. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. and so on. product life time.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. consider a word processing program. finding use in everything from cellular telephones to advanced scientific instruments. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). Clock frequency is generally a multiple of the system frequency.-40 . engineering and digital signal processing. A<B . The basic task is to store the information. Mathematical calculation used in science. Data manipulations involve storing and sorting information. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. There are technical tradeoffs in the hardware design.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. however it is difficult or expensive to make a device that is optimized for both.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. These tasks are accomplished by moving data from one location to another. For instance. corresponds to the number of pulses per second. 16. DSPs can perform the mathematical calculations needed in digital signal processing. the processor performs an action that corresponds to an instruction or a part thereof. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. 4. DEPARTMENT OF ECE PAGE NO. Computers are extremely capable in two broad areas 1. When this code is detected. Consider another example of how a document is printed from a word processor. Depending on the type of processor. written in Hertz (Hz). the overall number of registers can vary from about ten to many hundreds. meaning a multiple of the motherboard frequency. The clock speed (also called cycle). data is temporarily stored in small. and testing for inequalities (A=B. With each clock peak. Data manipulation such as word processing and database management 2. competitive position. When the processor executes instructions. local memory locations of 8. There are marketing issues involved: development and manufacturing cost. etc). DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing.

An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: .. y[n]. DEPARTMENT OF ECE PAGE NO.-41 . While mathematics is occasionally used in this type of application. consider the implementation of an FIR digital filter. such as to keep track of the intermediate results and control the loops.. This is simply saying that the input signal has been convolved with a filter kernel consisting of: .. . depending on the application. the most common DSP technique.. it is infrequent and does not significantly affect the overall execution speed.e. In comparison. Using standard notation. The task is to calculate the sample at location n in the output signal..32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. the math operations dominate the execution time... For example.. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. the input signal is referred to by x [ ]. there may only be a few coefficients in the filter kernel... i. while the output signal is denoted by y [ ]. While there is some data transfer and inequality evaluation in this algorithm...

After shaking is over. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. In these cases a 16-bit processor may suffice. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. In addition to performing mathematical calculations very rapidly. the DSP must be able to maintain a sustained throughput of 20.. 4. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers.. However. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. Also. a geophysicist might use a seismometer to record the ground movement during the earthquake.000 samples per second.. design difficulty and so on. Hence execution time is critical for selecting the proper device. Off-line processing is a realm of personal computers and mainframes. each sample in the output signal . the information may be read into a computer and analysed in some way. whereas 32-bit processors are naturally suited to the size of the data elements. DEPARTMENT OF ECE PAGE NO.2. The disadvantages of 32-bit processors are cost and system complexity.. as well as the algorithms that can be applied. say.x[n-1].x[n-2]. with the advent of very fast floating point processing hardware. the traditional speed advantage of integer operations over floating point operations is decreasing. the entire input signal resides in the computer at the same time. consider a designing of an audio signal in DSP system such as a hearing aid. There are a few reasons for why to not to make it faster than necessary because as speed increases. The key point in off-line processing is that all of the information is simultaneously available to the processing program. most DSPs are used in applications where the processing is continuous. .-42 . and to support code written in high level languages. x[n].y[n]. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. You simply wait for the action to be completed before you give the computer its next assignment In comparison.1: Graphical representation of FIR digital filter design.by the filter kernel coefficients. This is common in scientific research and engineering. power consumption. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. DSPs must also have a predictable execution time. Floating point calculations also require a 32-bit processor for good efficiency. so as the cost . floating point math must often be used to reduce the cost of programming a project.32-BIT FLOATING POINT PROCESSOR TEC Fig4. converting a word processing document from one form to another. There is less room on-chip for extra features such as hardware multipliers. . Difference between off-line processing and real time processing: In off-line processing.. If the digital signal is being received at 20. For example.000 samples per second. but these items will appear as chip fabrication technology gets denser. In FIR filtering . Digital signal processors are designed to quickly carry out FIR filters and similar techniques. If suppose you are launching your desktop computer on some task .3. For instance. is found by multiplying samples from the input signal. and summing the products. not having a defined start or end.

Super Harvard Architecture (SHARC). the output signal is produced at the same time that the input signal is acquired. Real time applications input a sample. two areas are important enough to be included are an instruction cache. For example. DEPARTMENT OF ECE PAGE NO. we start by relocating part of the "data" to program memory. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. Most of the computers are using this architecture today. at a 40 MHz clock speed. The SHARC DSPs provides both serial and parallel communications ports. This is the world of digital signal processors. For instance. program instructions and data can be fetched at the same time. improving the speed over the single bus design. 4. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. Likewise. over and over. These are extremely high speed connections. two binary values (the numbers) must be passed over the data memory bus. While the SHARC DSPs are optimized in dozens of ways. Alternatively. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). such as samples from the input signal and filter coefficients as well as program instructions. To improve upon this situation. Most present day DSPs use this dual bus architecture. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. When all six parallel ports are used together. while six parallel ports each provide a 40 Mbytes/second data transfer.4. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. perform the algorithm and output a sample. Different architectures available are: Von Neumann Architecture. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory.-43 . When two numbers are multiplied. the binary codes that go into the program sequencer. For instance. while keeping the input signal in data memory. This includes data. the data transfer rate is an incredible 240Mbytes/second.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. Harvard architecture has separate memories for data and program instructions. they may input a group of samples perform the algorithm and output a group of samples. we might place the filter coefficients in program memory. . Harvard Architecture. and an I/O controller. For example. there are two serial ports that operate at 40 Mbits/second each. this is needed in telephone communication. with separate buses for each. The basis of Harvard design is that the data memory bus is busier than the program memory bus. hearing aids and radar. Since the buses operate independently. while only one binary value (the program instruction) is passed over the program memory bus.

providing higher speed. This is a small memory that contains about 32 of the most recent program instructions. This allows .4. In comparison. the program instructions must be passed over the program memory bus. the Harvard architecture uses separate memories for data and instructions. providing an additional interface to off-chip memory and peripherals. In the jargon of the field. the program instructions can be pulled from the instruction cache. such as instructions.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. Some DSPs have on-board analog-to-digital and digital-toanalog converters. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. However. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. DEPARTMENT OF ECE PAGE NO. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. and the program instruction comes from the instruction cache.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. this efficient transfer of data is called a high memory-access bandwidth. However. This means that the same set of program instructions will continually pass from program memory to the CPU. a feature called mixed signal. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. on additional executions of the loop. all DSPs can interface with external converters through serial or parallel ports. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. The first time through a loop. DSP algorithms generally spend most of their execution time in loops.-44 . the coefficient comes over the program memory bus.

Digital Signal Processors are designed to implement tasks in parallel. In simpler microprocessors this task is handled as an inherent part of the program sequencer. OR. absolute value. The ALU performs addition. data from registers 8-15 can be passed to the ALU. for 32 bit data. The math processing is broken into three sections. conversion between fixed and floating point formats. DEPARTMENT OF ECE PAGE NO. At the top of the diagram are two blocks labelled Data Address Generator (DAG). and similar functions.2: Typical DSP architecture. and so on. This simplified diagram is of the Analog Devices SHARC DSP. In a single clock cycle. accessible at 40Mwords/second (160 Mbytes/second). and places the result into another register. rotating.4. multiplies them. subtraction. specifying where the information is to be read from or written to. data from registers 0-7 can be passed to the multiplier. Fig 4. logical operations (AND. Elementary binary operations are carried out by the barrel shifter. .32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. a multiplier. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. NOT). extracting and depositing segments. one for each of the two memories. These control the addresses sent to the program and data memories. such as shifting. and the two results returned to any of the 16 registers. All of the steps within the loop can be executed in a single clock cycle. XOR.-45 . Compare this architecture with the tasks needed to implement an FIR filter. an arithmetic logic unit (ALU). The multiplier takes the values from two registers. and is quite transparent to the programmer. and a barrel shifter.

By contrast. DEPARTMENT OF ECE PAGE NO. a result of the hardware being highly optimized for math operations. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. the latter normalized in the form of scientific notation. and an 8-bit exponent. since the programmer doesn’t generally need to worry about issues such as overflow. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. a necessity to implement counters. the instruction set must be larger and so on. While fixed-point DSP hardware performs strictly integer arithmetic. Comparison between Fixed Point and Floating Point System: TEC Both fixed.5. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent.and floating-point indicate. In addition. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). As the terms fixed. TMS320C64x™ DSPs. Fixed point DSPs are cheaper than floating point devices. The internal architecture of a floating point device is more complicated than for a fixed point device.or floating-point decision in the past. . the multiplier and ALU must be able to quickly perform floating point arithmetic. and signals coming from the ADC and going to the DAC. floating point programs often have a shorter development cycle. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. with architectures designed for handheld and control applications. However. including a 53-bit mantissa and an 11-bit exponent). TMS320C5x™ and TMS320C2x™ DSPs. For this reason. underflow and round-off." rather than just “Floating Point. All the registers and data buses must be 32 bits wide instead of only 16." fixed point arithmetic is much faster than floating point in general purpose computers. are based on single16-bit data paths. the SHARC devices are often referred to as "32-bit DSPs. All floating point DSPs can also handle fixed point numbers. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. though.-46 . thus supporting a vastly greater dynamic range than is available with the fixedpoint format.For instance. since it requires multiple cycles for each operation. with DSPs the speed is about the same. Today. Double-width precision achieves much greater precision and dynamic range at the expense of speed. loops. respectively. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. However. Tradeoffs of cost and ease of use often heavily influenced the fixed. it depends on the internal architecture . the SHARC DSPs are optimized for both floating point and fixed point operations. and executes them with equal efficiency. floating-point DSPs support either integer or real arithmetic.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing.32-BIT FLOATING POINT PROCESSOR 4.

32-BIT FLOATING POINT PROCESSOR TEC Figure 4. really bad. while floating point devices have better precision.000 times less quantisation noise than fixed point. Noise is signal is usually represented by its standard deviation. this accumulator is just another 16 bit fixed point variable. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. The same thing happens when a number is stored as a 16-bit fixed point value. The gap between numbers is one ten-thousandth of the value of the number we are storing. and will correspondingly add quantization noise on each step. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. DSPs handle this problem by using an extended precision accumulator. and a shorter development cycle. floating point has roughly 3. this quantization noise will simply add. In other words. and add the product to an accumulator. Standard deviation of this quantisation noise is about one-third of the gap size. DEPARTMENT OF ECE PAGE NO. For instance. while in the SHARC DSPs it contains 80 bits for fixed point use. we add noise to the signal. the noise on each output sample may be 500 times the noise on each input sample.. multiply it by the appropriate sample from the input signal. Although this is an extreme case.e. we need to scale the values being added.000 as a signed integer. in a 500 coefficient FIR filter. . while for a fixed point number it is only about ten-thousand to one. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. it must be round up or down by a maximum of one-half the gap size i.5. higher dynamic range. in a 16 bit DSP it may have 32 to 40 bits. In the worst case. except that the added noise is much worse. This extended range virtually eliminates round-off noise while the accumulation is in progress. It can be rated in the form of signal to noise ratio and quantisation noise. Suppose we implement an FIR filter in fixed point. each time we store a number in floating point notation. it illustrates the main point when many operations are carried out on each sample. Fixed point DSPs are generally cheaper.1: Fixed versus floating point. To avoid overflow. suppose we store the number 10. floating point has such low quantization noise that these techniques are usually not necessary. This is a special register that has 2-3 times as many bits as the other memory locations. In traditional microprocessors. Suppose we store in a 32 bit floating point format. To do this. This strategy works very well. greatly lowering the signal-to-noise ratio of the system. although it does limit how some algorithms must be carried out. For instance. To store the number. it's bad. In comparison.-47 . This is because the gaps between adjacent numbers are much larger. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. we loop through each coefficient. Here's the problem. For example.

While they can be written in fixed point. In comparison. In contrast. television and other video signals typically use 8 bit ADC and DAC. floating point systems are also easier to develop algorithms for. making them suitable for fixed point. the cost of the product will be reduced. floating point will generally result in a quicker and cheaper development cycle. the possibility of an overflow or underflow needs to be considered after each operation. DEPARTMENT OF ECE PAGE NO. and almost certainly need floating point to capture the large dynamic range. The next thing to look at is the complexity of the algorithm that will be run .If it is relatively simple. For instance. and the precision of fixed point is acceptable. and what scaling needs to take place. In many applications. .-48 . The programmer needs to continuously understand the amplitude of the numbers. such as spectral analysis and FFT convolution. how the quantization errors are accumulating. frequency domain algorithms. think floating point. these issues do not arise in floating point. but a more expensive final product. think fixed point. the development time will be greatly reduced if floating point is used.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. professional audio applications can sample with as high as 20 or 24 bits. are very detailed and can be much more difficult to program. In the reverse manner. if it is more complicated. When fixed point is chosen. but the development cost will probably be higher due to the more difficult algorithms. For example. 12-14 bits per sample is the crossover for using fixed versus floating point. In fixed point. FIR filtering and other operations in the time domain only require a few dozen lines of code. the numbers take care of themselves. In comparison. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. Most DSP techniques are based on repeated multiplications and additions.

Rn. While only a single command is needed for floating point. Fx. For instance. These are the multiplication instructions used in the SHARC DSPs. DEPARTMENT OF ECE PAGE NO. many options are needed for fixed point. . It could not be any simpler. This describes the ways that multiplication can be carried out for both fixed and floating point formats. scaling. look at all the possible commands for fixed point multiplication. Fn = Fx * Fy.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. The RND and SAT options are ways of controlling rounding and register overflow. and MRF and MRB are 80 bit accumulators. and Ry refer to any of the 16 data registers. the value of any two registers can be multiplied and placed into another register. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. the floating point programmer can spend his time concentrating on the algorithm. and Fy are any of the 16 data registers. and format. These are the many options needed to efficiently handle the problems of round-off. where Fn. In contrast.2: Fixed versus floating point instructions. This table also shows that the numbers may be either signed or unsigned (S or U). MRF = Rx * Ry. and may be fractional or integer (F or I). Rx.5. The vertical lines indicate options. In other words. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. or into one of the extended precision accumulators.-49 . In comparison. and MRB = Rx * Ry.

1: Major trends in DSPs. DEPARTMENT OF ECE PAGE NO. This is mainly driven by consumer products that must have low cost electronics. meaning there is a greater difference between the largest number and the smallest number that can be represented. As shown in (c). over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs .-50 . floating point is the fastest growing segment. such a . When you are in competition to sell millions of your product.6. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. a cost difference of only a few dollars can be the difference between success and failure. 32-bit floating point has a higher dynamic range. For instance. this depends greatly on the application.32-BIT FLOATING POINT PROCESSOR 4. such as cellular telephones. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. About twice as many engineers currently use fixed point as use floating point DSPs. However. about twice as many engineers use fixed point as use floating point DSPs. In comparison. as shown in (c). floating point is more common when greater performance is needed and cost is not important. suppose you are designing a medical imaging system. However. and another 49% are considering the change. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. In (b). As illustrated in (a). The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. A good example of this is cellular telephones.6 Trends in DSP: TEC Figure 4.

The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. the internal representations of data in floating-point DSPs are more exact than in fixed-point. Only a few hundred of the model will ever be sold. the same as the signal data in DSPs. the cost of the DSP is insignificant. The first is the I/O signal word width. 16. a 32-bit product would be needed. DEPARTMENT OF ECE PAGE NO. iterated MACs require additional bits for overflow headroom. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. Three data word widths are important to consider in the internal architecture of a DSP. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations.-51 . In spite of the larger number of fixed point DSPs being used. which is 24 bits for floating-point. The second word width is that of the coefficients used in multiplications. exponentiation vastly increases the dynamic range available for the application. For a single 16-bit by 16-bit multiplication. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). but the performance is critical. Fortunately. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. Third. For this application. or 32 bits for fixed-point DSPs. the floating point market is the fastest growing segment. which would go beyond most application requirements in accuracy. and can be 8. 16 bits for fixed-point. First. or a 48-bit product for a single 24-bit by 24-bit multiplication. in integer as well as real values. Finally. .32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. this overflow headroom is 8 bits.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. ensuring greater accuracy in end results. However. depending whether single or double precision is used. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. 4. In fixed. floating-point coefficients can be 24 bits or 53 bits of precision. at a price of several hundred-thousand dollars each. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow).point devices. Second. While fixed-point coefficients are 16 bits.

and etc. With advent of new technology. Using latest CAD tools could solve the problem. This created new challenges to digital designers as well as circuit designers. Later Integrated Circuits (ICs) were invented. counters.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. In this process. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). I/O peripheral devices and etc. . Designers felt need to automate these processes. i. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. It became very easy to a designer to verify functionality of design at various levels. Using design at this level. registers.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. Rapid advances in Software Technology and development of new higher level programming languages taken place. for design electronics circuits with assistance of software programs.-52 . This way of designing (using CAD tools) is certainly a revolution in electronic industry. One can fabricate a chip contains more than Million of gates.. At this point design process still became critical. because of manual converting the design from one level to other. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools.) on an IC.) on a chip. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale.e. At this point design process started getting very complicated.. multiplexes.e. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. DEPARTMENT OF ECE PAGE NO. using this scale of integration people succeeded to make digital subsystems (Microprocessor. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. This may be leading to development of sophisticated electronic products for both consumer as well as business. This level is LSI (Large Scale Integration). one can create digital sub blocks (adders. i. CMOS (Complementary Metal Oxide Semiconductor) process technology.

-53 .2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5. DEPARTMENT OF ECE PAGE NO.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.32-BIT FLOATING POINT PROCESSOR 5. .

Reprocurement and reuse was also a big issue.3. however. ranging from the algorithmic level to the gate level. The language can be used as a communication medium between different CAD and CAE tools . DEPARTMENT OF ECE PAGE NO.The complete language. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. and many ambiguities present in the 1987 version of the language were resolved. the syntax of many constructs was made more uniform. Therefore. According to IEEE rules.-54 . This subset is usually sufficient to model most applications .1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD).2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. available from IEEE.3. Thus. It is a hardware description language that can be used to model a digital system at many levels of abstraction. this version of the language is known as the IEEE STD 1076-1987. documentation. 5. models written in this language can be verified using a VHDL simulator.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. a need for a standardized hardware description language for the design. This new version of the language is known as the IEEE STD 1076-1993. The IEEE in the December 1987 standardized VHDL language. the language was upgraded with new features. Consequently. The language has also been recognized as an American National Standards Institute (ANSI) standard. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. and verification of the digital systems was generated. The language can be used as exchange medium between chip vendors and CAD tool users. The official language description appears in the IEEE standard VHDL language Reference manual. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. 5. Different chip vendors can provide VHDL descriptions of their components to system designers.

in turn. that is a digital can be modeled as asset of interconnected components. DEPARTMENT OF ECE PAGE NO. such as finite –state machine descriptions. and behavioral. Component And2 Port (L.3. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. and there are no limitations imposed by the language on the size of the design. and machine-readable. Structural style of modeling: In this one an entity is described as a set of interconnected components.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. which contains one external view and one or more internal views. End component. As a set of concurrent assignment statements (to represent data flow) 3. Begin X1: Xor2portmap (A. M: in BIT. As a set of interconnected components (to represent structure) 2. human-readable. It supports both synchronous and asynchronous timing models. B. CARRY). while the external view specifies the interface of the device through which it communicates with the other modules in the environment. . or mixed. Each Entity is described using one model. Arbitrarily large designs can be modeled using the language. B. Z:out BIT). each component. bottom-up. This model specifies the external view of the device and one or more internal views. SUM) A1: AND2portmap (A. called an Entity. and Boolean equations. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. can be modeled using the language. 1. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. Various digital modeling techniques. The language supports flexible design methodologies: top-down. In VHDL each device model is treated as a distinct representation of a unique device. 5. The language supports three basic different styles: Structural.-55 . The language is publicly available. Dataflow. The Entity is thus a hardware abstraction of the actual hardware device. Y: in BIT. Such a model for the HALF_ADDER entity. can be modeled as a set of interconnected subcomponents. N:outBIT). The internal view of the device specifies functionality or structure. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. End component.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy.

and EDIF and mixed VHDL-Verilog-EDIF designs. graphical and textual simulation output viewers.4 DATAFLOW STYLE OF MODELING: In this modeling style. do not explicitly specify the structure of the entity but merely its functionality. which are specified inside a process statement. 1076-1993 standard.3. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. designs. Two component declarations are present in the declarative part of the architecture body.4. The declared components are instantiated in the statement part of the architecture body using component instantiation.the entity declaration for half adder specifies the interface ports for this architecture body. VHDL'93 compiler. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order.1. . Verilog. and libraries. SIMULATION TOOL 5.32-BIT FLOATING POINT PROCESSOR TEC End ha. 5.In a signal assignment statement. single simulation kernel. 13641995 standard. The name of the architecture body is ha . Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. The data flow model for the half adder is described using two concurrent signal assignment statements . The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position. and auxiliary utilities designed for easy management of resource files. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std.4. 5. several debugging tools.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL.3. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. 5.4.-56 . 5. These sets of sequential statements. Verilog compiler.1. A process statement is a concurrent statement that can appear with in an architecture body. The architecture body is composed of two parts: the declaration part and the statement part. DEPARTMENT OF ECE PAGE NO. It comprises three different design entry tools.4 INTRODUCTION TO HDL TOOLS 5. the symbol <=implies an assignment of a value to a signal.2.

.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. DEPARTMENT OF ECE PAGE NO. and Tcl scripts.0 May 1997). The keyword coloring is also available when HDL Editor is used for editing macro files.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. SDF files must comply with OVI Standard Delay Format Specification Version 2. that is: a.0. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. HDL Editor: HDL Editor is a text editor designed for HDL source files. modification and procurement of hardware system.4. 1.1/D1. 2. It allows you to graphically edit waveforms so as to create desired test vectors. The VITAL-compliant models can be annotated with timing data from SDF files. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. the communication of hardware design and test verification data. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. The editor is tightly integrated with the simulator to enable debugging source code. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. 4. The contents of the default-working library of the design.1. 5. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. 5. It displays specific syntax categories in different colors (keyword coloring). Resource files attached to the design. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. Design Browser: The Design Browser window displays the contents of the current design. 3. Perl scripts. b.-57 . the maintenance. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms.

v) • EDIF net list file (. DEPARTMENT OF ECE PAGE NO. or EDIF objects declared within a selected region of the current design. Compilation: Compilation is a process of analysis of a source file.vhd) • Verilog file (. Cycle-based simulation is significantly faster than event-driven. Verilog.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. Verilog. d.asf) • Block diagram file (. and scripts. 5. VHDL. or EDIF file containing HDL code (or net list) generated from the diagram. The structure of the design unit selected for simulation. transistors or gates) and their interconnection.32-BIT FLOATING POINT PROCESSOR TEC c. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled.4. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel.-58 .EDIF) • State diagram file (. In Active-HDL. the compiler analyzes the intermediate VHDL. respectively for VHDL. • The Active-HDL simulator provides two simulation engines. . When you choose a menu command or toolbar button for compilation. Active-HDL provides three compilers. 6. Verilog.bde) In the case of a block or state diagram file. macros. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. and EDIF. All Active-HDL tools output their messages to Console. a source file can be on of the following: • VHDL file (. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. A net list is a set of statements that specifies the elements of a circuit (for example.

including: • HDL (VHDL.4. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities. .4. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC Fig4. ISE enables you to start your design with any of a number of different source types.2 Design Entry: • ISE Text Editor . 5.1: Simulation 5. and finally produce a bit stream for your device configuration.4.-59 .6 SYNTHESIS TOOL: 5.The ISE Text Editor is provided in ISE for entering design code and viewing reports.6.5.3. This overview explains the general progression of a design through ISE from start to finish. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. including ModelSim Xilinx Edition and the HDL Bencher test bench generator.6. Verilog HDL.

and produces output for the bit stream generator. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow. macro cell details. transforms.The Chip Viewer tool provides a graphical view of the inputs and outputs. FIFOs.The Map program maps a logical design to a Xilinx FPGA. • • • • 5. and pin assignments. Floor planner . Chip Viewer (CPLD only) .The PAR program accepts the mapped design. places and routes the FPGA. With Timing Analyzer.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor .3 Implementation: • Translate . PACE . and actions in a graphical editor. to system-level building blocks such as filters. Constraints Editor . and memories.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. equations. placing or routing an FPGA design.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O.State CAD allows you to specify states.6. Timing Analyzer .The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. including routing. transitions.-60 . view.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. Fit (CPLD only) .The Floor planner allows you to view a graphical representation of the FPGA. FPGA Editor . CORE Generator . State CAD State Machine Editor . Place and Route (PAR) . The state machine will be created in HDL. Global logic. and after fitting and routing a CPLD design.4. analysis can be performed immediately after mapping. and Area Group constraints. and to view and modify the placed design. • • • • • • • . Map .The Constraints Editor allows you to create and modify the most commonly used timing constraints.The FPGA Editor allows you view and modify the physical implementation.

32-BIT FLOATING POINT PROCESSOR TEC 5.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.6. • • • .-61 .The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration. iMPACT . and subsequently allows you to configure your device.The iMPACT tool generates various programming file formats.4. DEPARTMENT OF ECE PAGE NO.4 Device Download and Program File Formatting: • BitGen . Integration with ChipScope Pro. XPower .

DEPARTMENT OF ECE PAGE NO. subtraction.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition.-62 .1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6.1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . multiplication and division are done using active HDL tool and the results are as follows: 6.

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .-63 .2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format. DEPARTMENT OF ECE PAGE NO. .32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.

Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6. .32-BIT FLOATING POINT PROCESSOR TEC 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format. DEPARTMENT OF ECE PAGE NO.-64 .

4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6. .32-BIT FLOATING POINT PROCESSOR TEC 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . DEPARTMENT OF ECE PAGE NO. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.-65 .

• 7. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. . multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. subtraction. DEPARTMENT OF ECE PAGE NO. The Functional-simulation has been successfully carried out with the results matching with the expected ones. • • Procedures for performing basic arithmetic operations are been formed.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations.-66 . Basic arithmetic operations such as addition.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7.

or something might unexpectedly block its range of motion.-67 . however. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. The wide dynamic range of a floating-point DSP. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. The greater precision of signal data. DEPARTMENT OF ECE PAGE NO. The radar system may be tracking in a range from 0 to infinity.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. Many levels of signal input from light. but need to use only a small subset of the range for target acquisition and identification. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. enable imaging systems to achieve a much higher level of recognition and definition for the user. together with the device’s more accurate internal representations of data. However. unpredictable events can occur on an assembly line. Since the subset must be determined in real time during system operation. x-rays. . In these cases. the robot might weld itself to an assembly unit. Wide dynamic range also plays a part in robotic design. feedback is well out of the ordinary operating range. For instance. Normally. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range.

Science Research Associates. P.1109/SNPD. pp.) Introduction to Computer Architecture.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman. Williams. J. (1981) A survey of high-level language machines in Japan.ieeexplore. & Zaremba. T. H. (Ed. 281-317 Yamamoto.computer. Hayes. S.. (1987) The Implementation of Functional Programming Languages. (1986) A 32 bit processor architecture for direct execution of Forth.. Chicago. Proc. Prentice-Hall. M. 197-210 Jones. (1975) Stack computers. 1975.2007. 14(7) 68-78 REFERENCES www.ieee.org www.org/portal/web/csdl/doi/10.-68 . W..com . July 1981.intel. Pacific Grove CA. New York McKeeman. Computer. 28-30 November 1986. In: Stone. M. pp. DEPARTMENT OF ECE PAGE NO. In: 1986 FORML Conf.46 www. R.

use IEEE.-69 .all.all. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . DEPARTMENT OF ECE PAGE NO. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc.std_logic_unsigned.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1.Compute Ea-Eb -2. use IEEE. variable Temp :Std_logic_vector(6 downto 0).std_logic_1164.all.std_logic_arith. use IEEE. b : in std_logic_vector(31 downto 0).Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE. begin temp:=x. end Fadd.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. y : out std_logic_vector(31 downto 0) ).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.

-. end function.Mb : std_logic_vector(22 downto 0).Resultant Exponent variable Ns : integer.s2 : std_logic.b : std_logic. -.Subtraction of Exponents --*2.Internal Register variable MbIn : std_logic_vector(22 downto 0).32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i.-70 . -. b :=Data(31). -. --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).Internal Register variable Ea. Z :=(a&b). -.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). Ea :=Acc(30 downto 23). -. variable X : std_logic_vector(31 downto 0).Sign Of Resulant Exponent variable a. -. else TEC Sum:=Sum. -. end loop. end loop. return sum. -.Z : std_logic_vector(1 downto 0).Sign Of Resultant Mantissa variable W. Eb :=Data(30 downto 23).Sign Of Two exponents variable s1.Eb : std_logic_vector(7 downto 0). -. IE:=Eb(6 downto 0). MbIn:=Data(22 downto 0).Number Of Shifts variable Ma.Sign Of Two mantissas variable Sign : std_logic. -. DEPARTMENT OF ECE PAGE NO. --***************************************************************** --*Equalization of Exponents includes two steps --*1. Ma:=MaIn. end if. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).Mangitude Of Two mantissas variable ES : std_logic.Final Result begin MaIn:=Acc(22 downto 0).Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. a :=Acc(31). Es:=Eb(7) . -.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0).

IE:=Eb(6 downto 0). ES:=Ea(7). Ma:=MaIn. end loop. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). DEPARTMENT OF ECE PAGE NO. IE:=Ea(6 downto 0). ES:=Eb(7). IE:=Ea(6 downto 0). when "11" => Mb:=MbIn.-71 . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). IE:=IE. end loop. Mb:=Mb.32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end if. Ma:=Ma. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). when "10" => Mb:=MbIn. . Ma:=MaIn. IE:=Ea(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). else NS:=Ns. Es:=Ea(7). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). ES:=Ea(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). when "01" => Mb:=MbIn. end loop. end loop. Ma:=MaIn. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). ES:=Ea(7).

-72 . --******************Addition of Mantissas**************************** IR:=Ma+Mb.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). s2:=Data(31). --***********logic for the sign of the mantissa********************** s1:=Acc(31). elsif(Ma=Mb) then sign:='0'. else NS:=Ns. else sign:=sign. end if. when others => Null. Mb:=Mb. end case. end if. ES:=Ea(7). elsif(Ea<Eb) then sign:='1'. sign:='1'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. ES:=Eb(7). IE:=IE. IE:=Eb(6 downto 0). if(Ea>Eb) then sign:='0'. elsif(Ma<Mb) then sign:='1'. W :=(s1&s2). if(Ea>Eb) then sign:='1'. DEPARTMENT OF ECE sign:='0'. Ma:=Ma. PAGE NO. end loop. end if. case W is when "00" => when "11" => when "01" => when "10" => . else sign:=sign.

DEPARTMENT OF ECE PAGE NO. end case. else sign:=sign. when others => null. end if. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif(Ma=Mb) then sign:='0'. else sign:=sign.b) begin y<=float_add(a.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end process. begin process(a. elsif(Ma<Mb) then sign:='0'. end Fadd. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)).-73 * . TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . end function.b). return X. end if.

all. begin temp:=x. end Fsub. y : out std_logic_vector(31 downto 0)). use ieee.std_logic_1164.-74 .Compute Ea-Eb 2. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0).all. .std_logic_unsigned. use IEEE.32-BIT FLOATING POINT PROCESSOR ----1.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.std_logic_arith. b : in STD_LOGIC_VECTOR (31 downto 0). variable Temp : Std_logic_vector(6 downto 0).Shift the that has lesser Exponent by Ea-Eb places to the right * 3. DEPARTMENT OF ECE PAGE NO.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.all. use ieee.

b :=Data(30).MbIn: std_logic_vector(22 downto 0). -. -.Sign Of Resultant Mantissa variable W.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Mb : std_logic_vector(22 downto 0).Sign Of Two Mantissas variable sign : std_logic. return sum. -.Number Of Shifts variable Ma. variable X : std_logic_vector(31 downto 0).b : std_logic.Internal Register variable Ea.Sign Of Resulant Exponent variable a.Eb : std_logic_vector(7 downto 0). end function.Mangitude Of Two Mantissas variable ES : std_logic.Subtraction of Exponents * * . -.Final Result begin MaIn:=Accout(22 downto 0). Ea :=Accout(30 downto 23). a :=Accout(30). -. Eb :=Data(30 downto 23). -.Resultant Exponent variable Ns : integer. end if. else Sum:=Sum.Z : std_logic_vector(1 downto 0).s2 : std_logic.Sign Of Two Exponents variable s1. end loop. -. -.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). -. --*********************variable Declarations*********************** TEC variable MaIn.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i.-75 . DEPARTMENT OF ECE PAGE NO. --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -. -. Z :=(a&b). MbIn:=Data(22 downto 0).

ES:=Ea(7).-76 . DEPARTMENT OF ECE PAGE NO. end loop. end if.32-BIT FLOATING POINT PROCESSOR --*2. IE:=Eb(6 downto 0). end loop. Ma:=MaIn. else NS:=Ns. Ma:=Ma. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. ES:=Ea(7). IE:=IE. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Eb(7). TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). . IE:=Ea(6 downto 0). Mb:=Mb. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). end loop. IE:=Ea(6 downto 0). Ma:=MaIn. when "01" => Mb:=MbIn. ES:=Ea(7).

IE:=IE. --******************Subtraction of Mantissas************************ IR:=Ma-Mb. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. end loop. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). IE:=Ea(6 downto 0). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end if. end case. IE:=Eb(6 downto 0). TEC Ma:=MaIn. else NS:=Ns. Ma:=MaIn. Mb:=Mb. IE:=Eb(6 downto 0). ES:=Eb(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). when others => null. ES:=Eb(7). . end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). DEPARTMENT OF ECE PAGE NO. ES:=Ea(7). when "11" => Mb:=MbIn. end loop. ES:=Ea(7).-77 . Ma:=Ma.

elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'.-78 . end if. else sign:=sign. elsif (Ma=Mb) then sign:='0'. end if. elsif(Ma<Mb) then sign:='1'. DEPARTMENT OF ECE PAGE NO. elsif (Ma=Mb) then sign:='0'. . elsif(Ma<Mb) then sign:='0'. end if. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. case W is when "00"=> sign:='0'. end if. when "01"=> if(Ea>Eb)then sign:='0'. when "11"=> sign:='1'. else sign:=sign. elsif(Ea<Eb) then sign:='1'. else sign:=sign. else sign:=sign. when "10"=> if (Ea>Eb)then sign:='1'. s2:=Data(31). elsif (Ea<Eb) then sign:='0'. W:=(s1&s2).32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31).

end process. end case.b).all. --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0). --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)).Multiplication of the Mantissas * * -************************************************************************** library IEEE. end function. end Fmul. use IEEE.-79 .std_logic_unsigned. y: out STD_LOGIC_VECTOR (31 downto 0) ).all. return X.std_logic_1164. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. use IEEE. end f_sub. begin process(a. .b) begin y<=float_sub(a. b: in STD_LOGIC_VECTOR (31 downto 0). DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC when others=> null.Addtion of the Exponents 5.

-.Two Exponents Icluding Sign variable m1.Magnitude O Two Mantissas variable s : std_logic.Eb : std_logic_vector(6 downto 0). end case.Sign Of Resultant Mantissa variable a. e2 :=Data(30 downto 23). variable x : std_logic_vector(31 downto 0).Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0).-80 . m1 :=Accout(10 downto 0). -. --************logic for the sign of the Mantissa******************* s1:=Accout(31).Final Result begin Carry:='0'. -. -. case Z is when "00" => s:='0'. -. .Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1.sign Two Mantissas variable Ea. DEPARTMENT OF ECE PAGE NO. -.Z : std_logic_vector(1 downto 0).Carry variable W. Z :=(s1&s2). -.Resultant Mantissa variable carry : std_logic.Sign Two Exponents variable s1. -.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout.Magnitude Of Two Exponents variable c : std_logic. -.e2 : std_logic_vector(7 downto 0).b : std_logic. s2:=Data(31).s2 : std_logic. m2 :=Data(10 downto 0). e1 :=Accout(30 downto 23).m2 : std_logic_vector(10 downto 0). when "11" => s:='0'. when others=> s:='1'. -.Resultant exponent variable m : std_logic_vector(21 downto 0). -.

e:=Ea+Eb. e:=Ea+Eb. end if. Eb:=e2(6 downto 0). e:=Eb-Ea.-81 . else c:='0'. b :=Data(30). when "11" => when others => null. elsif(Ea<Eb) then c:='1'. case W is when "00" => c:='0'. end if. W :=(a&b). e:=Ea-Eb. DEPARTMENT OF ECE PAGE NO. e:=Eb-Ea. end case.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). . when "10" => if(Ea>Eb) then c:='1'. else c:='0'. --*************logic for multiplication************************* m:=m1*m2. e:="0000000". e:="0000000". e:=Ea-Eb. when "01" => if(Ea>Eb) then c:='0'. elsif(Ea<Eb) then c:='0'. c:='1'. a :=Accout(30).

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

when "10"=> if(Ea>Eb) then c:='1'. e:=Ea-Eb. end if. if(Ea>Eb) then c:='1'. Eb:=e2(6 downto 0). e:=Eb+Ea. if(Ea>Eb) then c:='0'. else c:='0'. else c:='0'. e:=Ea+Eb. b :=e2(7). . e:=Eb-Ea. e:="0000000". DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. Z :=(a&b). e:=Ea-Eb. elsif(Ea<Eb) then c:='0'. case Z is when "00" => if(Ea>Eb) then c:='0'.-86 . else c:='0'. elsif(Ea<Eb) then c:='1'. elsif(Ea<Eb) then c:='0'. e:=Ea+Eb. end if. e:="0000000".32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). end if. elsif(Ea<Eb) then c:='0'. e:="0000000". e:=Eb-Ea. a :=e1(7).

end F_div. e:="0000000".32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. when others=> null. DEPARTMENT OF ECE PAGE NO. TEC . end process. else c:='0'. return X.-87 .b). end case. end function. begin process(a. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). end if.b) begin Y<=float_div(a.

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