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- 1.1Objective
- 1.2Methodology
- 1.3Conceptual Survey
- 1.4Organisation Thesis
- 2.1. Real Number System
- 2.2. Fixed-point Vs floating-point in digital signal processing
- 2.3. Floating point
- 2.4. General floating point format:
- 2.5.1Single Precision Format:
- 2.5.3. Double Precision Format:
- 2.6 Ranges of Floating-Point Numbers
- 2.7Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic:
- 2.8.1.1. Block diagram representation of floating point adder:
- 2.8.1.2. Addition of floating points using IEEE 754 format:
- 2.8.2.1. Block diagram representation of floating point subtraction:
- 2.8.2.2. Subtraction of floating points using IEEE 754 format:
- 2.8.2.3. Flow chart for floating point subtraction:
- 2.8.3.1. Multiplication using IEEE floating point standard:
- 2.8.3.2. Block diagram of floating point multiplication:
- 2.8.3.3. Flow chart for floating point multiplication
- 2.8.4.1. Block diagram for floating point division:
- 2.8.4.2 Floating point division using IEEE floating point standard
- 2.8.4.3. Flow chart for floating point division
- 2.9. Rounding Error
- 2.10. Normalization
- 2.11. Truncation
- 3.1 Floating Point Addition
- 3.2 Floating Point Subtraction
- 3.3 Floating Point Multiplication
- 3.4 Floating Point Division
- 4.1 Processor:
- 4.2 Digital Signal Processing
- 4.3. Difference between off-line processing and real time processing:
- 4.4. Architecture of digital signal processor:
- 4.5. Comparison between Fixed Point and Floating Point System:
- 4.6 Trends in DSP:
- 4.7 Accuracy of Floating Point DSP
- 5.2 IC DESIGN FLOW:
- 5.3.1 HISTORY:
- 5.3.2 CAPABILITIES
- 5.3.3 HARDWARE ABSTRACTION:
- 5.3.4 DATAFLOW STYLE OF MODELING:
- 5.3.5 BEHAVIORAL STYLE OF MODELING:
- 5.4.1. SIMULATION TOOL 5.4.1.1 Active HDL Overview:
- 5.4.2. Standards Supported
- 5.4.3 ACTIVE-HDL Macro Language:
- 5.4.4Simulation:
- 5.4.6.1 OVERVIEW OF XILINX ISE:
- 5.4.6.2 Design Entry:
- 5.4.6.3 Implementation:
- 5.4.6.4 Device Download and Program File Formatting:
- 6.1 simulation results of floating point addition
- 6.2 simulation results for floating point subtraction
- 6.3 simulation results for floating point multiplication
- 6.4 simulation results for floating point division
- 7.1 CONCLUSIONS
- 7.2 FUTURE SCOPE

TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

. DEPARTMENT OF ECE PAGE NO.-4

1: Binary Real Number System Because the size and number of registers that any computer can have is limited. As shown at the bottom of Figure 1.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. As shown in Figure 1.1. .-5 . The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. the real-number system comprises the continuum of real numbers from minus infinity (. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers. only a subset of the real-number continuum can be used in real-number calculations.) to plus infinity (+ ). Figure 2. DEPARTMENT OF ECE PAGE NO.

768 to 32.535. Digital Signal Processing can be divided into two categories. In fixed-point systems. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. designers can identify the DSP that is best suited for an application. signed integer uses two's complement to make the range include negative numbers. Balancing these factors together. the signed fraction format allows . the stored number can take on any integer value from 0 to 65. 2. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. from -32. performance attributes. DSPs enable designers to build innovative features and differentiating value into their products. although a different length can be used. With unsigned fraction notation. low-cost development tools. the number is an integer). the digit string can be of any length. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. but decimal fixed point is common in commercial applications. fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices. In common mathematical notation.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. There are four common ways that these 216 ' 65. some specific assumption is made about where the radix point is located in the string. In unsigned integer.-6 . The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic.536 levels are spread uniformly between 0 and 1.767. Fixed point DSPs usually represent each number with a minimum of 16 bits. DEPARTMENT OF ECE PAGE NO. Similarly.2. Motorola manufactures a family of fixed point DSPs that use 24 bits. Among the key factors to consider are the computational capabilities required for the application. Lastly. For instance. processor and system costs. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. the 65.536 possible bit patterns can represent a number. Software programmable for maximum flexibility and supported by easy-touse. and ease of development. Fixed-point Vs floating-point in digital signal processing Fig 2. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. while floating-point DSPs support either integer or real arithmetic.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers.

This results in many more bit patterns than for fixed point.294. but small gaps between small numbers.296 to be exact. respectively.3. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. a necessity to implement counters. and executes them with equal efficiency.967. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . For this reason.-7 . It is measured in” FLOPS”. This position is indicated separately in the internal representation. The term” floating point” refers to the fact that the radix point can "float".4 ×1038 and ±1.In comparison. loops. it depends on the internal architecture. In the most common format (ANSI/IEEE Std. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix).2 ×1038. The speed of floating-point operations is an important measure of performance for computers in many application domains. 2324. This is known as the significand. DEPARTMENT OF ECE PAGE NO. the SHARC DSPs are optimized for both floating point and fixed point operations. The represented values are unequally spaced between these two extremes. 2. This is important because it places large gaps between large numbers. the largest and smallest numbers are ±3." 2. it can be placed anywhere relative to the significant digits of the number. floating point DSPs typically use a minimum of 32 bits to store each value. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. and floating-point representation can thus be thought of as a computer realization of scientific notation.4. and signals coming from the ADC and going to the DAC." rather than just "Floating Point. For instance. that is. Floating point A floating-point number is the one. the SHARC devices are often referred to as "32-bit DSPs. which is capable of representing real and decimal numbers. equally spaced between -1 and 1. All floating point DSPs can also handle fixed point numbers.However. A key feature of floating point notation is that the represented numbers are not uniformly spaced. The radix point is not explicitly included. The floating-point operations are incorporated into the design as functions. or sometimes the mantissa (see below) or coefficient.754-1985). The logic for these is different from the ordinary arithmetic functions.

(This is because the exponent field is in . with an average error of about 3%. composed as integer. A signed integer exponent.-8 . 1 for negative values. DEPARTMENT OF ECE PAGE NO. The significand is multiplied by the base raised to the power of the exponent. b is the base. 2. computers used many different forms of floating-point. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. and e is the exponent. Significand is a real number.Fraction.32-BIT FLOATING POINT PROCESSOR TEC significant digit. 10 or 16. Symbolically. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. The floating-point format needs slightly more storage (to encode the position of the radix point).5. also referred to as the characteristic or scale. Prior to the IEEE-754 standard. which modifies the magnitude of the number. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. this final value is where s is the value of the significand (after taking into account the implied radix point). so when stored in the same space. These differing systems implemented different parts of the arithmetic in hardware and software. the format of the representations. or to the right of the rightmost digit. and the rounding behaviour of operations. floating-point numbers achieve their greater range at the expense of precision. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. The length of the significand determines the precision to which numbers can be represented. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. These differed in the word sizes.

The exponent's base is two. IEEE-754 specifies binary representations for floating point numbers: Table 2. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. also known as the significand.f. and the mantissa. To do this. DEPARTMENT OF ECE . or 1023 plus the true exponent for double precision. such as volume ramping in digital sound processing. Flipping the value of this bit flips the sign of the number.-9 . 4. and each possible combination of bits represents one real number. 0 denotes a positive number. The exponent field contains 127 plus the true exponent for single-precision. The sign bit is 0 for positive. 2. the exponent. a bias is added to the actual exponent in order to get the stored exponent. represents the precision bits of the number.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. 1 for negative. where f is the field of fraction bits. even though there are infinitely many real numbers (even between 0 and 1). to sum up: 1. So. This means that at most 232 possible real numbers can be exactly represented. It is composed of an implicit leading bit and the fraction bits. The Mantissa: The mantissa. 1 denotes a negative number. The first bit of the mantissa is typically assumed to be 1. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. A float is represented using 32 bits. There are many formats that are used for representation of floating point number. The Sign Bit: The sign bit is as simple as it gets. 3.) This can be exploited in some applications. The Exponent: The exponent field needs to represent both positive and negative exponents.

-10 . and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0).1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. 'E'. Table 2.5. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. which may be represented as numbered from 0 to 31.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. then V=-Infinity If E=255 and F is zero and S is 0. then V=Infinity .5. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. left to right.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. the next eight bits are the exponent bits. DEPARTMENT OF ECE PAGE NO.5. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010). IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. S. then V=NaN ("Not a number") If E=255 and F is zero and S is 1.

00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.101 = -6. If E=0 and F is nonzero.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1. DEPARTMENT OF ECE PAGE NO.F) These are "unnormalized" values.3125 The biased exponent is -2+127=125= (01111101 • 1.0 The biased exponent is . then V=-0 If E=0 and F is zero and S is 0.-11 .5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1. If E=0 and F is zero and S is 1.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1. then V=(-1)**S * 2 ** (-126) * (0.101 = 6.F) where "1. then V=0 In particular.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.

01012.8125 .40625 × 2 = 0.5 The based exponent: 127+5= (10000100 .312510 = 10100100001.625 × 2 = 1.5 × 2 = 0.40625 0.8125 × 2 = 1.0 0 1 0 1 1313.1015625 × 2 = 0. • -78.25 × 2 = 0.010010000101012 × 210. = 1.5 × 2 = 1. . So -1313.25 0.1015625 0.203125 0.25 The biased exponent: 127+6=133=(10000101 • -1313. DEPARTMENT OF ECE PAGE NO.3125 131310 = 101001000012 0.625 0.-12 .3125 0.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0. sign bit is 1.203125 × 2 = 0. 10 + 127 = 137 = 100010012.32-BIT FLOATING POINT PROCESSOR TEC • 37.3125 is • 0.

32-BIT FLOATING POINT PROCESSOR 0. 'E'.5.101562510 = 0. which may be represented as numbered from 0 to 63. the next eleven bits are the exponent bits.625 0. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.0 1 0. DEPARTMENT OF ECE .3.5 0 × 2 = 1. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0). next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001).1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.1015625 is 0 00111101 110100000000000000000000 TEC 2. left to right.25 1 × 2 = 0.5 × 2 = 1.25 0. The first bit is the sign bit.5. then V=NaN ("Not a number") PAGE NO.00011012 = 1. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. S.-13 .

53 ~ 10308. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. then V=(-1)**S * 2 ** (-1022) * (0.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). floating-point notation allows calculations over a wide range of magnitudes. DEPARTMENT OF ECE PAGE NO. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . . using a fixed number of digits.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. If E=0 and F is zero and S is 1.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. then V=-Infinity If E=2047 and F is zero and S is 0. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision. while maintaining good precision.5. If E=0 and F is nonzero.6. Table 2. 15 exponent bits and 112 significand bits. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1.-14 .1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. then V=-0 If E=0 and F is zero and S is 0.F) These are "unnormalized" values.F) where "1.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable.

2: Effective Range of IEEE Floating Point Number with Denormalized. U) (where B is the base of the system.85 to ~1038. Positive numbers less than 2-149 (positive underflow) . Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand.53 ~10-323. Approximate Decimal 2127 21023 ~10-44. The number of normalized floating point numbers in a system F(B. Normalized And Approximate Decimal Values.3 to ~10308.32-BIT FLOATING POINT PROCESSOR TEC Table 2. Negative numbers greater than -2-149 (negative underflow) 3. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). DEPARTMENT OF ECE PAGE NO. L. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. P is the precision of the system to P numbers. the range for negative numbers is given by the negation of the above values. Zero 4.-15 . P. There is a largest floating point number. There is a smallest positive normalized floating-point number. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2. L is the smallest exponent represent able in the system.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. and the smallest possible value for the exponent.6.

7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. 2.32-BIT FLOATING POINT PROCESSOR 5. Recently. the most negative value which is defined in bias-127 exponent representation. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . If M = 0. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. 2.infinity. the largest value which is defined in bias-127 exponent representation. the exponent is set to -127 (E = 0). However the CPU will have to perform extra arithmetic to read the number when stored in this format. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately.-16 . When this occurs. the number is exactly zero. When this occurs. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. DEPARTMENT OF ECE PAGE NO. Underflow occurs when the sum of the exponents is more negative than -126. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format.

i..32-BIT FLOATING POINT PROCESSOR TEC Fig 2.25x and b= 1. as the smaller number here is a=2. Division 2. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded.0225x .e. But by using floating point addition this can be avoided to a little extent.8. Floating point addition is analogous to addition using scientific notation.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.. let us consider two numbers a= 2.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. Multiplication 4. Subtraction 3. Hence the value of number ‘a’ becomes 0. Now as both the exponent values are same. For example. both the numbers are added.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal. DEPARTMENT OF ECE PAGE NO. Normalize the result. Add the numbers with decimal points aligned. They are: 1. Addition 2.1. .-17 .

. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. b= 9.1. Thus this case can said to be having rounding errors. then bit 1 is represented for sign.876543x after shifting becomes b= 0. signB as sign of number B.2345670 x in which the remaining part (9876543) which is discarded also carries the result.1. then the following result may occur: 1. ExpA as exponent of number A . 2. If the numbers are represented with both positive and negative sign.e. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. Consider a example in which a =1.. ManA as mantissa of number A. then sign of greater number is considered.1. Now both the numbers are added.234567x b= 0. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: .8.-18 . The mantissa of both numbers A and B are added.2.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1.876543x and if the addition has to be performed.234567x and b= 9.8.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.1. But the normalised result may sometimes carry the required result. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. ExpB as exponent of number B and ManB as mantissa of number B.00000009876543 x 2. a =1. 2. DEPARTMENT OF ECE PAGE NO.e. i.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .8.00000009876543 x c= 1. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.

the bias value must be subtracted from the sum 3.8. . 1. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. If the exponents are stored in biased form. the exponent sum would have doubled the bias.1. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.-19 . 6. Thus. 2. 4. DEPARTMENT OF ECE PAGE NO. Addition of significands is done. If not. the significand is rounded to the appropriate number of bits required and again normalization is checked. Firstly. the numbers are represented in IEEE floating point format.2: Flow Chart for Floating Point Adder. If there is an underflow or overflow. exception is made.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. 5.

2. resulting in a large loss of accuracy. 2. then the mantissa must be shifted one bit to the right and the exponent incremented. The number 2.25 becomes: The mantissas are added using integer addition: The result is already in normal form. so the hidden bits can sum to no more than 3 (11). When adding numbers of opposite sign.2. the result is converted back to signmagnitude form. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. resulting in a sum which is arbitrarily small.25 in IEEE Floating Point Standard is: The number 134. If the sum overflows the position of the hidden bit.340625x . After the addition is performed.25x and 1. Consider addition of the numbers 2. Negative mantissas are handled by first converting to 2's complement and then performing the addition.8. Subtraction . the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. or even zero if the numbers are equal in magnitude. Thus.-20 . The mantissa is always less than 2. cancellation may occur. Normalization in this case may require shifting by the total number of bits in the mantissa.32-BIT FLOATING POINT PROCESSOR TEC 7. DEPARTMENT OF ECE PAGE NO.0625 in IEEE Floating Point Standard is: To align the binary points.

if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if . ExpB as exponent of number B and ManB as mantissa of number B.1.. both the numbers are added.2.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.8.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .8. ManA as mantissa of number A. i. Hence the value of number ‘a’ becomes 0.e.0225x . The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2. The mantissa of both numbers A and B are subtracted. Subtract the numbers with decimal points aligned. DEPARTMENT OF ECE PAGE NO. then sign is represented according to the number i. as the smaller number here is a=2. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.-21 .e. ExpA as exponent of number A . 2.25x and b= 1..340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal.. Now as both the exponent values are same. Normalize the result.1.2. The normalised result may contain the required number of digits discarding the unwanted part. signB as sign of number B. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2.

the significand is rounded to the appropriate number of bits required and again normalization is checked. the exponent sum would have doubled the bias. 4. 2. 5. If not. Thus. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 6. Consider subtraction of the numbers 2.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign.-22 . If there is an underflow or overflow. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. DEPARTMENT OF ECE PAGE NO.25x and 1.8. Thus.340625x . The numbers are represented in IEEE floating point format. 2. Subtraction of significands is done. The number 2. If the exponents are stored in biased form.25 become: The mantissas are subtracted using integer subtraction: . 2.2.0625 in IEEE Floating Point Standard is: To align the binary points. the bias value must be subtracted from the sum 3.25 in IEEE Floating Point Standard is: The number 134. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1.2. exception is made.

3.e. Z=Y. then the mantissa must be shifted one bit to the right and the exponent incremented. If the exponents are same. consider two numbers X and Y and the resultant be Z.8. number X is checked.2. Flow chart for floating point subtraction: Subtract significand si Fig 2. 2. If overflow occurred then overflow is reported and returned.2.8. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent .-23 . then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. then the result would be Z=X. In the first step. If the sum overflows the position of the hidden bit. then the significands of numbers X and Y are subtracted. If not then the result is normalized. then number Y is checked. If it is ‘0’. If both the numbers X and Y are non zeros.. At this point. then the following steps can be followed: Exponents of both the numbers are checked. If the significand is zero then it is returned if not significand overflow is checked. If overflow occurs.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. DEPARTMENT OF ECE PAGE NO. If it is ‘0’ then the resultant solution Z would be Y i. If number X is not ‘0’.

The number 18. If the exponents are not same. 1.1. If underflow occurred then it is reported if not the normalized result is given out.8. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.8. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers.8 x 9. to multiply 1.5 in IEEE FPS format is: . 2. if the significand is not zero then subtraction and further process is carried out. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.-24 .3.3.8x times 9.5 ----17. DEPARTMENT OF ECE PAGE NO.0 in IEEE FPS format is: The number 9.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result.5x : Perform unsigned integer multiplication of the mantissas. 2.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked. For example.

2. The sign of the result is the xor of the sign bits of the two numbers. If the position of the hidden bit overflows. the mantissa is: The biased-127 exponents are added. DEPARTMENT OF ECE PAGE NO. the mantissa must be shifted right and the exponent incremented. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.8.3. Block diagram of floating point multiplication: .32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in ().-25 . the result is: 2. When the fields are assembled in IEEE FPS format.

Resultant mantissa is truncated and normalized to fit for the IEEE format. . If the exponents are stored in biased form. expB as exponent of number B and manB as mantissa of number B. XOR operation for sign bit can be given as follows: Table 2.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. The mantissa of both numbers A and B are multiplied. Sign of the result is given by performing xor operation of signA and signB.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . signB as sign of number B.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. manA as mantissa of number A. DEPARTMENT OF ECE PAGE NO. The exponents of both the numbers are added and subtracted from the bias 127. Thus. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero.3.3.-26 . the exponent sum would have doubled the bias.3. expA as exponent of number A . If both the numbers X and Y are not zero. then the exponents are added and a bias of 127 is subtracted from the result. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported.8.3.8.8. At the first step.

e. .3: Flow Chart For Floating Point Multiplication. Exponent of a is 2 and exponent of b is 3.3 0.5 . When the division of both significands are done then the quotient would be 1.4. 0.5. So resultant exponent would be 2-3=-1..3. The resultant sign bit would be the xor operation of sign bits of X and Y. Hence the result can be given as 1.-27 . in general floating point division the exponents of both the numbers are subtracted and the significands are divided. DEPARTMENT OF ECE PAGE NO.2 . Fig 2.2 =1. Division Consider an example of dividing a=0.8.8.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned.5. 2.3 and b= 0. i.

DEPARTMENT OF ECE PAGE NO.8.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .-28 .8. If both the numbers are either positive or negative.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. ManA as mantissa of number A. If anyone number of the two are negative. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend.1.4. In the first step. Special . signB as sign of number B. As in floating point multiplication. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. Normalize the result. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit.8. ExpB as exponent of number B and ManB as mantissa of number B. The mantissa of both numbers A and B are divided.4.4. When divided by a 24 bit divisor. ExpA as exponent of number A . Subtract the exponent of the divisor from the exponent of the dividend. The exponents are subtracted and biased using the bias value.32-BIT FLOATING POINT PROCESSOR TEC 2. Block diagram for floating point division: Fig 2. Set the sign of the result. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement. then the resultant sign is also positive and is represented by bit ‘0’. a 24 bit quotient is produced. 2. then the result is also negative is represented by bit ‘1’.

DEPARTMENT OF ECE PAGE NO. . Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2. Number X and Y are checked.2 can be represented as M 010000001(0)11000000000000000000000 0. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity . If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked.3 S E and b= 0. in this case as larger number has to be subtracted from smaller number.Then the steps that occur are: 1.3.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted.-29 . 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned. This value is called Not A Number.8.4.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . or NaN. 2.3 0. Considering a=0. For this.

g. some form of rounding is required. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e.8. Rounding Error In floating point arithmetic. DEPARTMENT OF ECE PAGE NO.This means that the number is too small to be represented. 2.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value.. and it may be reported as 0. • Significand underflow: In the process of aligning significands. then those conditions are reported. Fig 2.4.-30 . As we shall discuss. this may be designated as +∞ or -∞.32-BIT FLOATING POINT PROCESSOR TEC 3.127). digits may flow off the right end of the significand.9.200 is less than . If not the mantissas are divided and truncated and normalized result is given out. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit. In some systems. rounding errors occur as a result of the limited precision of the mantissa . . If they are present.

RZ: Round toward Zero. relative errors increase as the magnitude of the number decreases toward zero. RP: Round toward Positive infinity. The least significant 24 bits are discarded.-31 . Same as truncation in 2's complement. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. To efficiently use the bits available for the significand. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). . DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits.10. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. The value can be kept unchanged by adjusting the exponent accordingly. However. The size of the absolute error is proportional to the magnitude of the number. For normalized floating point numbers. highest precision can be achieved. For numbers in IEEE FPS format. the relative error is approximately since For denormalized numbers (E = 0). RN is generally preferred and introduces less systematic error than the other rules. Normalization By normalization. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. RM: Round toward minus infinity. Break ties by choosing the least significant bit = 0. Same as truncation in sign-magnitude.

-32 . extra guard bits are kept during operation. to avoid possible confusion.g. resulting 1. By the end of the operation.. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. as the MSB of the significand is always 1. bits are used in final representation of a bits by one of the three methods. Zero is represented by all 0's and is not (and cannot be) normalized. The first bit 1 before the decimal point is implicit. DEPARTMENT OF ECE PAGE NO. Truncation To retain maximum accuracy. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. a 4-bit exponent field and a 9-bit significand field): 2.32-BIT FLOATING POINT PROCESSOR TEC Moreover. all extra bits during operation (called guard bits) are kept (e. the bits need to be truncated to guard bit Chopping: simply drop all . multiplication). If we assume number. it does not need to be shown explicitly. The actual value represented is However. in the following the default normalization does not assume this implicit 1 unless otherwise specified.11.

.5 round up. we say this truncation error is biased. (no matter Von Neumann Rounding: If at least one of the guard bits is 1. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. Interpretation: Value represented by guard bits is greater than 0.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. Two worst cases Both two cases can be summarized as i.-33 . otherwise do nothing. is always greater than 0.e. the Von Neumann rounding error is unbiased. 3.. add 1 to LSB . . set whether it is originally 0 or 1). DEPARTMENT OF ECE PAGE NO.

Interpretation: Value represented by guard bits is smaller than 0. round down: or if . c) If the highest guard bit is 1 and the rest guard bits are all 0. drop all guard bits. .5 round down. the rounding depends on the LSB : if . The rounding error of these cases can summarized as .32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0.5 either up or down with equal probability (50%). round up: Interpretation: Value represented by guard bits is 0. it is randomly rounded .-34 . DEPARTMENT OF ECE PAGE NO.

1985 floating point standard representation before any sort of operations are conducted on them.e.-35 . The next eight bits are that of the exponent. The numbers in contention have to be first converted into the standard IEEE 784. DEPARTMENT OF ECE PAGE NO. The exponent in this IEEE standard is represented in excess-127 format. 1111. subtraction. 1111 and negative numbers are represented by binary values less than it. multiplication and division is presented in the following pages.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER .3 Floating Point Functions A floating-point number is the one. which is capable of representing real and decimal numbers. Positive numbers are represented by binary values greater than 0111. I. The floating-point operations are incorporated into the design as functions. . the sign of the floating point number. 1111. Therefore zero is represented by 0111.e. The logic for these is different from the ordinary arithmetic functions. the exponent obtained by balancing operations is added to 0111. The MSB is the sign-bit i. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. The above representation is the IEEE-784 1985 standard representation. The logic for floating point addition.

Once the exponents are normalized. we have to first normalize their exponents. These numbers are stored into the memory from which they are read and processed. The mantissas are then added to each other and the result is then stored in a temporary register. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. This is done till the lower exponent becomes equal to the higher one.-36 . Now the numbers from the memory are loaded into two registers. So to add their mantissa’s. • • . DEPARTMENT OF ECE PAGE NO. So. These numbers are distinct.32-BIT FLOATING POINT PROCESSOR TEC 3. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. namely Accumulator and the Temp register that loads the value appearing on the data bus.

The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. namely Accumulator and the Temp register that loads the value appearing on the data bus. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. . Once the exponents are normalized. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. These numbers are stored into the memory from which they are read and processed. So to add their mantissa’s. So. These numbers are distinct.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. we have to first normalize their exponents. This is done till the lower exponent becomes equal to the higher one.-37 . DEPARTMENT OF ECE PAGE NO. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out.32-BIT FLOATING POINT PROCESSOR 3. Now the numbers from the memory are loaded into two registers. The mantissas are then subtracted and the result is stored in a temporary register.

There is however a limitation to this operation.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. so that the result is restricted to not more than 24-bits. the resulting exponent and the sign of the result that is calculated separately. So each input should not exceed 12-bits in length.32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO.-38 . • • • . If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. The final output is obtained by concatenating the product of the mantissas.

4 Floating Point Division • • • • This is more complicated then Multiplication. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. Once the quotient is full. We initiate a counter and carry this process for 24 times. we append it with the exponent value and the Sign of the division that are calculated separately. The result is stored in Temp. First the exponents are directly added or subtracted depending on which is bigger. if the MSB or the 49th bit is one than we add a one in the quotient.32-BIT FLOATING POINT PROCESSOR TEC 3. Now since the greater of the two numbers is decided. And if it is zero. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. • • • • • . Now both the numbers in the IEEE-784 standard format are compared.-39 . Apart from that the final sign of the division is calculated separately. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. This is to ensure that whatever comes as the result is after the decimal point. The convention here is that the Numerator should be always less than the denominator. Now the first 24-bits from the MSB are compared with the divisor. till the quotient is full. The decimal is assumed to be before the MSB of the resulting quotient. DEPARTMENT OF ECE PAGE NO. The logic for floating point division is as follows. we put a zero in the quotient.

DSPs can perform the mathematical calculations needed in digital signal processing. Data manipulation such as word processing and database management 2. and testing for inequalities (A=B. product life time. When this code is detected. 4. Clock frequency is generally a multiple of the system frequency.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. the overall number of registers can vary from about ten to many hundreds. When the processor executes instructions. There are marketing issues involved: development and manufacturing cost. Computers are extremely capable in two broad areas 1. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. engineering and digital signal processing.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. consider a word processing program. such as the size of the instruction set and how it interrupts are handled. finding use in everything from cellular telephones to advanced scientific instruments. The basic task is to store the information. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. the processor performs an action that corresponds to an instruction or a part thereof. written in Hertz (Hz). Consider another example of how a document is printed from a word processor. 16.-40 . These devices have seen tremendous growth in the last decade. Mathematical calculation used in science. meaning a multiple of the motherboard frequency. 32 or 64 bits called registers. competitive position. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). corresponds to the number of pulses per second. Depending on the type of processor. There are technical tradeoffs in the hardware design. The clock speed (also called cycle). DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. A<B . All microprocessors can perform both tasks. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. local memory locations of 8. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. the program moves the data from . and so on. These tasks are accomplished by moving data from one location to another. For instance. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. data is temporarily stored in small. Data manipulations involve storing and sorting information. With each clock peak. however it is difficult or expensive to make a device that is optimized for both. etc).

. depending on the application.. the math operations dominate the execution time.. such as to keep track of the intermediate results and control the loops.. While mathematics is occasionally used in this type of application. While there is some data transfer and inequality evaluation in this algorithm.e... while the output signal is denoted by y [ ]. it is infrequent and does not significantly affect the overall execution speed. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. the most common DSP technique. y[n].-41 .. In comparison. Using standard notation. the input signal is referred to by x [ ].. there may only be a few coefficients in the filter kernel. consider the implementation of an FIR digital filter. This is simply saying that the input signal has been convolved with a filter kernel consisting of: . DEPARTMENT OF ECE PAGE NO.. . An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: ..32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. i. The task is to calculate the sample at location n in the output signal.. For example..

the DSP must be able to maintain a sustained throughput of 20. The key point in off-line processing is that all of the information is simultaneously available to the processing program. In these cases a 16-bit processor may suffice. This is common in scientific research and engineering. x[n]. a geophysicist might use a seismometer to record the ground movement during the earthquake. After shaking is over. There is less room on-chip for extra features such as hardware multipliers. floating point math must often be used to reduce the cost of programming a project.x[n-1].3. For instance.32-BIT FLOATING POINT PROCESSOR TEC Fig4. design difficulty and so on.. In addition to performing mathematical calculations very rapidly. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. whereas 32-bit processors are naturally suited to the size of the data elements. For example.1: Graphical representation of FIR digital filter design. each sample in the output signal . the information may be read into a computer and analysed in some way. power consumption.-42 . most DSPs are used in applications where the processing is continuous. with the advent of very fast floating point processing hardware. The disadvantages of 32-bit processors are cost and system complexity. Also. as well as the algorithms that can be applied.x[n-2]. If suppose you are launching your desktop computer on some task . DEPARTMENT OF ECE PAGE NO. Hence execution time is critical for selecting the proper device. is found by multiplying samples from the input signal... converting a word processing document from one form to another. Floating point calculations also require a 32-bit processor for good efficiency. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. In FIR filtering . Off-line processing is a realm of personal computers and mainframes. . Difference between off-line processing and real time processing: In off-line processing. 4. consider a designing of an audio signal in DSP system such as a hearing aid. However. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. and to support code written in high level languages. but these items will appear as chip fabrication technology gets denser. say. the traditional speed advantage of integer operations over floating point operations is decreasing.y[n]. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. There are a few reasons for why to not to make it faster than necessary because as speed increases. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. and summing the products.2.. If the digital signal is being received at 20. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. so as the cost .by the filter kernel coefficients. You simply wait for the action to be completed before you give the computer its next assignment In comparison.000 samples per second. DSPs must also have a predictable execution time. not having a defined start or end. ..000 samples per second. the entire input signal resides in the computer at the same time.

4.4. this is needed in telephone communication. while keeping the input signal in data memory. For instance. we start by relocating part of the "data" to program memory. Since the buses operate independently. two binary values (the numbers) must be passed over the data memory bus. and an I/O controller. These are extremely high speed connections. This includes data. This is the world of digital signal processors. we might place the filter coefficients in program memory. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. such as samples from the input signal and filter coefficients as well as program instructions. Most present day DSPs use this dual bus architecture. the binary codes that go into the program sequencer. Real time applications input a sample. DEPARTMENT OF ECE PAGE NO. at a 40 MHz clock speed. Harvard architecture has separate memories for data and program instructions. When two numbers are multiplied. To improve upon this situation. perform the algorithm and output a sample. Alternatively. . Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. The SHARC DSPs provides both serial and parallel communications ports. Super Harvard Architecture (SHARC). For instance. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). the data transfer rate is an incredible 240Mbytes/second. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. Harvard Architecture.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. while six parallel ports each provide a 40 Mbytes/second data transfer. For example. Most of the computers are using this architecture today. While the SHARC DSPs are optimized in dozens of ways. The basis of Harvard design is that the data memory bus is busier than the program memory bus. two areas are important enough to be included are an instruction cache. Different architectures available are: Von Neumann Architecture. while only one binary value (the program instruction) is passed over the program memory bus. they may input a group of samples perform the algorithm and output a group of samples. When all six parallel ports are used together. Likewise. For example. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. improving the speed over the single bus design. there are two serial ports that operate at 40 Mbits/second each. the output signal is produced at the same time that the input signal is acquired. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. hearing aids and radar. program instructions and data can be fetched at the same time.-43 . over and over. with separate buses for each.

all DSPs can interface with external converters through serial or parallel ports. The first time through a loop. the coefficient comes over the program memory bus. DSP algorithms generally spend most of their execution time in loops. Some DSPs have on-board analog-to-digital and digital-toanalog converters. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. In the jargon of the field. providing higher speed. the program instructions must be passed over the program memory bus. However. This means that the same set of program instructions will continually pass from program memory to the CPU.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. a feature called mixed signal. providing an additional interface to off-chip memory and peripherals. DEPARTMENT OF ECE PAGE NO.-44 . The main buses (program memory bus and data memory bus) are also accessible from outside the chip. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. this efficient transfer of data is called a high memory-access bandwidth. on additional executions of the loop.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path.4. the Harvard architecture uses separate memories for data and instructions. This is a small memory that contains about 32 of the most recent program instructions. and the program instruction comes from the instruction cache. This allows . In comparison. the program instructions can be pulled from the instruction cache. such as instructions. However.

and similar functions. and the two results returned to any of the 16 registers. and is quite transparent to the programmer. NOT). subtraction.-45 . extracting and depositing segments. for 32 bit data. Fig 4. data from registers 0-7 can be passed to the multiplier. . In a single clock cycle. specifying where the information is to be read from or written to. rotating. such as shifting.4. DEPARTMENT OF ECE PAGE NO.2: Typical DSP architecture. data from registers 8-15 can be passed to the ALU. an arithmetic logic unit (ALU). A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. At the top of the diagram are two blocks labelled Data Address Generator (DAG). In simpler microprocessors this task is handled as an inherent part of the program sequencer.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. and places the result into another register. conversion between fixed and floating point formats. and a barrel shifter. OR. Elementary binary operations are carried out by the barrel shifter. Digital Signal Processors are designed to implement tasks in parallel. and so on. The math processing is broken into three sections. a multiplier. logical operations (AND. All of the steps within the loop can be executed in a single clock cycle. The multiplier takes the values from two registers. accessible at 40Mwords/second (160 Mbytes/second). one for each of the two memories. The ALU performs addition. multiplies them. absolute value. XOR. This simplified diagram is of the Analog Devices SHARC DSP. Compare this architecture with the tasks needed to implement an FIR filter. These control the addresses sent to the program and data memories.

this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. In addition. . a result of the hardware being highly optimized for math operations.-46 . However. floating-point DSPs support either integer or real arithmetic. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). TMS320C64x™ DSPs. it depends on the internal architecture . However. floating point programs often have a shorter development cycle. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. and executes them with equal efficiency.5. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. underflow and round-off. since it requires multiple cycles for each operation. including a 53-bit mantissa and an 11-bit exponent)." fixed point arithmetic is much faster than floating point in general purpose computers. the SHARC DSPs are optimized for both floating point and fixed point operations. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. Fixed point DSPs are cheaper than floating point devices. and signals coming from the ADC and going to the DAC.32-BIT FLOATING POINT PROCESSOR 4. and an 8-bit exponent. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. with architectures designed for handheld and control applications. though. Double-width precision achieves much greater precision and dynamic range at the expense of speed. By contrast. As the terms fixed. Tradeoffs of cost and ease of use often heavily influenced the fixed. the multiplier and ALU must be able to quickly perform floating point arithmetic. DEPARTMENT OF ECE PAGE NO.or floating-point decision in the past. since the programmer doesn’t generally need to worry about issues such as overflow. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. the SHARC devices are often referred to as "32-bit DSPs.For instance. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. loops. Today. with DSPs the speed is about the same. While fixed-point DSP hardware performs strictly integer arithmetic. The internal architecture of a floating point device is more complicated than for a fixed point device. the instruction set must be larger and so on. a necessity to implement counters. respectively. Comparison between Fixed Point and Floating Point System: TEC Both fixed." rather than just “Floating Point. thus supporting a vastly greater dynamic range than is available with the fixedpoint format.and floating-point indicate. All the registers and data buses must be 32 bits wide instead of only 16.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. For this reason. the latter normalized in the form of scientific notation. TMS320C5x™ and TMS320C2x™ DSPs. All floating point DSPs can also handle fixed point numbers. are based on single16-bit data paths.

Suppose we implement an FIR filter in fixed point. although it does limit how some algorithms must be carried out. Although this is an extreme case. This is a special register that has 2-3 times as many bits as the other memory locations. we need to scale the values being added. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. this quantization noise will simply add. To avoid overflow. while in the SHARC DSPs it contains 80 bits for fixed point use. In traditional microprocessors. and a shorter development cycle. higher dynamic range. DSPs handle this problem by using an extended precision accumulator. The same thing happens when a number is stored as a 16-bit fixed point value. Standard deviation of this quantisation noise is about one-third of the gap size. it illustrates the main point when many operations are carried out on each sample. This strategy works very well. it must be round up or down by a maximum of one-half the gap size i. except that the added noise is much worse. In comparison. Here's the problem.1: Fixed versus floating point.5. . it's bad.000 times less quantisation noise than fixed point. multiply it by the appropriate sample from the input signal. we add noise to the signal. really bad. In the worst case. each time we store a number in floating point notation. For instance. in a 500 coefficient FIR filter. suppose we store the number 10. greatly lowering the signal-to-noise ratio of the system. It can be rated in the form of signal to noise ratio and quantisation noise. DEPARTMENT OF ECE PAGE NO. and will correspondingly add quantization noise on each step. Fixed point DSPs are generally cheaper. the noise on each output sample may be 500 times the noise on each input sample. we loop through each coefficient. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one.000 as a signed integer. this accumulator is just another 16 bit fixed point variable. This is because the gaps between adjacent numbers are much larger. Suppose we store in a 32 bit floating point format. while floating point devices have better precision. while for a fixed point number it is only about ten-thousand to one. Noise is signal is usually represented by its standard deviation. The gap between numbers is one ten-thousandth of the value of the number we are storing. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. floating point has such low quantization noise that these techniques are usually not necessary. To store the number.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. This extended range virtually eliminates round-off noise while the accumulation is in progress. floating point has roughly 3. For instance.e.-47 . To do this. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. in a 16 bit DSP it may have 32 to 40 bits. and add the product to an accumulator. For example.. In other words.

television and other video signals typically use 8 bit ADC and DAC. 12-14 bits per sample is the crossover for using fixed versus floating point. floating point will generally result in a quicker and cheaper development cycle. how the quantization errors are accumulating. In comparison. floating point systems are also easier to develop algorithms for. Most DSP techniques are based on repeated multiplications and additions. making them suitable for fixed point.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. While they can be written in fixed point. In fixed point. For example. the possibility of an overflow or underflow needs to be considered after each operation. if it is more complicated. these issues do not arise in floating point. and the precision of fixed point is acceptable. The next thing to look at is the complexity of the algorithm that will be run . Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point.If it is relatively simple. professional audio applications can sample with as high as 20 or 24 bits.-48 . For instance. are very detailed and can be much more difficult to program. the cost of the product will be reduced. The programmer needs to continuously understand the amplitude of the numbers. the numbers take care of themselves. In the reverse manner. frequency domain algorithms. DEPARTMENT OF ECE PAGE NO. In many applications. the development time will be greatly reduced if floating point is used. and what scaling needs to take place. but a more expensive final product. FIR filtering and other operations in the time domain only require a few dozen lines of code. When fixed point is chosen. In contrast. such as spectral analysis and FFT convolution. . think floating point. and almost certainly need floating point to capture the large dynamic range. but the development cost will probably be higher due to the more difficult algorithms. In comparison. think fixed point.

where Fn. and MRF and MRB are 80 bit accumulators. The RND and SAT options are ways of controlling rounding and register overflow.2: Fixed versus floating point instructions. For instance. MRF = Rx * Ry. These are the multiplication instructions used in the SHARC DSPs. and format. In contrast. DEPARTMENT OF ECE PAGE NO. and Fy are any of the 16 data registers. It could not be any simpler. and may be fractional or integer (F or I). These are the many options needed to efficiently handle the problems of round-off. This table also shows that the numbers may be either signed or unsigned (S or U). look at all the possible commands for fixed point multiplication. scaling. the value of any two registers can be multiplied and placed into another register. and Ry refer to any of the 16 data registers.5. many options are needed for fixed point. The vertical lines indicate options. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry.-49 . . the floating point programmer can spend his time concentrating on the algorithm. Rn. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. While only a single command is needed for floating point. In other words. Fn = Fx * Fy. Fx. and MRB = Rx * Ry. This describes the ways that multiplication can be carried out for both fixed and floating point formats.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. or into one of the extended precision accumulators. Rx. In comparison.

This is mainly driven by consumer products that must have low cost electronics.6. this depends greatly on the application. In comparison. 32-bit floating point has a higher dynamic range. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. About twice as many engineers currently use fixed point as use floating point DSPs. meaning there is a greater difference between the largest number and the smallest number that can be represented. such a . floating point is more common when greater performance is needed and cost is not important. A good example of this is cellular telephones. In (b). The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. When you are in competition to sell millions of your product. a cost difference of only a few dollars can be the difference between success and failure.1: Major trends in DSPs. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs .32-BIT FLOATING POINT PROCESSOR 4. However.6 Trends in DSP: TEC Figure 4. as shown in (c). However. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low.-50 . As shown in (c). For instance. DEPARTMENT OF ECE PAGE NO. about twice as many engineers use fixed point as use floating point DSPs. suppose you are designing a medical imaging system. As illustrated in (a). about 38% of embedded designers have already switched from conventional microprocessors to DSPs. and another 49% are considering the change. such as cellular telephones. floating point is the fastest growing segment.

The second word width is that of the coefficients used in multiplications. . and can be 8. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. Fortunately. In fixed. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. 16 bits for fixed-point. iterated MACs require additional bits for overflow headroom. ensuring greater accuracy in end results. the same as the signal data in DSPs. Three data word widths are important to consider in the internal architecture of a DSP. depending whether single or double precision is used. DEPARTMENT OF ECE PAGE NO. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. but the performance is critical. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow).32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. For a single 16-bit by 16-bit multiplication. The first is the I/O signal word width. or a 48-bit product for a single 24-bit by 24-bit multiplication. For this application. which would go beyond most application requirements in accuracy. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. However. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. First. floating-point coefficients can be 24 bits or 53 bits of precision. exponentiation vastly increases the dynamic range available for the application. this overflow headroom is 8 bits. In spite of the larger number of fixed point DSPs being used. or 32 bits for fixed-point DSPs. a 32-bit product would be needed. in integer as well as real values. Second.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. the internal representations of data in floating-point DSPs are more exact than in fixed-point. the floating point market is the fastest growing segment. While fixed-point coefficients are 16 bits. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). Finally. the cost of the DSP is insignificant. Only a few hundred of the model will ever be sold. 16. at a price of several hundred-thousand dollars each.-51 . Third.point devices. which is 24 bits for floating-point. 4.

Later Integrated Circuits (ICs) were invented.. multiplexes.e. Using design at this level. Using latest CAD tools could solve the problem.. counters. With advent of new technology. for design electronics circuits with assistance of software programs. using this scale of integration people succeeded to make digital subsystems (Microprocessor.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. I/O peripheral devices and etc. At this point design process started getting very complicated. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). This may be leading to development of sophisticated electronic products for both consumer as well as business.) on an IC. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors.e. This level is LSI (Large Scale Integration). One can fabricate a chip contains more than Million of gates. one can create digital sub blocks (adders. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. DEPARTMENT OF ECE PAGE NO.-52 . At this point design process still became critical. In this process. i. because of manual converting the design from one level to other. Designers felt need to automate these processes.) on a chip. CMOS (Complementary Metal Oxide Semiconductor) process technology. This way of designing (using CAD tools) is certainly a revolution in electronic industry. registers. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. . manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. Rapid advances in Software Technology and development of new higher level programming languages taken place. i. and etc. It became very easy to a designer to verify functionality of design at various levels. This created new challenges to digital designers as well as circuit designers.

. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR 5.2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.-53 .3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.

-54 .2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. available from IEEE. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct.3.1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD).The complete language. a need for a standardized hardware description language for the design. 5. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. This new version of the language is known as the IEEE STD 1076-1993. Reprocurement and reuse was also a big issue. This subset is usually sufficient to model most applications . this version of the language is known as the IEEE STD 1076-1987. documentation.3. the language was upgraded with new features. Different chip vendors can provide VHDL descriptions of their components to system designers. DEPARTMENT OF ECE PAGE NO. models written in this language can be verified using a VHDL simulator. Consequently. According to IEEE rules. and many ambiguities present in the 1987 version of the language were resolved. Therefore. It is a hardware description language that can be used to model a digital system at many levels of abstraction. The language can be used as a communication medium between different CAD and CAE tools . The IEEE in the December 1987 standardized VHDL language. The language can be used as exchange medium between chip vendors and CAD tool users. however. ranging from the algorithmic level to the gate level. The official language description appears in the IEEE standard VHDL language Reference manual. 5. The language has also been recognized as an American National Standards Institute (ANSI) standard.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. Thus. and verification of the digital systems was generated. the syntax of many constructs was made more uniform.

N:outBIT). bottom-up. M: in BIT. Each Entity is described using one model.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. can be modeled using the language. B.-55 . As a set of interconnected components (to represent structure) 2. DEPARTMENT OF ECE PAGE NO. and machine-readable. each component. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. SUM) A1: AND2portmap (A. human-readable. Component And2 Port (L. Such a model for the HALF_ADDER entity. or mixed. such as finite –state machine descriptions. 1. End component. Begin X1: Xor2portmap (A. and there are no limitations imposed by the language on the size of the design. Y: in BIT. This model specifies the external view of the device and one or more internal views. CARRY). As a set of concurrent assignment statements (to represent data flow) 3. called an Entity.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. B. Dataflow. In VHDL each device model is treated as a distinct representation of a unique device. and behavioral. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. and Boolean equations. The internal view of the device specifies functionality or structure. 5. . Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. End component. Arbitrarily large designs can be modeled using the language. Various digital modeling techniques. Structural style of modeling: In this one an entity is described as a set of interconnected components. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. Z:out BIT). The language supports flexible design methodologies: top-down. in turn. which contains one external view and one or more internal views. The Entity is thus a hardware abstraction of the actual hardware device. The language supports three basic different styles: Structural. can be modeled as a set of interconnected subcomponents.3. that is a digital can be modeled as asset of interconnected components. It supports both synchronous and asynchronous timing models. The language is publicly available. As a set of sequential assignment statements (to represent behavior) As any combination of the above three.

The data flow model for the half adder is described using two concurrent signal assignment statements . A process statement is a concurrent statement that can appear with in an architecture body.4. 1076-1993 standard. VHDL'93 compiler. and libraries. It comprises three different design entry tools.3. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. Verilog. These sets of sequential statements.32-BIT FLOATING POINT PROCESSOR TEC End ha. SIMULATION TOOL 5. do not explicitly specify the structure of the entity but merely its functionality.3. 13641995 standard.4 INTRODUCTION TO HDL TOOLS 5.2.-56 . several debugging tools. and EDIF and mixed VHDL-Verilog-EDIF designs.In a signal assignment statement. Two component declarations are present in the declarative part of the architecture body. 5.1.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. DEPARTMENT OF ECE PAGE NO. designs. The name of the architecture body is ha . the symbol <=implies an assignment of a value to a signal.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. single simulation kernel. The architecture body is composed of two parts: the declaration part and the statement part. and auxiliary utilities designed for easy management of resource files. which are specified inside a process statement. 5.4. Verilog compiler. 5. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position.4. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. graphical and textual simulation output viewers.4 DATAFLOW STYLE OF MODELING: In this modeling style. The declared components are instantiated in the statement part of the architecture body using component instantiation. 5.the entity declaration for half adder specifies the interface ports for this architecture body.1. .

Resource files attached to the design. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. 1. 2. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. that is: a. and Tcl scripts. 5. SDF files must comply with OVI Standard Delay Format Specification Version 2. Design Browser: The Design Browser window displays the contents of the current design. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). the communication of hardware design and test verification data. It allows you to graphically edit waveforms so as to create desired test vectors.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. HDL Editor: HDL Editor is a text editor designed for HDL source files.1/D1. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs.-57 . It displays specific syntax categories in different colors (keyword coloring).4. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. The editor is tightly integrated with the simulator to enable debugging source code. 5. 3. the maintenance. The contents of the default-working library of the design.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. DEPARTMENT OF ECE PAGE NO. The editor automatically translates graphically designed diagrams into VHDL or Verilog code.1.0. b. The VITAL-compliant models can be annotated with timing data from SDF files. The keyword coloring is also available when HDL Editor is used for editing macro files.0 May 1997). modification and procurement of hardware system. . 4. Perl scripts. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard.

• The Active-HDL simulator provides two simulation engines. In Active-HDL. the compiler analyzes the intermediate VHDL. transistors or gates) and their interconnection.-58 . When you choose a menu command or toolbar button for compilation.bde) In the case of a block or state diagram file. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. Verilog. or EDIF objects declared within a selected region of the current design. 5. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. Verilog.asf) • Block diagram file (. and scripts.EDIF) • State diagram file (. VHDL.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. DEPARTMENT OF ECE PAGE NO. a source file can be on of the following: • VHDL file (. Active-HDL provides three compilers. Verilog.4. d. and EDIF. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. . Cycle-based simulation is significantly faster than event-driven. The structure of the design unit selected for simulation. All Active-HDL tools output their messages to Console. or EDIF file containing HDL code (or net list) generated from the diagram. macros.v) • EDIF net list file (.32-BIT FLOATING POINT PROCESSOR TEC c. A net list is a set of statements that specifies the elements of a circuit (for example. Compilation: Compilation is a process of analysis of a source file. respectively for VHDL. 6. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator.vhd) • Verilog file (.

6.4. .4. and finally produce a bit stream for your device configuration. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.2 Design Entry: • ISE Text Editor .The ISE Text Editor is provided in ISE for entering design code and viewing reports.32-BIT FLOATING POINT PROCESSOR TEC Fig4. including: • HDL (VHDL. DEPARTMENT OF ECE PAGE NO. Verilog HDL.1: Simulation 5. 5. ISE enables you to start your design with any of a number of different source types.4. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities. including ModelSim Xilinx Edition and the HDL Bencher test bench generator.3.-59 . This overview explains the general progression of a design through ISE from start to finish.6. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.5. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.6 SYNTHESIS TOOL: 5.

-60 .3 Implementation: • Translate . Chip Viewer (CPLD only) .The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. CORE Generator . DEPARTMENT OF ECE PAGE NO. macro cell details.The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. Constraints Editor . and memories. and pin assignments. view. placing or routing an FPGA design.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. State CAD State Machine Editor . transitions.6.The Floor planner allows you to view a graphical representation of the FPGA. and after fitting and routing a CPLD design.The PAR program accepts the mapped design. With Timing Analyzer. and Area Group constraints.The Map program maps a logical design to a Xilinx FPGA. PACE .32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor . • • • • • • • . FIFOs. Global logic.The Chip Viewer tool provides a graphical view of the inputs and outputs. and actions in a graphical editor.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create.The Constraints Editor allows you to create and modify the most commonly used timing constraints. Map .4.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. and produces output for the bit stream generator. equations. Fit (CPLD only) .The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. Floor planner . The state machine will be created in HDL. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.The FPGA Editor allows you view and modify the physical implementation. including routing. Place and Route (PAR) . places and routes the FPGA. to system-level building blocks such as filters. Timing Analyzer . FPGA Editor . transforms. • • • • 5.State CAD allows you to specify states. analysis can be performed immediately after mapping. and to view and modify the placed design.

The iMPACT tool generates various programming file formats.4. • • • .-61 .The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices. iMPACT . XPower . DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC 5.6.4 Device Download and Program File Formatting: • BitGen . Integration with ChipScope Pro. and subsequently allows you to configure your device.

DEPARTMENT OF ECE PAGE NO. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. multiplication and division are done using active HDL tool and the results are as follows: 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . .1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. subtraction.-62 .

-63 . DEPARTMENT OF ECE PAGE NO. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format. .2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .32-BIT FLOATING POINT PROCESSOR TEC 6.

.3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO.-64 .3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format.

4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format. DEPARTMENT OF ECE PAGE NO.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.32-BIT FLOATING POINT PROCESSOR TEC 6. . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.-65 .

Basic arithmetic operations such as addition.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. . • 7. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. subtraction.-66 . multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. The Functional-simulation has been successfully carried out with the results matching with the expected ones. • • Procedures for performing basic arithmetic operations are been formed.

In these cases. DEPARTMENT OF ECE PAGE NO. but need to use only a small subset of the range for target acquisition and identification. unpredictable events can occur on an assembly line. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. The greater precision of signal data. . or something might unexpectedly block its range of motion. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. enable imaging systems to achieve a much higher level of recognition and definition for the user. Normally. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. Since the subset must be determined in real time during system operation. Wide dynamic range also plays a part in robotic design. The radar system may be tracking in a range from 0 to infinity. the robot might weld itself to an assembly unit. However. together with the device’s more accurate internal representations of data. however. feedback is well out of the ordinary operating range. The wide dynamic range of a floating-point DSP. Many levels of signal input from light. For instance. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. x-rays. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy.-67 .

& Zaremba. Pacific Grove CA.) Introduction to Computer Architecture. Chicago. M.intel.ieeexplore. Science Research Associates.. (1987) The Implementation of Functional Programming Languages. P. New York McKeeman.2007. Computer. Hayes. H.1109/SNPD. In: 1986 FORML Conf.com . In: Stone. pp. T. pp. Proc. 14(7) 68-78 REFERENCES www. R.org www. 197-210 Jones. (1975) Stack computers. (1981) A survey of high-level language machines in Japan. (Ed. 281-317 Yamamoto...46 www. M. (1986) A 32 bit processor architecture for direct execution of Forth.ieee. DEPARTMENT OF ECE PAGE NO.computer. 28-30 November 1986. S.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman.-68 . 1975. July 1981. Williams. J. W.org/portal/web/csdl/doi/10. Prentice-Hall.

all.all. use IEEE. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc. DEPARTMENT OF ECE PAGE NO. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0).std_logic_arith. y : out std_logic_vector(31 downto 0) ).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.std_logic_unsigned.Compute Ea-Eb -2.all. begin temp:=x. b : in std_logic_vector(31 downto 0).Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.std_logic_1164.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. variable Temp :Std_logic_vector(6 downto 0). --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . end Fadd. use IEEE.-69 .

Two Exponents including Sign variable IR : std_logic_vector(22 downto 0).Sign Of Resulant Exponent variable a.Z : std_logic_vector(1 downto 0).Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. Eb :=Data(30 downto 23). Ma:=MaIn.Resultant Exponent variable Ns : integer.Number Of Shifts variable Ma. -.Internal Register variable Ea. -. -. end if.-70 . Es:=Eb(7) . a :=Acc(31).b : std_logic.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Sign Of Resultant Mantissa variable W. --***************************************************************** --*Equalization of Exponents includes two steps --*1. -.Final Result begin MaIn:=Acc(22 downto 0).Sign Of Two exponents variable s1. -. -. Z :=(a&b). MbIn:=Data(22 downto 0). Ea :=Acc(30 downto 23).s2 : std_logic. -.Mb : std_logic_vector(22 downto 0). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). DEPARTMENT OF ECE PAGE NO. return sum. b :=Data(31).Eb : std_logic_vector(7 downto 0). --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).Sign Of Two mantissas variable Sign : std_logic. else TEC Sum:=Sum. end function. IE:=Eb(6 downto 0). end loop. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). -. -.Subtraction of Exponents --*2. variable X : std_logic_vector(31 downto 0). -. -.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. end loop.Internal Register variable MbIn : std_logic_vector(22 downto 0).Mangitude Of Two mantissas variable ES : std_logic. -.

Ma:=Ma. when "11" => Mb:=MbIn. DEPARTMENT OF ECE PAGE NO. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)).32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Es:=Ea(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). . IE:=Ea(6 downto 0). IE:=Ea(6 downto 0). end loop. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). Ma:=MaIn. IE:=Ea(6 downto 0). end if. IE:=Eb(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. ES:=Ea(7). Ma:=MaIn. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). end loop. IE:=IE.-71 . when "10" => Mb:=MbIn. ES:=Eb(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). when "01" => Mb:=MbIn. Ma:=MaIn. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). else NS:=Ns. end loop. Mb:=Mb.

IE:=IE. elsif(Ea<Eb) then sign:='1'. sign:='1'. elsif(Ma=Mb) then sign:='0'. else NS:=Ns. elsif(Ma<Mb) then sign:='1'. --******************Addition of Mantissas**************************** IR:=Ma+Mb. IE:=Eb(6 downto 0). end if. end loop. when others => Null. W :=(s1&s2). else sign:=sign. s2:=Data(31). if(Ea>Eb) then sign:='0'. Ma:=Ma. end case. Mb:=Mb. end if. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. else sign:=sign. if(Ea>Eb) then sign:='1'. ES:=Eb(7). --***********logic for the sign of the mantissa********************** s1:=Acc(31).32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Ea(7). DEPARTMENT OF ECE sign:='0'. end if. PAGE NO.-72 . case W is when "00" => when "11" => when "01" => when "10" => .

b). end function. elsif(Ma<Mb) then sign:='0'. DEPARTMENT OF ECE PAGE NO. elsif(Ma=Mb) then sign:='0'. end case. end if. end process. else sign:=sign. end Fadd. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'.b) begin y<=float_add(a. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps .-73 * . --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). return X.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. when others => null. else sign:=sign. begin process(a. end if.

--***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0).all. y : out std_logic_vector(31 downto 0)).Compute Ea-Eb 2.-74 .Shift the that has lesser Exponent by Ea-Eb places to the right * 3.all. use IEEE. DEPARTMENT OF ECE PAGE NO. begin temp:=x.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.32-BIT FLOATING POINT PROCESSOR ----1. use ieee.std_logic_1164.std_logic_unsigned. end Fsub.std_logic_arith.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0. use ieee. variable Temp : Std_logic_vector(6 downto 0).all. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout. . b : in STD_LOGIC_VECTOR (31 downto 0).

32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. Eb :=Data(30 downto 23). end function. -.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -. a :=Accout(30).s2 : std_logic. return sum. else Sum:=Sum. --*********************variable Declarations*********************** TEC variable MaIn. -.Mb : std_logic_vector(22 downto 0). Ea :=Accout(30 downto 23).Sign Of Two Mantissas variable sign : std_logic. -.MbIn: std_logic_vector(22 downto 0). end loop.Sign Of Resultant Mantissa variable W. -. -.Mangitude Of Two Mantissas variable ES : std_logic.Subtraction of Exponents * * .Eb : std_logic_vector(7 downto 0). -.Z : std_logic_vector(1 downto 0).-75 .Internal Register variable Ea. -.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). Z :=(a&b). -. -. -.Resultant Exponent variable Ns : integer. variable X : std_logic_vector(31 downto 0). MbIn:=Data(22 downto 0).Sign Of Two Exponents variable s1. end if.Final Result begin MaIn:=Accout(22 downto 0). b :=Data(30).b : std_logic. DEPARTMENT OF ECE PAGE NO.Sign Of Resulant Exponent variable a.Number Of Shifts variable Ma.

elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). ES:=Eb(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). end loop. IE:=IE. else NS:=Ns.-76 . when "01" => Mb:=MbIn. ES:=Ea(7).32-BIT FLOATING POINT PROCESSOR --*2. end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). . IE:=Ea(6 downto 0). TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). DEPARTMENT OF ECE PAGE NO. Ma:=MaIn. Ma:=MaIn. Ma:=Ma. IE:=Eb(6 downto 0). end if. IE:=Ea(6 downto 0).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. Mb:=Mb.

for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). --******************Subtraction of Mantissas************************ IR:=Ma-Mb. DEPARTMENT OF ECE PAGE NO. IE:=IE. IE:=Ea(6 downto 0).32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. ES:=Eb(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). when others => null. end if. ES:=Ea(7). Ma:=MaIn. when "11" => Mb:=MbIn. Ma:=Ma. IE:=Eb(6 downto 0). else NS:=Ns. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)).-77 . end loop. end case. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). TEC Ma:=MaIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. ES:=Eb(7). IE:=Eb(6 downto 0). . ES:=Ea(7). end loop. Mb:=Mb.

DEPARTMENT OF ECE PAGE NO. elsif (Ea<Eb) then sign:='0'. elsif(Ma<Mb) then sign:='0'. s2:=Data(31). end if. when "01"=> if(Ea>Eb)then sign:='0'. end if. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. else sign:=sign.-78 . when "10"=> if (Ea>Eb)then sign:='1'.32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). elsif(Ma<Mb) then sign:='1'. elsif (Ma=Mb) then sign:='0'. end if. elsif (Ma=Mb) then sign:='0'. end if. else sign:=sign. when "11"=> sign:='1'. else sign:=sign. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. W:=(s1&s2). . else sign:=sign. elsif(Ea<Eb) then sign:='1'. case W is when "00"=> sign:='0'.

Multiplication of the Mantissas * * -************************************************************************** library IEEE. end process.all.b) begin y<=float_sub(a.std_logic_unsigned. end case. use IEEE.all.-79 . . b: in STD_LOGIC_VECTOR (31 downto 0).std_logic_1164. y: out STD_LOGIC_VECTOR (31 downto 0) ). --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)). return X. end f_sub. DEPARTMENT OF ECE PAGE NO. end Fmul. use IEEE.b). -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1.Addtion of the Exponents 5. begin process(a. --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0). end function.32-BIT FLOATING POINT PROCESSOR TEC when others=> null.

Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. m1 :=Accout(10 downto 0).s2 : std_logic. variable x : std_logic_vector(31 downto 0). DEPARTMENT OF ECE PAGE NO.e2 : std_logic_vector(7 downto 0). end case.Magnitude O Two Mantissas variable s : std_logic.Eb : std_logic_vector(6 downto 0).b : std_logic. -.Sign Two Exponents variable s1.Magnitude Of Two Exponents variable c : std_logic.sign Two Mantissas variable Ea. -. -. -.Final Result begin Carry:='0'. m2 :=Data(10 downto 0). -. case Z is when "00" => s:='0'.Resultant Mantissa variable carry : std_logic. e2 :=Data(30 downto 23).m2 : std_logic_vector(10 downto 0).Sign Of Resultant Mantissa variable a.Z : std_logic_vector(1 downto 0).Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0). -.-80 . Z :=(s1&s2). -. . s2:=Data(31). when others=> s:='1'. -.Resultant exponent variable m : std_logic_vector(21 downto 0). when "11" => s:='0'.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout. e1 :=Accout(30 downto 23). --************logic for the sign of the Mantissa******************* s1:=Accout(31). -.Two Exponents Icluding Sign variable m1. -.Carry variable W. -.

else c:='0'. when "10" => if(Ea>Eb) then c:='1'. end if. --*************logic for multiplication************************* m:=m1*m2. Eb:=e2(6 downto 0). end if. when "11" => when others => null. when "01" => if(Ea>Eb) then c:='0'. e:=Eb-Ea. elsif(Ea<Eb) then c:='0'. W :=(a&b). .32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). a :=Accout(30). e:=Ea-Eb. e:=Ea+Eb.-81 . DEPARTMENT OF ECE PAGE NO. elsif(Ea<Eb) then c:='1'. e:=Ea+Eb. b :=Data(30). end case. c:='1'. case W is when "00" => c:='0'. e:=Eb-Ea. else c:='0'. e:=Ea-Eb. e:="0000000". e:="0000000".

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

elsif(Ea<Eb) then c:='0'. case Z is when "00" => if(Ea>Eb) then c:='0'. e:=Ea-Eb. elsif(Ea<Eb) then c:='0'. b :=e2(7). . else c:='0'. e:="0000000". elsif(Ea<Eb) then c:='0'. end if. e:=Ea-Eb. else c:='0'. e:=Eb+Ea. e:="0000000".-86 . elsif(Ea<Eb) then c:='1'. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). if(Ea>Eb) then c:='0'. Eb:=e2(6 downto 0). e:=Ea+Eb. end if. e:=Ea+Eb. if(Ea>Eb) then c:='1'. when "10"=> if(Ea>Eb) then c:='1'. e:="0000000". else c:='0'. e:=Eb-Ea. end if. a :=e1(7). Z :=(a&b). e:=Eb-Ea.

end if. end function. return X. end case.-87 . end process. begin process(a. end F_div.b) begin Y<=float_div(a. else c:='0'. DEPARTMENT OF ECE PAGE NO. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)).32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. e:="0000000". TEC . when others=> null.b).

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