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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

. DEPARTMENT OF ECE PAGE NO.-4

the subset of real numbers that a particular FPU supports represents an approximation of the real number system. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. Figure 2. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers. the real-number system comprises the continuum of real numbers from minus infinity (.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. As shown in Figure 1. .1. DEPARTMENT OF ECE PAGE NO. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.-5 . only a subset of the real-number continuum can be used in real-number calculations.) to plus infinity (+ ).32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. As shown at the bottom of Figure 1.

signed integer uses two's complement to make the range include negative numbers. processor and system costs. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. Balancing these factors together. designers can identify the DSP that is best suited for an application.2. Digital Signal Processing can be divided into two categories. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. Motorola manufactures a family of fixed point DSPs that use 24 bits. These refer to the format used to store and manipulate numbers within the devices. the digit string can be of any length. Among the key factors to consider are the computational capabilities required for the application. DSPs enable designers to build innovative features and differentiating value into their products. while floating-point DSPs support either integer or real arithmetic. With unsigned fraction notation. Similarly. There are four common ways that these 216 ' 65.535.767. For instance. although a different length can be used. and ease of development. the stored number can take on any integer value from 0 to 65. Fixed-point Vs floating-point in digital signal processing Fig 2. In common mathematical notation. Lastly.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers.768 to 32. 2.536 levels are spread uniformly between 0 and 1. from -32.-6 . Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. the signed fraction format allows . Software programmable for maximum flexibility and supported by easy-touse. fixed point and floating point. the number is an integer). some specific assumption is made about where the radix point is located in the string. Fixed point DSPs usually represent each number with a minimum of 16 bits. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data.536 possible bit patterns can represent a number. DEPARTMENT OF ECE PAGE NO. In unsigned integer. In fixed-point systems. but decimal fixed point is common in commercial applications. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. the 65. performance attributes. low-cost development tools.

the SHARC DSPs are optimized for both floating point and fixed point operations. it can be placed anywhere relative to the significant digits of the number. The logic for these is different from the ordinary arithmetic functions. respectively. For instance.3. a necessity to implement counters. and floating-point representation can thus be thought of as a computer realization of scientific notation. but small gaps between small numbers. the largest and smallest numbers are ±3. The represented values are unequally spaced between these two extremes.2 ×1038.-7 . The term” floating point” refers to the fact that the radix point can "float".4 ×1038 and ±1. 2. floating point DSPs typically use a minimum of 32 bits to store each value. loops. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . that is. or sometimes the mantissa (see below) or coefficient. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent." rather than just "Floating Point. The radix point is not explicitly included. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. The floating-point operations are incorporated into the design as functions. This is important because it places large gaps between large numbers. A key feature of floating point notation is that the represented numbers are not uniformly spaced. This is known as the significand.967.However. This results in many more bit patterns than for fixed point. the SHARC devices are often referred to as "32-bit DSPs. 2324. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. This position is indicated separately in the internal representation." 2. equally spaced between -1 and 1. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers.754-1985). The speed of floating-point operations is an important measure of performance for computers in many application domains. and signals coming from the ADC and going to the DAC.296 to be exact. it depends on the internal architecture. All floating point DSPs can also handle fixed point numbers.In comparison.294. In the most common format (ANSI/IEEE Std. which is capable of representing real and decimal numbers. Floating point A floating-point number is the one.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. It is measured in” FLOPS”.4. DEPARTMENT OF ECE PAGE NO. For this reason. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). and executes them with equal efficiency.

floating-point numbers achieve their greater range at the expense of precision. DEPARTMENT OF ECE PAGE NO. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. 1 for negative values. The significand is multiplied by the base raised to the power of the exponent. composed as integer. The floating-point format needs slightly more storage (to encode the position of the radix point). 10 or 16. the format of the representations. or to the right of the rightmost digit. These differed in the word sizes. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. Significand is a real number. and the rounding behaviour of operations. this final value is where s is the value of the significand (after taking into account the implied radix point). 2. also referred to as the characteristic or scale.-8 . and e is the exponent.32-BIT FLOATING POINT PROCESSOR TEC significant digit. Symbolically. A signed integer exponent. (This is because the exponent field is in . The length of the significand determines the precision to which numbers can be represented.Fraction. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. so when stored in the same space. with an average error of about 3%. Prior to the IEEE-754 standard. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. b is the base. computers used many different forms of floating-point. which modifies the magnitude of the number.5. These differing systems implemented different parts of the arithmetic in hardware and software. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754.

4. to sum up: 1. and the mantissa. the exponent. The Sign Bit: The sign bit is as simple as it gets.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. and each possible combination of bits represents one real number. 2. or 1023 plus the true exponent for double precision.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. To do this. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. even though there are infinitely many real numbers (even between 0 and 1). The Exponent: The exponent field needs to represent both positive and negative exponents. 1 denotes a negative number. 3. also known as the significand. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. IEEE-754 specifies binary representations for floating point numbers: Table 2. where f is the field of fraction bits. The first bit of the mantissa is typically assumed to be 1. There are many formats that are used for representation of floating point number. Flipping the value of this bit flips the sign of the number. It is composed of an implicit leading bit and the fraction bits. A float is represented using 32 bits. DEPARTMENT OF ECE . The Mantissa: The mantissa. The exponent field contains 127 plus the true exponent for single-precision. So.-9 . The sign bit is 0 for positive. This means that at most 232 possible real numbers can be exactly represented. such as volume ramping in digital sound processing. 1 for negative.) This can be exploited in some applications. a bias is added to the actual exponent in order to get the stored exponent. 0 denotes a positive number.f. represents the precision bits of the number. The exponent's base is two.

the next eight bits are the exponent bits. then V=Infinity .2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. then V=-Infinity If E=255 and F is zero and S is 0. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010).1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero.-10 .5. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. left to right. which may be represented as numbered from 0 to 31.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. S.5.5. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). 'E'. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. Table 2. DEPARTMENT OF ECE PAGE NO. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit.

If E=0 and F is nonzero.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.-11 . DEPARTMENT OF ECE PAGE NO.F) where "1.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.3125 The biased exponent is -2+127=125= (01111101 • 1. If E=0 and F is zero and S is 1.101 = 6.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.101 = -6. then V=-0 If E=0 and F is zero and S is 0. then V=(-1)**S * 2 ** (-126) * (0.F) These are "unnormalized" values.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.0 The biased exponent is . then V=0 In particular. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.

sign bit is 1.3125 131310 = 101001000012 0.1015625 × 2 = 0.5 × 2 = 1.25 The biased exponent: 127+6=133=(10000101 • -1313.312510 = 10100100001.8125 × 2 = 1.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0.203125 × 2 = 0.0 0 1 0 1 1313.01012.3125 is • 0. So -1313. 10 + 127 = 137 = 100010012.010010000101012 × 210.3125 0.-12 . . • -78.40625 0.1015625 0.25 × 2 = 0.40625 × 2 = 0.8125 . = 1.625 × 2 = 1.203125 0.5 The based exponent: 127+5= (10000100 .625 0.5 × 2 = 0.32-BIT FLOATING POINT PROCESSOR TEC • 37. DEPARTMENT OF ECE PAGE NO.25 0.

The number of bits for each field are shown (bit ranges are in square brackets): Table 2. 'E'. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0).5. DEPARTMENT OF ECE .5 0 × 2 = 1.101562510 = 0.32-BIT FLOATING POINT PROCESSOR 0.1015625 is 0 00111101 110100000000000000000000 TEC 2.5 × 2 = 1.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0. The first bit is the sign bit. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001). which may be represented as numbered from 0 to 63. then V=NaN ("Not a number") PAGE NO.25 1 × 2 = 0. left to right. S. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.625 0.-13 . the next eleven bits are the exponent bits.0 1 0.25 0.00011012 = 1.3.5.

53 ~ 10308.F) These are "unnormalized" values. If E=0 and F is nonzero.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). and denormalized numbers (discussed later) which use only a portion of the fraction’s precision. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. Table 2.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable. 15 exponent bits and 112 significand bits. then V=-Infinity If E=2047 and F is zero and S is 0. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent.F) where "1. using a fixed number of digits. then V=-0 If E=0 and F is zero and S is 0. while maintaining good precision. . If E=0 and F is zero and S is 1.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. DEPARTMENT OF ECE PAGE NO.-14 . then V=(-1)**S * 2 ** (-1022) * (0.6. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1.5. floating-point notation allows calculations over a wide range of magnitudes.

There is a largest floating point number.2: Effective Range of IEEE Floating Point Number with Denormalized. Zero 4. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent.53 ~10-323.85 to ~1038. Negative numbers greater than -2-149 (negative underflow) 3. L is the smallest exponent represent able in the system. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. and the smallest possible value for the exponent. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1).6. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2.-15 .32-BIT FLOATING POINT PROCESSOR TEC Table 2. DEPARTMENT OF ECE PAGE NO. P is the precision of the system to P numbers. L. Normalized And Approximate Decimal Values.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. The number of normalized floating point numbers in a system F(B. Positive numbers less than 2-149 (positive underflow) . Approximate Decimal 2127 21023 ~10-44.3 to ~10308. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand. U) (where B is the base of the system. P. There is a smallest positive normalized floating-point number. the range for negative numbers is given by the negation of the above values.

Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. 2.32-BIT FLOATING POINT PROCESSOR 5. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. the number is exactly zero. When this occurs.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. 2.infinity. the largest value which is defined in bias-127 exponent representation. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . However the CPU will have to perform extra arithmetic to read the number when stored in this format. Underflow occurs when the sum of the exponents is more negative than -126.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . the most negative value which is defined in bias-127 exponent representation. DEPARTMENT OF ECE PAGE NO. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. If M = 0. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. When this occurs. Recently. the exponent is set to -127 (E = 0). Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers.-16 . Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately.

. as the smaller number here is a=2. But by using floating point addition this can be avoided to a little extent. DEPARTMENT OF ECE PAGE NO.-17 .32-BIT FLOATING POINT PROCESSOR TEC Fig 2. Floating point addition is analogous to addition using scientific notation. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. For example. Hence the value of number ‘a’ becomes 0.. Normalize the result. Subtraction 3.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. Division 2. Addition 2.e. Add the numbers with decimal points aligned. Now as both the exponent values are same.1. both the numbers are added. They are: 1.8.0225x . Multiplication 4.25x and b= 1. let us consider two numbers a= 2. .340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal. i.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points.

Consider a example in which a =1. 2.234567x and b= 9. If the numbers are represented with both positive and negative sign. then bit 1 is represented for sign. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.8.. a =1.1. The mantissa of both numbers A and B are added. But the normalised result may sometimes carry the required result.8. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. DEPARTMENT OF ECE PAGE NO.00000009876543 x c= 1..2.1. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i.234567x b= 0. Now both the numbers are added.1. then sign of greater number is considered.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: . signB as sign of number B. Thus this case can said to be having rounding errors. ExpA as exponent of number A .876543x and if the addition has to be performed.1.-18 . 2.00000009876543 x 2.876543x after shifting becomes b= 0. b= 9.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.e. ManA as mantissa of number A.2345670 x in which the remaining part (9876543) which is discarded also carries the result. i.8. ExpB as exponent of number B and ManB as mantissa of number B. then the following result may occur: 1.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.e.

2: Flow Chart for Floating Point Adder. If the exponents are stored in biased form. . the numbers are represented in IEEE floating point format.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. If not. Thus. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same.1.-19 . the significand is rounded to the appropriate number of bits required and again normalization is checked. Addition of significands is done. 6. DEPARTMENT OF ECE PAGE NO. 4.8. 5. exception is made. the bias value must be subtracted from the sum 3. If there is an underflow or overflow. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. 2. 1. Firstly. the exponent sum would have doubled the bias.

resulting in a sum which is arbitrarily small. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. The mantissa is always less than 2. Subtraction . When adding numbers of opposite sign. DEPARTMENT OF ECE PAGE NO. The number 2. Normalization in this case may require shifting by the total number of bits in the mantissa.32-BIT FLOATING POINT PROCESSOR TEC 7. Consider addition of the numbers 2.25 becomes: The mantissas are added using integer addition: The result is already in normal form. the result is converted back to signmagnitude form.2. or even zero if the numbers are equal in magnitude.25x and 1.-20 . Thus. After the addition is performed. 2.340625x . 2.8.0625 in IEEE Floating Point Standard is: To align the binary points. Negative mantissas are handled by first converting to 2's complement and then performing the addition. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. then the mantissa must be shifted one bit to the right and the exponent incremented. so the hidden bits can sum to no more than 3 (11). resulting in a large loss of accuracy.25 in IEEE Floating Point Standard is: The number 134. cancellation may occur. If the sum overflows the position of the hidden bit.

both the numbers are added.e. 2. ExpB as exponent of number B and ManB as mantissa of number B.340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if . Hence the value of number ‘a’ becomes 0.25x and b= 1..-21 . ManA as mantissa of number A.1.8.e. Normalize the result. The mantissa of both numbers A and B are subtracted. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2.2. Now as both the exponent values are same.8. Subtract the numbers with decimal points aligned. ExpA as exponent of number A . then sign is represented according to the number i. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. as the smaller number here is a=2.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . The normalised result may contain the required number of digits discarding the unwanted part. i.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.1..2.0225x . DEPARTMENT OF ECE PAGE NO. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. signB as sign of number B..

2. 2.8. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.25 become: The mantissas are subtracted using integer subtraction: . The number 2. Consider subtraction of the numbers 2. 2.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign.340625x . 6.-22 . the exponent sum would have doubled the bias. DEPARTMENT OF ECE PAGE NO. 2. If there is an underflow or overflow.0625 in IEEE Floating Point Standard is: To align the binary points. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. Thus. If not. the significand is rounded to the appropriate number of bits required and again normalization is checked. If the exponents are stored in biased form. exception is made. Thus.2. 4. The numbers are represented in IEEE floating point format. the bias value must be subtracted from the sum 3. Subtraction of significands is done. 5.25 in IEEE Floating Point Standard is: The number 134.25x and 1.

then the result would be Z=X.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form.. At this point. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. If both the numbers X and Y are non zeros. In the first step. If overflow occurs. then the following steps can be followed: Exponents of both the numbers are checked.3. number X is checked. If it is ‘0’. DEPARTMENT OF ECE PAGE NO. then the mantissa must be shifted one bit to the right and the exponent incremented.8.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction.8.2. Flow chart for floating point subtraction: Subtract significand si Fig 2.-23 . If not then the result is normalized. consider two numbers X and Y and the resultant be Z. If the sum overflows the position of the hidden bit.2. 2. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . If number X is not ‘0’. If the exponents are same. If it is ‘0’ then the resultant solution Z would be Y i. then the significands of numbers X and Y are subtracted. Z=Y. If the significand is zero then it is returned if not significand overflow is checked. If overflow occurred then overflow is reported and returned.e. then number Y is checked.

5x : Perform unsigned integer multiplication of the mantissas. If underflow occurred then it is reported if not the normalized result is given out.5 in IEEE FPS format is: . to multiply 1. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.0 in IEEE FPS format is: The number 9. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z.3.1. The number 18.8x times 9. 2.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. 2. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers.-24 .8. 1.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.5 ----17.8 x 9.3. If the exponents are not same. DEPARTMENT OF ECE PAGE NO.8. For example. if the significand is not zero then subtraction and further process is carried out. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.

The sign of the result is the xor of the sign bits of the two numbers. the result is: 2. the mantissa must be shifted right and the exponent incremented. If the position of the hidden bit overflows.8. Block diagram of floating point multiplication: . DEPARTMENT OF ECE PAGE NO. the mantissa is: The biased-127 exponents are added. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.2.3.-25 . When the fields are assembled in IEEE FPS format.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in ().

Sign of the result is given by performing xor operation of signA and signB. Thus. DEPARTMENT OF ECE PAGE NO.8.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . manA as mantissa of number A.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. If the exponents are stored in biased form.8.3. expB as exponent of number B and manB as mantissa of number B.3. The exponents of both the numbers are added and subtracted from the bias 127. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. Resultant mantissa is truncated and normalized to fit for the IEEE format. XOR operation for sign bit can be given as follows: Table 2.3. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. the exponent sum would have doubled the bias.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. The mantissa of both numbers A and B are multiplied.-26 . then the exponents are added and a bias of 127 is subtracted from the result. At the first step.8.3. . expA as exponent of number A . If both the numbers X and Y are not zero. signB as sign of number B.

4. The resultant sign bit would be the xor operation of sign bits of X and Y. . Hence the result can be given as 1. Division Consider an example of dividing a=0.3: Flow Chart For Floating Point Multiplication.5. DEPARTMENT OF ECE PAGE NO.3 and b= 0.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned. 2.3 0. Exponent of a is 2 and exponent of b is 3. When the division of both significands are done then the quotient would be 1.2 . in general floating point division the exponents of both the numbers are subtracted and the significands are divided. i.5.-27 . So resultant exponent would be 2-3=-1.e.3.2 =1. Fig 2..8.5 . 0.8.

1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . ManA as mantissa of number A. 2. If anyone number of the two are negative. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement.-28 . then the resultant sign is also positive and is represented by bit ‘0’. signB as sign of number B. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. ExpA as exponent of number A . a 24 bit quotient is produced. ExpB as exponent of number B and ManB as mantissa of number B.1. When divided by a 24 bit divisor.32-BIT FLOATING POINT PROCESSOR TEC 2. DEPARTMENT OF ECE PAGE NO. In the first step. As in floating point multiplication. then the result is also negative is represented by bit ‘1’. Set the sign of the result. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. Normalize the result. Block diagram for floating point division: Fig 2. Special . The mantissa of both numbers A and B are divided.4.4.8. If both the numbers are either positive or negative.8. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. The exponents are subtracted and biased using the bias value. Subtract the exponent of the divisor from the exponent of the dividend.8.4.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa.

Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero.4.3 S E and b= 0. or NaN.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. .8. Considering a=0. in this case as larger number has to be subtracted from smaller number. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned. Number X and Y are checked.3 0. DEPARTMENT OF ECE PAGE NO.2 can be represented as M 010000001(0)11000000000000000000000 0. This value is called Not A Number.-29 .Then the steps that occur are: 1. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . For this. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked.3. 2.

some form of rounding is required..g. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit. and it may be reported as 0. .3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. digits may flow off the right end of the significand. DEPARTMENT OF ECE PAGE NO. If not the mantissas are divided and truncated and normalized result is given out. this may be designated as +∞ or -∞.This means that the number is too small to be represented.9. then those conditions are reported. In some systems. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. 2.8. Fig 2.200 is less than .32-BIT FLOATING POINT PROCESSOR TEC 3. rounding errors occur as a result of the limited precision of the mantissa .-30 .127). • Significand underflow: In the process of aligning significands. If they are present. Rounding Error In floating point arithmetic.4. As we shall discuss.

RN is generally preferred and introduces less systematic error than the other rules. Same as truncation in 2's complement. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). the relative error is approximately since For denormalized numbers (E = 0). relative errors increase as the magnitude of the number decreases toward zero. However. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. Break ties by choosing the least significant bit = 0. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. Normalization By normalization. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. RP: Round toward Positive infinity. RM: Round toward minus infinity. highest precision can be achieved. To efficiently use the bits available for the significand.10. For normalized floating point numbers. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. The least significant 24 bits are discarded. For numbers in IEEE FPS format. The value can be kept unchanged by adjusting the exponent accordingly. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. Same as truncation in sign-magnitude. The size of the absolute error is proportional to the magnitude of the number. RZ: Round toward Zero.-31 . .

Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit.32-BIT FLOATING POINT PROCESSOR TEC Moreover.11. resulting 1.. By the end of the operation. the bits need to be truncated to guard bit Chopping: simply drop all . in the following the default normalization does not assume this implicit 1 unless otherwise specified. as the MSB of the significand is always 1. multiplication). Truncation To retain maximum accuracy. all extra bits during operation (called guard bits) are kept (e. extra guard bits are kept during operation.-32 . to avoid possible confusion. bits are used in final representation of a bits by one of the three methods. The first bit 1 before the decimal point is implicit. Zero is represented by all 0's and is not (and cannot be) normalized. a 4-bit exponent field and a 9-bit significand field): 2. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. DEPARTMENT OF ECE PAGE NO. If we assume number.g. it does not need to be shown explicitly. The actual value represented is However.

e. . Interpretation: Value represented by guard bits is greater than 0. (no matter Von Neumann Rounding: If at least one of the guard bits is 1. 3.5 round up.-33 .. DEPARTMENT OF ECE PAGE NO. the Von Neumann rounding error is unbiased. we say this truncation error is biased. set whether it is originally 0 or 1). otherwise do nothing. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. is always greater than 0. .32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. Two worst cases Both two cases can be summarized as i. add 1 to LSB .

c) If the highest guard bit is 1 and the rest guard bits are all 0. round up: Interpretation: Value represented by guard bits is 0. drop all guard bits.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0. Interpretation: Value represented by guard bits is smaller than 0. .5 round down. DEPARTMENT OF ECE PAGE NO. The rounding error of these cases can summarized as .-34 . the rounding depends on the LSB : if . round down: or if .5 either up or down with equal probability (50%). it is randomly rounded .

The logic for these is different from the ordinary arithmetic functions. 1985 floating point standard representation before any sort of operations are conducted on them. 1111 and negative numbers are represented by binary values less than it. I. 1111. The logic for floating point addition. The MSB is the sign-bit i. subtraction. The exponent in this IEEE standard is represented in excess-127 format. The next eight bits are that of the exponent. the exponent obtained by balancing operations is added to 0111.3 Floating Point Functions A floating-point number is the one. The above representation is the IEEE-784 1985 standard representation. . The numbers in contention have to be first converted into the standard IEEE 784.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . Therefore zero is represented by 0111. which is capable of representing real and decimal numbers.e. Positive numbers are represented by binary values greater than 0111. the sign of the floating point number.-35 . 1111. DEPARTMENT OF ECE PAGE NO. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. multiplication and division is presented in the following pages.e. The floating-point operations are incorporated into the design as functions.

32-BIT FLOATING POINT PROCESSOR TEC 3. These numbers are distinct. This is done till the lower exponent becomes equal to the higher one. These numbers are stored into the memory from which they are read and processed.-36 . we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. So. namely Accumulator and the Temp register that loads the value appearing on the data bus. The mantissas are then added to each other and the result is then stored in a temporary register. DEPARTMENT OF ECE PAGE NO. Once the exponents are normalized. we have to first normalize their exponents. • • . The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. Now the numbers from the memory are loaded into two registers.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. So to add their mantissa’s.

The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. namely Accumulator and the Temp register that loads the value appearing on the data bus. So to add their mantissa’s. DEPARTMENT OF ECE PAGE NO. Once the exponents are normalized. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. So. These numbers are stored into the memory from which they are read and processed.-37 . Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. These numbers are distinct. we have to first normalize their exponents. This is done till the lower exponent becomes equal to the higher one. . The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. The mantissas are then subtracted and the result is stored in a temporary register.32-BIT FLOATING POINT PROCESSOR 3. Now the numbers from the memory are loaded into two registers.

so that the result is restricted to not more than 24-bits. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. There is however a limitation to this operation. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. the resulting exponent and the sign of the result that is calculated separately.32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. So each input should not exceed 12-bits in length.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. The final output is obtained by concatenating the product of the mantissas.-38 . • • • .

Now both the numbers in the IEEE-784 standard format are compared. we put a zero in the quotient.-39 . The result is stored in Temp. Now the first 24-bits from the MSB are compared with the divisor. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. • • • • • . This is to ensure that whatever comes as the result is after the decimal point. we append it with the exponent value and the Sign of the division that are calculated separately. Once the quotient is full. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. First the exponents are directly added or subtracted depending on which is bigger. till the quotient is full. And if it is zero.32-BIT FLOATING POINT PROCESSOR TEC 3. The decimal is assumed to be before the MSB of the resulting quotient. Apart from that the final sign of the division is calculated separately. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. The convention here is that the Numerator should be always less than the denominator.4 Floating Point Division • • • • This is more complicated then Multiplication. DEPARTMENT OF ECE PAGE NO. Now since the greater of the two numbers is decided. The logic for floating point division is as follows. We initiate a counter and carry this process for 24 times. if the MSB or the 49th bit is one than we add a one in the quotient.

All microprocessors can perform both tasks. Mathematical calculation used in science. DSPs can perform the mathematical calculations needed in digital signal processing. however it is difficult or expensive to make a device that is optimized for both. Consider another example of how a document is printed from a word processor. These devices have seen tremendous growth in the last decade. 32 or 64 bits called registers. engineering and digital signal processing. and so on. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. Clock frequency is generally a multiple of the system frequency. the program moves the data from . Data manipulations involve storing and sorting information. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. A<B . such as the size of the instruction set and how it interrupts are handled. data is temporarily stored in small. product life time. For instance. With each clock peak. and testing for inequalities (A=B. 16. consider a word processing program. DEPARTMENT OF ECE PAGE NO. The clock speed (also called cycle). Computers are extremely capable in two broad areas 1. The basic task is to store the information. the overall number of registers can vary from about ten to many hundreds. corresponds to the number of pulses per second. These tasks are accomplished by moving data from one location to another.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. Depending on the type of processor. etc). The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). There are marketing issues involved: development and manufacturing cost.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. meaning a multiple of the motherboard frequency. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. There are technical tradeoffs in the hardware design. written in Hertz (Hz). the processor performs an action that corresponds to an instruction or a part thereof.-40 . finding use in everything from cellular telephones to advanced scientific instruments. competitive position.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. When the processor executes instructions. 4. When this code is detected. Data manipulation such as word processing and database management 2. local memory locations of 8.

. y[n]. While there is some data transfer and inequality evaluation in this algorithm. the math operations dominate the execution time. the input signal is referred to by x [ ]. While mathematics is occasionally used in this type of application. .. depending on the application.. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. Using standard notation. consider the implementation of an FIR digital filter.. In comparison.-41 .e. The task is to calculate the sample at location n in the output signal. such as to keep track of the intermediate results and control the loops. DEPARTMENT OF ECE PAGE NO. For example. it is infrequent and does not significantly affect the overall execution speed. there may only be a few coefficients in the filter kernel... while the output signal is denoted by y [ ]...32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer.. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: . the most common DSP technique. i.... This is simply saying that the input signal has been convolved with a filter kernel consisting of: .

DEPARTMENT OF ECE PAGE NO. the DSP must be able to maintain a sustained throughput of 20. each sample in the output signal . After shaking is over. The key point in off-line processing is that all of the information is simultaneously available to the processing program. so as the cost .3. For example. Hence execution time is critical for selecting the proper device. consider a designing of an audio signal in DSP system such as a hearing aid.. converting a word processing document from one form to another. and summing the products. Digital signal processors are designed to quickly carry out FIR filters and similar techniques.-42 . 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers.2.32-BIT FLOATING POINT PROCESSOR TEC Fig4. This is common in scientific research and engineering. the traditional speed advantage of integer operations over floating point operations is decreasing. not having a defined start or end. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. the information may be read into a computer and analysed in some way.000 samples per second. The disadvantages of 32-bit processors are cost and system complexity. whereas 32-bit processors are naturally suited to the size of the data elements.. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. However. Off-line processing is a realm of personal computers and mainframes. 4. For instance. with the advent of very fast floating point processing hardware. There are a few reasons for why to not to make it faster than necessary because as speed increases. say. most DSPs are used in applications where the processing is continuous. There is less room on-chip for extra features such as hardware multipliers. the entire input signal resides in the computer at the same time. design difficulty and so on.x[n-1]. In FIR filtering .. Difference between off-line processing and real time processing: In off-line processing. as well as the algorithms that can be applied. Floating point calculations also require a 32-bit processor for good efficiency. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds.. a geophysicist might use a seismometer to record the ground movement during the earthquake.1: Graphical representation of FIR digital filter design.by the filter kernel coefficients. but these items will appear as chip fabrication technology gets denser. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors.. power consumption. floating point math must often be used to reduce the cost of programming a project. If suppose you are launching your desktop computer on some task . DSPs must also have a predictable execution time. . Also. If the digital signal is being received at 20. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. You simply wait for the action to be completed before you give the computer its next assignment In comparison. . In addition to performing mathematical calculations very rapidly. is found by multiplying samples from the input signal. x[n]. In these cases a 16-bit processor may suffice.000 samples per second.x[n-2]. and to support code written in high level languages.y[n].

a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. . This is the world of digital signal processors. we might place the filter coefficients in program memory. 4. the output signal is produced at the same time that the input signal is acquired. the binary codes that go into the program sequencer. DEPARTMENT OF ECE PAGE NO. The basis of Harvard design is that the data memory bus is busier than the program memory bus. at a 40 MHz clock speed. the data transfer rate is an incredible 240Mbytes/second. they may input a group of samples perform the algorithm and output a group of samples. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. While the SHARC DSPs are optimized in dozens of ways. Most present day DSPs use this dual bus architecture. with separate buses for each. For instance.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. such as samples from the input signal and filter coefficients as well as program instructions. Different architectures available are: Von Neumann Architecture.4. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. while only one binary value (the program instruction) is passed over the program memory bus. Likewise. Real time applications input a sample. Harvard architecture has separate memories for data and program instructions.-43 . For example. Super Harvard Architecture (SHARC). there are two serial ports that operate at 40 Mbits/second each. over and over. and an I/O controller. this is needed in telephone communication. Most of the computers are using this architecture today. improving the speed over the single bus design. This includes data. To improve upon this situation. perform the algorithm and output a sample. Since the buses operate independently. we start by relocating part of the "data" to program memory. These are extremely high speed connections. program instructions and data can be fetched at the same time. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. two areas are important enough to be included are an instruction cache. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). The SHARC DSPs provides both serial and parallel communications ports. while keeping the input signal in data memory. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. When two numbers are multiplied. two binary values (the numbers) must be passed over the data memory bus. When all six parallel ports are used together. For instance. Harvard Architecture. while six parallel ports each provide a 40 Mbytes/second data transfer. For example. Alternatively. hearing aids and radar.

32-BIT FLOATING POINT PROCESSOR TEC Figure 4. on additional executions of the loop. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. In comparison. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. This allows . all DSPs can interface with external converters through serial or parallel ports.4.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. a feature called mixed signal. this efficient transfer of data is called a high memory-access bandwidth. such as instructions. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. and the program instruction comes from the instruction cache.-44 . DSP algorithms generally spend most of their execution time in loops. This means that the same set of program instructions will continually pass from program memory to the CPU. However. the program instructions can be pulled from the instruction cache. In the jargon of the field. However. DEPARTMENT OF ECE PAGE NO. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. Some DSPs have on-board analog-to-digital and digital-toanalog converters. providing higher speed. providing an additional interface to off-chip memory and peripherals. the program instructions must be passed over the program memory bus. the Harvard architecture uses separate memories for data and instructions. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. the coefficient comes over the program memory bus. The first time through a loop. This is a small memory that contains about 32 of the most recent program instructions.

multiplies them. and similar functions. subtraction. extracting and depositing segments. In a single clock cycle. Compare this architecture with the tasks needed to implement an FIR filter. This simplified diagram is of the Analog Devices SHARC DSP. specifying where the information is to be read from or written to.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. data from registers 8-15 can be passed to the ALU. OR. Digital Signal Processors are designed to implement tasks in parallel. a multiplier. one for each of the two memories. These control the addresses sent to the program and data memories. logical operations (AND. DEPARTMENT OF ECE PAGE NO. and the two results returned to any of the 16 registers. for 32 bit data. accessible at 40Mwords/second (160 Mbytes/second). XOR.-45 . absolute value. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. All of the steps within the loop can be executed in a single clock cycle. data from registers 0-7 can be passed to the multiplier. an arithmetic logic unit (ALU). and is quite transparent to the programmer. The multiplier takes the values from two registers. In simpler microprocessors this task is handled as an inherent part of the program sequencer. Elementary binary operations are carried out by the barrel shifter. At the top of the diagram are two blocks labelled Data Address Generator (DAG).2: Typical DSP architecture. such as shifting.4. conversion between fixed and floating point formats. The ALU performs addition. NOT). and a barrel shifter. . and so on. rotating. and places the result into another register. Fig 4. The math processing is broken into three sections.

. and signals coming from the ADC and going to the DAC. Comparison between Fixed Point and Floating Point System: TEC Both fixed. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers.and floating-point indicate. though. are based on single16-bit data paths. a necessity to implement counters. As the terms fixed. However. respectively. the SHARC devices are often referred to as "32-bit DSPs.-46 . Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. For this reason.32-BIT FLOATING POINT PROCESSOR 4. and an 8-bit exponent. TMS320C5x™ and TMS320C2x™ DSPs." rather than just “Floating Point. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. DEPARTMENT OF ECE PAGE NO. since the programmer doesn’t generally need to worry about issues such as overflow. the fundamental difference between the two types of DSPs is in their respective numeric representations of data.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. All floating point DSPs can also handle fixed point numbers. Fixed point DSPs are cheaper than floating point devices. In addition. the SHARC DSPs are optimized for both floating point and fixed point operations. it depends on the internal architecture . However. All the registers and data buses must be 32 bits wide instead of only 16.or floating-point decision in the past. The internal architecture of a floating point device is more complicated than for a fixed point device. loops. the multiplier and ALU must be able to quickly perform floating point arithmetic. floating-point DSPs support either integer or real arithmetic. and executes them with equal efficiency. underflow and round-off. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. with DSPs the speed is about the same. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. While fixed-point DSP hardware performs strictly integer arithmetic. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. Tradeoffs of cost and ease of use often heavily influenced the fixed.For instance. a result of the hardware being highly optimized for math operations. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. with architectures designed for handheld and control applications. Double-width precision achieves much greater precision and dynamic range at the expense of speed. floating point programs often have a shorter development cycle. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). the latter normalized in the form of scientific notation." fixed point arithmetic is much faster than floating point in general purpose computers. TMS320C64x™ DSPs. the instruction set must be larger and so on.5. By contrast. including a 53-bit mantissa and an 11-bit exponent). Today. since it requires multiple cycles for each operation.

32-BIT FLOATING POINT PROCESSOR TEC Figure 4. For instance. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. In traditional microprocessors. This extended range virtually eliminates round-off noise while the accumulation is in progress. although it does limit how some algorithms must be carried out. in a 500 coefficient FIR filter. this quantization noise will simply add. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. This strategy works very well. For example. Here's the problem. it's bad. . For instance. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. the noise on each output sample may be 500 times the noise on each input sample. really bad.5. This is because the gaps between adjacent numbers are much larger. it must be round up or down by a maximum of one-half the gap size i. multiply it by the appropriate sample from the input signal. greatly lowering the signal-to-noise ratio of the system. To store the number. Fixed point DSPs are generally cheaper. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. In the worst case. while floating point devices have better precision. Standard deviation of this quantisation noise is about one-third of the gap size. The same thing happens when a number is stored as a 16-bit fixed point value. Noise is signal is usually represented by its standard deviation. and will correspondingly add quantization noise on each step. In comparison. it illustrates the main point when many operations are carried out on each sample. while for a fixed point number it is only about ten-thousand to one. we need to scale the values being added. This is a special register that has 2-3 times as many bits as the other memory locations. higher dynamic range.1: Fixed versus floating point. Although this is an extreme case.000 times less quantisation noise than fixed point. To avoid overflow. floating point has such low quantization noise that these techniques are usually not necessary. while in the SHARC DSPs it contains 80 bits for fixed point use. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. this accumulator is just another 16 bit fixed point variable.. floating point has roughly 3.000 as a signed integer. It can be rated in the form of signal to noise ratio and quantisation noise. suppose we store the number 10. and add the product to an accumulator. in a 16 bit DSP it may have 32 to 40 bits. DEPARTMENT OF ECE PAGE NO. except that the added noise is much worse. DSPs handle this problem by using an extended precision accumulator.e. In other words. To do this. and a shorter development cycle. each time we store a number in floating point notation.-47 . we add noise to the signal. we loop through each coefficient. Suppose we implement an FIR filter in fixed point. The gap between numbers is one ten-thousandth of the value of the number we are storing. Suppose we store in a 32 bit floating point format.

the numbers take care of themselves. When fixed point is chosen. For instance. FIR filtering and other operations in the time domain only require a few dozen lines of code. but the development cost will probably be higher due to the more difficult algorithms.If it is relatively simple. The programmer needs to continuously understand the amplitude of the numbers. the cost of the product will be reduced. and almost certainly need floating point to capture the large dynamic range. if it is more complicated. DEPARTMENT OF ECE PAGE NO. In comparison. In fixed point. these issues do not arise in floating point. While they can be written in fixed point. television and other video signals typically use 8 bit ADC and DAC. The next thing to look at is the complexity of the algorithm that will be run .32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. the possibility of an overflow or underflow needs to be considered after each operation. floating point will generally result in a quicker and cheaper development cycle. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. think fixed point. In comparison.-48 . Most DSP techniques are based on repeated multiplications and additions. and the precision of fixed point is acceptable. such as spectral analysis and FFT convolution. how the quantization errors are accumulating. In many applications. 12-14 bits per sample is the crossover for using fixed versus floating point. frequency domain algorithms. and what scaling needs to take place. . For example. but a more expensive final product. are very detailed and can be much more difficult to program. making them suitable for fixed point. professional audio applications can sample with as high as 20 or 24 bits. In contrast. think floating point. In the reverse manner. the development time will be greatly reduced if floating point is used. floating point systems are also easier to develop algorithms for.

The vertical lines indicate options.2: Fixed versus floating point instructions. It could not be any simpler. In contrast. and may be fractional or integer (F or I). The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. This table also shows that the numbers may be either signed or unsigned (S or U). In comparison. Rn. In other words. Rx. or into one of the extended precision accumulators. This describes the ways that multiplication can be carried out for both fixed and floating point formats. the floating point programmer can spend his time concentrating on the algorithm. many options are needed for fixed point. look at all the possible commands for fixed point multiplication. scaling.5. While only a single command is needed for floating point. These are the multiplication instructions used in the SHARC DSPs. DEPARTMENT OF ECE PAGE NO. These are the many options needed to efficiently handle the problems of round-off. For instance. MRF = Rx * Ry. . The RND and SAT options are ways of controlling rounding and register overflow. where Fn. and Fy are any of the 16 data registers.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. Fn = Fx * Fy. and format. and Ry refer to any of the 16 data registers. and MRB = Rx * Ry. and MRF and MRB are 80 bit accumulators. Fx. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry.-49 . the value of any two registers can be multiplied and placed into another register.

a cost difference of only a few dollars can be the difference between success and failure. suppose you are designing a medical imaging system. DEPARTMENT OF ECE PAGE NO.6.6 Trends in DSP: TEC Figure 4. floating point is the fastest growing segment. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. this depends greatly on the application.1: Major trends in DSPs. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . and another 49% are considering the change. For instance. about twice as many engineers use fixed point as use floating point DSPs. as shown in (c).-50 . such a . In (b). meaning there is a greater difference between the largest number and the smallest number that can be represented. However. A good example of this is cellular telephones. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low.32-BIT FLOATING POINT PROCESSOR 4. such as cellular telephones. When you are in competition to sell millions of your product. 32-bit floating point has a higher dynamic range. In comparison. As shown in (c). This is mainly driven by consumer products that must have low cost electronics. However. floating point is more common when greater performance is needed and cost is not important. As illustrated in (a). The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. About twice as many engineers currently use fixed point as use floating point DSPs.

Three data word widths are important to consider in the internal architecture of a DSP. and can be 8. which is 24 bits for floating-point. In fixed. However. a 32-bit product would be needed. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). For a single 16-bit by 16-bit multiplication.-51 . the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. Third. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. or 32 bits for fixed-point DSPs. this overflow headroom is 8 bits. First. which would go beyond most application requirements in accuracy. While fixed-point coefficients are 16 bits. In spite of the larger number of fixed point DSPs being used. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. ensuring greater accuracy in end results.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. Second. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. 16. . 4. depending whether single or double precision is used. the same as the signal data in DSPs. For this application. the floating point market is the fastest growing segment. The first is the I/O signal word width. the internal representations of data in floating-point DSPs are more exact than in fixed-point. Fortunately. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). the cost of the DSP is insignificant. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. Finally. DEPARTMENT OF ECE PAGE NO. but the performance is critical. 16 bits for fixed-point. or a 48-bit product for a single 24-bit by 24-bit multiplication. The second word width is that of the coefficients used in multiplications.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. at a price of several hundred-thousand dollars each. in integer as well as real values. Only a few hundred of the model will ever be sold.point devices. exponentiation vastly increases the dynamic range available for the application. iterated MACs require additional bits for overflow headroom. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. floating-point coefficients can be 24 bits or 53 bits of precision.

. Using design at this level. counters. multiplexes. for design electronics circuits with assistance of software programs.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. one can create digital sub blocks (adders.e. DEPARTMENT OF ECE PAGE NO. One can fabricate a chip contains more than Million of gates. because of manual converting the design from one level to other. This may be leading to development of sophisticated electronic products for both consumer as well as business. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. Designers felt need to automate these processes. Rapid advances in Software Technology and development of new higher level programming languages taken place.e. and etc.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. I/O peripheral devices and etc.) on a chip. At this point design process started getting very complicated. This level is LSI (Large Scale Integration). This created new challenges to digital designers as well as circuit designers. . Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. i. Using latest CAD tools could solve the problem. using this scale of integration people succeeded to make digital subsystems (Microprocessor. At this point design process still became critical. CMOS (Complementary Metal Oxide Semiconductor) process technology.) on an IC. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). It became very easy to a designer to verify functionality of design at various levels. i.. In this process. registers. This way of designing (using CAD tools) is certainly a revolution in electronic industry.-52 . People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. Later Integrated Circuits (ICs) were invented. With advent of new technology. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical.

. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR 5.2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.-53 .

Thus. and verification of the digital systems was generated. According to IEEE rules.-54 .1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). This new version of the language is known as the IEEE STD 1076-1993. 5. The language can be used as a communication medium between different CAD and CAE tools . This subset is usually sufficient to model most applications . It is a hardware description language that can be used to model a digital system at many levels of abstraction. Consequently. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. the language was upgraded with new features.3. The official language description appears in the IEEE standard VHDL language Reference manual. and many ambiguities present in the 1987 version of the language were resolved. the syntax of many constructs was made more uniform. ranging from the algorithmic level to the gate level. available from IEEE. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. however. The IEEE in the December 1987 standardized VHDL language. documentation.The complete language. Reprocurement and reuse was also a big issue.3. The language has also been recognized as an American National Standards Institute (ANSI) standard. The language can be used as exchange medium between chip vendors and CAD tool users. Therefore. Different chip vendors can provide VHDL descriptions of their components to system designers. 5.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. models written in this language can be verified using a VHDL simulator. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. this version of the language is known as the IEEE STD 1076-1987. a need for a standardized hardware description language for the design. DEPARTMENT OF ECE PAGE NO.

The language supports flexible design methodologies: top-down. and there are no limitations imposed by the language on the size of the design. called an Entity. DEPARTMENT OF ECE PAGE NO. and machine-readable. Y: in BIT. M: in BIT. N:outBIT). Arbitrarily large designs can be modeled using the language. Z:out BIT). and Boolean equations. in turn. End component. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. Component And2 Port (L. Various digital modeling techniques. that is a digital can be modeled as asset of interconnected components. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. Begin X1: Xor2portmap (A. As a set of concurrent assignment statements (to represent data flow) 3. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. Dataflow. Such a model for the HALF_ADDER entity. bottom-up. CARRY). B.3. SUM) A1: AND2portmap (A. each component. 1. This model specifies the external view of the device and one or more internal views. In VHDL each device model is treated as a distinct representation of a unique device. End component. The language is publicly available. As a set of sequential assignment statements (to represent behavior) As any combination of the above three.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. It supports both synchronous and asynchronous timing models. B. Structural style of modeling: In this one an entity is described as a set of interconnected components. 5. . or mixed. The language supports three basic different styles: Structural. The Entity is thus a hardware abstraction of the actual hardware device. such as finite –state machine descriptions. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions.-55 . As a set of interconnected components (to represent structure) 2. human-readable. can be modeled using the language. The internal view of the device specifies functionality or structure. Each Entity is described using one model.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. can be modeled as a set of interconnected subcomponents. and behavioral. which contains one external view and one or more internal views.

4.3. These sets of sequential statements.-56 . EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. the symbol <=implies an assignment of a value to a signal. SIMULATION TOOL 5. Two component declarations are present in the declarative part of the architecture body. A process statement is a concurrent statement that can appear with in an architecture body. 5.2. and auxiliary utilities designed for easy management of resource files. DEPARTMENT OF ECE PAGE NO. Verilog. do not explicitly specify the structure of the entity but merely its functionality. 5.the entity declaration for half adder specifies the interface ports for this architecture body. 5. Verilog compiler.1.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. It comprises three different design entry tools. designs. several debugging tools. 1076-1993 standard. and libraries. 5. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std.32-BIT FLOATING POINT PROCESSOR TEC End ha.4 DATAFLOW STYLE OF MODELING: In this modeling style. VHDL'93 compiler. The data flow model for the half adder is described using two concurrent signal assignment statements . the flow of data through the entity is expressed primarily using concurrent signal assignment statements.3.4 INTRODUCTION TO HDL TOOLS 5. which are specified inside a process statement. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std.4. graphical and textual simulation output viewers. single simulation kernel. The declared components are instantiated in the statement part of the architecture body using component instantiation. The name of the architecture body is ha .1. 13641995 standard.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL.4.In a signal assignment statement. The architecture body is composed of two parts: the declaration part and the statement part. . and EDIF and mixed VHDL-Verilog-EDIF designs. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position.

State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. 5. the maintenance. Design Browser: The Design Browser window displays the contents of the current design. The contents of the default-working library of the design. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. 3.1/D1. modification and procurement of hardware system. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. Perl scripts. the communication of hardware design and test verification data. DEPARTMENT OF ECE PAGE NO. 1. The VITAL-compliant models can be annotated with timing data from SDF files.0. and Tcl scripts. 2. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. that is: a. .4. 4. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. The editor is tightly integrated with the simulator to enable debugging source code. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. SDF files must comply with OVI Standard Delay Format Specification Version 2.1. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. 5.-57 . HDL Editor: HDL Editor is a text editor designed for HDL source files.0 May 1997). It allows you to graphically edit waveforms so as to create desired test vectors. It displays specific syntax categories in different colors (keyword coloring). b. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. The keyword coloring is also available when HDL Editor is used for editing macro files.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. Resource files attached to the design. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI).

or EDIF objects declared within a selected region of the current design.4. When you choose a menu command or toolbar button for compilation. Verilog. Verilog.EDIF) • State diagram file (.vhd) • Verilog file (. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. a source file can be on of the following: • VHDL file (. Compilation: Compilation is a process of analysis of a source file.asf) • Block diagram file (. In Active-HDL. 6. Cycle-based simulation is significantly faster than event-driven.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired.-58 .32-BIT FLOATING POINT PROCESSOR TEC c.v) • EDIF net list file (. transistors or gates) and their interconnection. Verilog. and scripts. The structure of the design unit selected for simulation. macros. 5. or EDIF file containing HDL code (or net list) generated from the diagram. DEPARTMENT OF ECE PAGE NO. All Active-HDL tools output their messages to Console. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. the compiler analyzes the intermediate VHDL. VHDL. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. A net list is a set of statements that specifies the elements of a circuit (for example. • The Active-HDL simulator provides two simulation engines. d.bde) In the case of a block or state diagram file. Active-HDL provides three compilers. and EDIF. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. . respectively for VHDL.

5.6.2 Design Entry: • ISE Text Editor .1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.4.32-BIT FLOATING POINT PROCESSOR TEC Fig4.-59 .The ISE Text Editor is provided in ISE for entering design code and viewing reports. including ModelSim Xilinx Edition and the HDL Bencher test bench generator. Verilog HDL. .4.3. and finally produce a bit stream for your device configuration. including: • HDL (VHDL. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE.6 SYNTHESIS TOOL: 5. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files. DEPARTMENT OF ECE PAGE NO.1: Simulation 5.6.4. ISE enables you to start your design with any of a number of different source types. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities. 5. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD. This overview explains the general progression of a design through ISE from start to finish.

CORE Generator . and produces output for the bit stream generator. Place and Route (PAR) . Constraints Editor .3 Implementation: • Translate .The Chip Viewer tool provides a graphical view of the inputs and outputs. equations.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. State CAD State Machine Editor . placing or routing an FPGA design. • • • • • • • . and actions in a graphical editor. view. and after fitting and routing a CPLD design. analysis can be performed immediately after mapping.The FPGA Editor allows you view and modify the physical implementation.6. The state machine will be created in HDL.The Floor planner allows you to view a graphical representation of the FPGA.4. macro cell details.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders.State CAD allows you to specify states.-60 . and to view and modify the placed design.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. Fit (CPLD only) . places and routes the FPGA. to system-level building blocks such as filters. and Area Group constraints. FPGA Editor . FIFOs. Timing Analyzer . PACE . transforms.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor .The Constraints Editor allows you to create and modify the most commonly used timing constraints. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.The PAR program accepts the mapped design. including routing. Chip Viewer (CPLD only) .The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. • • • • 5. Map . Floor planner . Global logic. and pin assignments. and memories.The Map program maps a logical design to a Xilinx FPGA. With Timing Analyzer. DEPARTMENT OF ECE PAGE NO. transitions.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O.

-61 . Integration with ChipScope Pro.4. XPower . DEPARTMENT OF ECE PAGE NO.4 Device Download and Program File Formatting: • BitGen .6. • • • .XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration. iMPACT .The iMPACT tool generates various programming file formats. and subsequently allows you to configure your device.32-BIT FLOATING POINT PROCESSOR TEC 5.

1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. subtraction. multiplication and division are done using active HDL tool and the results are as follows: 6. . DEPARTMENT OF ECE PAGE NO.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6.-62 .

2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .32-BIT FLOATING POINT PROCESSOR TEC 6.2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6. . DEPARTMENT OF ECE PAGE NO. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.-63 .

3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6. DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . .32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.-64 .3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format.

DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC 6.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form. . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .-65 .

.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. • • Procedures for performing basic arithmetic operations are been formed.-66 . Basic arithmetic operations such as addition.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. The Functional-simulation has been successfully carried out with the results matching with the expected ones. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. subtraction. • 7. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. DEPARTMENT OF ECE PAGE NO.

however. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. or something might unexpectedly block its range of motion. unpredictable events can occur on an assembly line. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. . Since the subset must be determined in real time during system operation. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. The radar system may be tracking in a range from 0 to infinity.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. In these cases.-67 . The greater precision of signal data. Many levels of signal input from light. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. For instance. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. but need to use only a small subset of the range for target acquisition and identification. together with the device’s more accurate internal representations of data. x-rays. the robot might weld itself to an assembly unit. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. DEPARTMENT OF ECE PAGE NO. Wide dynamic range also plays a part in robotic design. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. The wide dynamic range of a floating-point DSP. However. feedback is well out of the ordinary operating range. Normally. enable imaging systems to achieve a much higher level of recognition and definition for the user.

Proc. Hayes.46 www. J. Science Research Associates.. pp.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman.1109/SNPD. (1986) A 32 bit processor architecture for direct execution of Forth. Chicago. 281-317 Yamamoto.com .computer.-68 . New York McKeeman. 14(7) 68-78 REFERENCES www. (1981) A survey of high-level language machines in Japan. W.ieee.. In: 1986 FORML Conf.. R. S. & Zaremba.ieeexplore.org www.) Introduction to Computer Architecture. In: Stone. T. 197-210 Jones.2007. 1975. (Ed. DEPARTMENT OF ECE PAGE NO. Pacific Grove CA.org/portal/web/csdl/doi/10. Prentice-Hall. (1975) Stack computers. M. Williams. Computer. pp. 28-30 November 1986. P. July 1981. H. M. (1987) The Implementation of Functional Programming Languages.intel.

architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1.std_logic_1164. end Fadd.std_logic_unsigned.all.Compute Ea-Eb -2.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.-69 . use IEEE. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). y : out std_logic_vector(31 downto 0) ).Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE. b : in std_logic_vector(31 downto 0). use IEEE. variable Temp :Std_logic_vector(6 downto 0).all. begin temp:=x.Shift the that has lesser Exponent by Ea-Eb places to the right * -3.all.std_logic_arith. DEPARTMENT OF ECE PAGE NO. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop .

-.Eb : std_logic_vector(7 downto 0). --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0). return sum.Resultant Exponent variable Ns : integer.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0). Eb :=Data(30 downto 23).Number Of Shifts variable Ma. -. Ma:=MaIn.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i.s2 : std_logic.Subtraction of Exponents --*2. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). end loop.Final Result begin MaIn:=Acc(22 downto 0). -. MbIn:=Data(22 downto 0). IE:=Eb(6 downto 0). end loop. end function. -.Z : std_logic_vector(1 downto 0).Internal Register variable Ea. -. DEPARTMENT OF ECE PAGE NO.-70 . else TEC Sum:=Sum. -. end if. Es:=Eb(7) .b : std_logic. --***************************************************************** --*Equalization of Exponents includes two steps --*1. a :=Acc(31). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). -. -.Sign Of Resultant Mantissa variable W.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Mangitude Of Two mantissas variable ES : std_logic.Sign Of Two exponents variable s1. -. variable X : std_logic_vector(31 downto 0). -. Z :=(a&b). -.Sign Of Resulant Exponent variable a. b :=Data(31).Sign Of Two mantissas variable Sign : std_logic. -. Ea :=Acc(30 downto 23).Mb : std_logic_vector(22 downto 0).Internal Register variable MbIn : std_logic_vector(22 downto 0).Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn.

Es:=Ea(7). IE:=Eb(6 downto 0).32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Ma:=Ma. ES:=Eb(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). DEPARTMENT OF ECE PAGE NO. ES:=Ea(7). end loop. Mb:=Mb. ES:=Ea(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. IE:=Ea(6 downto 0). when "10" => Mb:=MbIn. when "01" => Mb:=MbIn. Ma:=MaIn. end if. Ma:=MaIn. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). IE:=IE. else NS:=Ns. when "11" => Mb:=MbIn. end loop. IE:=Ea(6 downto 0). ES:=Ea(7). end loop. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). . Ma:=MaIn. IE:=Ea(6 downto 0).-71 .

if(Ea>Eb) then sign:='0'. Ma:=Ma.-72 . when others => Null. --***********logic for the sign of the mantissa********************** s1:=Acc(31). else NS:=Ns. end if. ES:=Eb(7). W :=(s1&s2). elsif(Ea<Eb) then sign:='1'. PAGE NO. s2:=Data(31). end if.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end case. sign:='1'. elsif(Ma<Mb) then sign:='1'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. else sign:=sign. IE:=Eb(6 downto 0). elsif(Ma=Mb) then sign:='0'. Mb:=Mb. case W is when "00" => when "11" => when "01" => when "10" => . DEPARTMENT OF ECE sign:='0'. end loop. ES:=Ea(7). end if. IE:=IE. else sign:=sign. --******************Addition of Mantissas**************************** IR:=Ma+Mb. if(Ea>Eb) then sign:='1'.

elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif(Ma=Mb) then sign:='0'. end case. else sign:=sign. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). when others => null.b). end Fadd.b) begin y<=float_add(a. elsif(Ma<Mb) then sign:='0'. return X. end if. end function. end if. begin process(a. end process.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps .-73 * . else sign:=sign. DEPARTMENT OF ECE PAGE NO.

end Fsub. .Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE. variable Temp : Std_logic_vector(6 downto 0). y : out std_logic_vector(31 downto 0)). architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout. use IEEE.-74 .std_logic_1164.all.all.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.Compute Ea-Eb 2. use ieee.Shift the that has lesser Exponent by Ea-Eb places to the right * 3. use ieee.all. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). begin temp:=x. DEPARTMENT OF ECE PAGE NO.std_logic_unsigned.std_logic_arith.32-BIT FLOATING POINT PROCESSOR ----1. b : in STD_LOGIC_VECTOR (31 downto 0).

Sign Of Two Mantissas variable sign : std_logic. -. end loop.Sign Of Resulant Exponent variable a.-75 . -.Final Result begin MaIn:=Accout(22 downto 0). DEPARTMENT OF ECE PAGE NO.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Subtraction of Exponents * * . Eb :=Data(30 downto 23). end if.Sign Of Resultant Mantissa variable W. -. Z :=(a&b). end function. Ea :=Accout(30 downto 23). -. variable X : std_logic_vector(31 downto 0).Sign Of Two Exponents variable s1.b : std_logic. a :=Accout(30). b :=Data(30). -.Internal Register variable Ea. -.Mb : std_logic_vector(22 downto 0). MbIn:=Data(22 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -.s2 : std_logic.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). --*********************variable Declarations*********************** TEC variable MaIn.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. return sum. -.Eb : std_logic_vector(7 downto 0). -.Z : std_logic_vector(1 downto 0). -. else Sum:=Sum.Mangitude Of Two Mantissas variable ES : std_logic.Resultant Exponent variable Ns : integer.MbIn: std_logic_vector(22 downto 0). -.Number Of Shifts variable Ma.

IE:=Ea(6 downto 0). IE:=Eb(6 downto 0). when "01" => Mb:=MbIn. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). IE:=Ea(6 downto 0). end loop.-76 . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Eb(7). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Ea(7). TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Ma:=Ma. end if. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Ma:=MaIn. DEPARTMENT OF ECE PAGE NO.Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn.32-BIT FLOATING POINT PROCESSOR --*2. ES:=Ea(7). Ma:=MaIn. end loop. Mb:=Mb. . end loop. IE:=IE. else NS:=Ns.

when others => null. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Ea(7). end loop. ES:=Ea(7). TEC Ma:=MaIn. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). . IE:=Eb(6 downto 0). end case. IE:=Eb(6 downto 0). Ma:=MaIn. Ma:=Ma. IE:=Ea(6 downto 0). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). else NS:=Ns. end if. IE:=IE. ES:=Eb(7).-77 . end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Mb:=Mb. ES:=Eb(7). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). DEPARTMENT OF ECE PAGE NO. when "11" => Mb:=MbIn. --******************Subtraction of Mantissas************************ IR:=Ma-Mb.32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. end loop. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).

s2:=Data(31). when "01"=> if(Ea>Eb)then sign:='0'. else sign:=sign. end if. when "11"=> sign:='1'. elsif(Ma<Mb) then sign:='0'. else sign:=sign. elsif (Ma=Mb) then sign:='0'. end if. W:=(s1&s2). elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif(Ea<Eb) then sign:='1'. case W is when "00"=> sign:='0'. else sign:=sign. else sign:=sign.-78 .32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). elsif(Ma<Mb) then sign:='1'. elsif (Ma=Mb) then sign:='0'. end if. . DEPARTMENT OF ECE PAGE NO. elsif (Ea<Eb) then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. when "10"=> if (Ea>Eb)then sign:='1'. end if.

-************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. begin process(a. . end function.std_logic_unsigned. end process.-79 . use IEEE.Addtion of the Exponents 5.b) begin y<=float_sub(a. end case. end Fmul.Multiplication of the Mantissas * * -************************************************************************** library IEEE. return X.std_logic_1164. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)).32-BIT FLOATING POINT PROCESSOR TEC when others=> null.b). end f_sub. b: in STD_LOGIC_VECTOR (31 downto 0). --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0). use IEEE. y: out STD_LOGIC_VECTOR (31 downto 0) ). DEPARTMENT OF ECE PAGE NO.all.all.

Magnitude Of Two Exponents variable c : std_logic. -.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0). -. -. -.Magnitude O Two Mantissas variable s : std_logic. when "11" => s:='0'. --************logic for the sign of the Mantissa******************* s1:=Accout(31).Sign Of Resultant Mantissa variable a.Resultant exponent variable m : std_logic_vector(21 downto 0).Resultant Mantissa variable carry : std_logic. -. e2 :=Data(30 downto 23). end case.b : std_logic. -.Z : std_logic_vector(1 downto 0). s2:=Data(31).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. -. e1 :=Accout(30 downto 23).-80 .s2 : std_logic. -. m2 :=Data(10 downto 0). Z :=(s1&s2). . case Z is when "00" => s:='0'.Final Result begin Carry:='0'. when others=> s:='1'.sign Two Mantissas variable Ea. -.Two Exponents Icluding Sign variable m1. -.Sign Two Exponents variable s1. m1 :=Accout(10 downto 0). variable x : std_logic_vector(31 downto 0).32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout.Carry variable W. DEPARTMENT OF ECE PAGE NO.m2 : std_logic_vector(10 downto 0).Eb : std_logic_vector(6 downto 0).e2 : std_logic_vector(7 downto 0). -.

W :=(a&b). elsif(Ea<Eb) then c:='1'. DEPARTMENT OF ECE PAGE NO. c:='1'. else c:='0'. e:=Ea+Eb. e:=Ea-Eb.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). end if. e:=Eb-Ea. elsif(Ea<Eb) then c:='0'. end if. when "11" => when others => null. . a :=Accout(30). Eb:=e2(6 downto 0). e:="0000000". else c:='0'. e:=Ea-Eb. b :=Data(30). case W is when "00" => c:='0'. e:=Eb-Ea. end case. e:=Ea+Eb. when "10" => if(Ea>Eb) then c:='1'. --*************logic for multiplication************************* m:=m1*m2. when "01" => if(Ea>Eb) then c:='0'. e:="0000000".-81 .

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

-86 . elsif(Ea<Eb) then c:='1'. e:=Eb-Ea. e:=Ea+Eb. case Z is when "00" => if(Ea>Eb) then c:='0'. b :=e2(7). e:="0000000". end if. end if. else c:='0'. Z :=(a&b). if(Ea>Eb) then c:='1'. else c:='0'. e:=Eb-Ea. e:=Ea-Eb.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). else c:='0'. e:="0000000". e:=Ea+Eb. if(Ea>Eb) then c:='0'. end if. e:=Ea-Eb. e:="0000000". . elsif(Ea<Eb) then c:='0'. when "10"=> if(Ea>Eb) then c:='1'. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. e:=Eb+Ea. a :=e1(7). Eb:=e2(6 downto 0). elsif(Ea<Eb) then c:='0'. elsif(Ea<Eb) then c:='0'.

DEPARTMENT OF ECE PAGE NO.b) begin Y<=float_div(a. end process. when others=> null. end F_div. end function. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). return X. end case. begin process(a.b). end if. else c:='0'.-87 .32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. TEC . e:="0000000".

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