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Synthesizable Ip Core for 32

Synthesizable Ip Core for 32

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Published by: Varun Reddy on Oct 17, 2011
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Sections

  • 1.1Objective
  • 1.2Methodology
  • 1.3Conceptual Survey
  • 1.4Organisation Thesis
  • 2.1. Real Number System
  • 2.2. Fixed-point Vs floating-point in digital signal processing
  • 2.3. Floating point
  • 2.4. General floating point format:
  • 2.5.1Single Precision Format:
  • 2.5.3. Double Precision Format:
  • 2.6 Ranges of Floating-Point Numbers
  • 2.7Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic:
  • 2.8.1.1. Block diagram representation of floating point adder:
  • 2.8.1.2. Addition of floating points using IEEE 754 format:
  • 2.8.2.1. Block diagram representation of floating point subtraction:
  • 2.8.2.2. Subtraction of floating points using IEEE 754 format:
  • 2.8.2.3. Flow chart for floating point subtraction:
  • 2.8.3.1. Multiplication using IEEE floating point standard:
  • 2.8.3.2. Block diagram of floating point multiplication:
  • 2.8.3.3. Flow chart for floating point multiplication
  • 2.8.4.1. Block diagram for floating point division:
  • 2.8.4.2 Floating point division using IEEE floating point standard
  • 2.8.4.3. Flow chart for floating point division
  • 2.9. Rounding Error
  • 2.10. Normalization
  • 2.11. Truncation
  • 3.1 Floating Point Addition
  • 3.2 Floating Point Subtraction
  • 3.3 Floating Point Multiplication
  • 3.4 Floating Point Division
  • 4.1 Processor:
  • 4.2 Digital Signal Processing
  • 4.3. Difference between off-line processing and real time processing:
  • 4.4. Architecture of digital signal processor:
  • 4.5. Comparison between Fixed Point and Floating Point System:
  • 4.6 Trends in DSP:
  • 4.7 Accuracy of Floating Point DSP
  • 5.2 IC DESIGN FLOW:
  • 5.3.1 HISTORY:
  • 5.3.2 CAPABILITIES
  • 5.3.3 HARDWARE ABSTRACTION:
  • 5.3.4 DATAFLOW STYLE OF MODELING:
  • 5.3.5 BEHAVIORAL STYLE OF MODELING:
  • 5.4.1. SIMULATION TOOL 5.4.1.1 Active HDL Overview:
  • 5.4.2. Standards Supported
  • 5.4.3 ACTIVE-HDL Macro Language:
  • 5.4.4Simulation:
  • 5.4.6.1 OVERVIEW OF XILINX ISE:
  • 5.4.6.2 Design Entry:
  • 5.4.6.3 Implementation:
  • 5.4.6.4 Device Download and Program File Formatting:
  • 6.1 simulation results of floating point addition
  • 6.2 simulation results for floating point subtraction
  • 6.3 simulation results for floating point multiplication
  • 6.4 simulation results for floating point division
  • 7.1 CONCLUSIONS
  • 7.2 FUTURE SCOPE

32-BIT FLOATING POINT PROCESSOR

TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1
INTRODUCTION
1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

. DEPARTMENT OF ECE PAGE NO.-4

The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers.) to plus infinity (+ ). The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. only a subset of the real-number continuum can be used in real-number calculations. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. DEPARTMENT OF ECE PAGE NO.-5 . . the real-number system comprises the continuum of real numbers from minus infinity (. As shown at the bottom of Figure 1.1.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. As shown in Figure 1.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. Figure 2. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.

the stored number can take on any integer value from 0 to 65. and ease of development. DEPARTMENT OF ECE PAGE NO. For instance. Similarly. some specific assumption is made about where the radix point is located in the string. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. from -32. Fixed-point Vs floating-point in digital signal processing Fig 2. performance attributes. Digital Signal Processing can be divided into two categories.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. while floating-point DSPs support either integer or real arithmetic. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications.535. the number is an integer). DSPs enable designers to build innovative features and differentiating value into their products. Lastly. These refer to the format used to store and manipulate numbers within the devices. designers can identify the DSP that is best suited for an application. the digit string can be of any length.536 possible bit patterns can represent a number. signed integer uses two's complement to make the range include negative numbers. There are four common ways that these 216 ' 65. Balancing these factors together. processor and system costs.-6 . and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. Fixed point DSPs usually represent each number with a minimum of 16 bits. low-cost development tools.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. fixed point and floating point. With unsigned fraction notation. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic.768 to 32. but decimal fixed point is common in commercial applications. the 65. In fixed-point systems. 2.536 levels are spread uniformly between 0 and 1. Software programmable for maximum flexibility and supported by easy-touse. In unsigned integer. Motorola manufactures a family of fixed point DSPs that use 24 bits.767. the signed fraction format allows . Among the key factors to consider are the computational capabilities required for the application. although a different length can be used. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. In common mathematical notation.2.

It is measured in” FLOPS”. In the most common format (ANSI/IEEE Std. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers.4. or sometimes the mantissa (see below) or coefficient. 2. which is capable of representing real and decimal numbers. Floating point A floating-point number is the one. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix).-7 .32-BIT FLOATING POINT PROCESSOR TEC negative numbers.In comparison. equally spaced between -1 and 1. it depends on the internal architecture. The represented values are unequally spaced between these two extremes. DEPARTMENT OF ECE PAGE NO. For instance.2 ×1038. loops. This results in many more bit patterns than for fixed point. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. This is known as the significand. and floating-point representation can thus be thought of as a computer realization of scientific notation. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. floating point DSPs typically use a minimum of 32 bits to store each value. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent.296 to be exact." 2. The term” floating point” refers to the fact that the radix point can "float". This position is indicated separately in the internal representation. the largest and smallest numbers are ±3. a necessity to implement counters. 2324. the SHARC devices are often referred to as "32-bit DSPs.967. The radix point is not explicitly included. This is important because it places large gaps between large numbers. All floating point DSPs can also handle fixed point numbers. the SHARC DSPs are optimized for both floating point and fixed point operations. For this reason.294. it can be placed anywhere relative to the significant digits of the number. but small gaps between small numbers.However. The floating-point operations are incorporated into the design as functions. that is. respectively. The logic for these is different from the ordinary arithmetic functions." rather than just "Floating Point. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most  . A key feature of floating point notation is that the represented numbers are not uniformly spaced.754-1985).3. and executes them with equal efficiency. and signals coming from the ADC and going to the DAC. The speed of floating-point operations is an important measure of performance for computers in many application domains.4 ×1038 and ±1.

and e is the exponent. b is the base.  A signed integer exponent. 2. computers used many different forms of floating-point. The floating-point format needs slightly more storage (to encode the position of the radix point). which modifies the magnitude of the number. so when stored in the same space. or to the right of the rightmost digit.Fraction. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. the format of the representations. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values.32-BIT FLOATING POINT PROCESSOR TEC significant digit. composed as integer. floating-point numbers achieve their greater range at the expense of precision.5. this final value is where s is the value of the significand (after taking into account the implied radix point). DEPARTMENT OF ECE PAGE NO. The length of the significand determines the precision to which numbers can be represented. These differing systems implemented different parts of the arithmetic in hardware and software. Significand is a real number. Prior to the IEEE-754 standard. The significand is multiplied by the base raised to the power of the exponent. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. with an average error of about 3%. and the rounding behaviour of operations. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. These differed in the word sizes. 10 or 16. 1 for negative values. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. also referred to as the characteristic or scale. Symbolically. (This is because the exponent field is in .-8 . IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754.

The Sign Bit: The sign bit is as simple as it gets. 2.-9 . The exponent's base is two. such as volume ramping in digital sound processing. and the mantissa. represents the precision bits of the number. 1 denotes a negative number. and each possible combination of bits represents one real number. DEPARTMENT OF ECE .32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. A float is represented using 32 bits. even though there are infinitely many real numbers (even between 0 and 1).f. To do this. There are many formats that are used for representation of floating point number. The sign bit is 0 for positive. 4. The Mantissa: The mantissa. or 1023 plus the true exponent for double precision.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. 3. The exponent field contains 127 plus the true exponent for single-precision. So. The Exponent: The exponent field needs to represent both positive and negative exponents. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. where f is the field of fraction bits.) This can be exploited in some applications. 0 denotes a positive number. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. to sum up: 1. also known as the significand. The first bit of the mantissa is typically assumed to be 1. a bias is added to the actual exponent in order to get the stored exponent. This means that at most 232 possible real numbers can be exactly represented. Flipping the value of this bit flips the sign of the number. It is composed of an implicit leading bit and the fraction bits. the exponent. 1 for negative. IEEE-754 specifies binary representations for floating point numbers: Table 2.

5.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). then V=-Infinity If E=255 and F is zero and S is 0. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010). The number of bits for each field are shown (bit ranges are in square brackets): Table 2. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. the next eight bits are the exponent bits. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. which may be represented as numbered from 0 to 31.1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. S.5. left to right.-10 .2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word.5. then V=Infinity . 'E'. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. Table 2. DEPARTMENT OF ECE PAGE NO.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2.

5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1. then V=(-1)**S * 2 ** (-126) * (0. then V=0 In particular. If E=0 and F is zero and S is 1.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.101 = -6. then V=-0 If E=0 and F is zero and S is 0.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.-11 .F) where "1.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1. If E=0 and F is nonzero.0 The biased exponent is .3125 The biased exponent is -2+127=125= (01111101 • 1.F) These are "unnormalized" values.101 = 6.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0. DEPARTMENT OF ECE PAGE NO.

0 0 1 0 1 1313.1015625 × 2 = 0.203125 0.1015625 0.01012.3125 is • 0. sign bit is 1. 10 + 127 = 137 = 100010012.-12 .010010000101012 × 210. So -1313.203125 × 2 = 0.40625 × 2 = 0. = 1.3125 131310 = 101001000012 0.312510 = 10100100001.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0. • -78.25 0.25 The biased exponent: 127+6=133=(10000101 • -1313.5 × 2 = 1. .5 × 2 = 0.32-BIT FLOATING POINT PROCESSOR TEC • 37.625 × 2 = 1.8125 × 2 = 1.5 The based exponent: 127+5= (10000100 . DEPARTMENT OF ECE PAGE NO.3125 0.25 × 2 = 0.8125 .625 0.40625 0.

3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.-13 . the next eleven bits are the exponent bits. then V=NaN ("Not a number") PAGE NO.5 × 2 = 1.1015625 is 0 00111101 110100000000000000000000 TEC 2. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0). next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001). Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.32-BIT FLOATING POINT PROCESSOR 0. left to right. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.5. DEPARTMENT OF ECE .25 0.101562510 = 0.3. which may be represented as numbered from 0 to 63.5 0 × 2 = 1.25 1 × 2 = 0.00011012 = 1.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0.5. 'E'.0 1 0. The first bit is the sign bit.625 0. S. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.

If E=0 and F is zero and S is 1.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa).-14 . . while maintaining good precision.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1.5.6.53 ~ 10308.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2.F) where "1.F) These are "unnormalized" values. If E=0 and F is nonzero. then V=(-1)**S * 2 ** (-1022) * (0. using a fixed number of digits.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2. Table 2. then V=-0 If E=0 and F is zero and S is 0. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . 15 exponent bits and 112 significand bits. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. then V=-Infinity If E=2047 and F is zero and S is 0.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable. floating-point notation allows calculations over a wide range of magnitudes. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision.

and the smallest possible value for the exponent. Normalized And Approximate Decimal Values. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. Approximate Decimal 2127 21023 ~10-44.53 ~10-323. P is the precision of the system to P numbers. Negative numbers greater than -2-149 (negative underflow) 3.6. The number of normalized floating point numbers in a system F(B. P.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. Zero 4. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1).2: Effective Range of IEEE Floating Point Number with Denormalized. DEPARTMENT OF ECE PAGE NO. L is the smallest exponent represent able in the system. Positive numbers less than 2-149 (positive underflow) . L. There is a largest floating point number.3 to ~10308.85 to ~1038. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand. U) (where B is the base of the system. the range for negative numbers is given by the negation of the above values. There is a smallest positive normalized floating-point number.-15 .32-BIT FLOATING POINT PROCESSOR TEC Table 2. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2.

the exponent is set to -127 (E = 0). Underflow occurs when the sum of the exponents is more negative than -126. Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers.32-BIT FLOATING POINT PROCESSOR 5. 2.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. the most negative value which is defined in bias-127 exponent representation. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. Recently.infinity. When this occurs. When this occurs. the number is exactly zero. However the CPU will have to perform extra arithmetic to read the number when stored in this format. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. DEPARTMENT OF ECE PAGE NO. 2. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. the largest value which is defined in bias-127 exponent representation. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. If M = 0.-16 . These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications.

Addition 2..8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. Subtraction 3.. . let us consider two numbers a= 2. i.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. Now as both the exponent values are same. DEPARTMENT OF ECE PAGE NO. as the smaller number here is a=2. But by using floating point addition this can be avoided to a little extent.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.-17 .8.0225x .25x and b= 1. Hence the value of number ‘a’ becomes 0. Division 2. Multiplication 4.e. both the numbers are added. Floating point addition is analogous to addition using scientific notation. For example. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. They are: 1. Normalize the result.1. Add the numbers with decimal points aligned.

Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.00000009876543 x c= 1. 2.8.e. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. then the following result may occur: 1.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.e. But the normalised result may sometimes carry the required result.234567x b= 0. i.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.8.1.1. a =1. The mantissa of both numbers A and B are added.1.8. b= 9. Now both the numbers are added. then bit 1 is represented for sign.1. signB as sign of number B.00000009876543 x 2.234567x and b= 9.. Thus this case can said to be having rounding errors. 2.-18 . the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. ExpA as exponent of number A . Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: .2345670 x in which the remaining part (9876543) which is discarded also carries the result. ManA as mantissa of number A. ExpB as exponent of number B and ManB as mantissa of number B.. If the numbers are represented with both positive and negative sign. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. then sign of greater number is considered.876543x and if the addition has to be performed. DEPARTMENT OF ECE PAGE NO.2.876543x after shifting becomes b= 0. Consider a example in which a =1.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1.

2: Flow Chart for Floating Point Adder. exception is made. the numbers are represented in IEEE floating point format. 4. the exponent sum would have doubled the bias. If there is an underflow or overflow.8. Addition of significands is done. DEPARTMENT OF ECE PAGE NO. Firstly.1.-19 . the significand is rounded to the appropriate number of bits required and again normalization is checked. If not. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. . the bias value must be subtracted from the sum 3. 6. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. 2.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. If the exponents are stored in biased form. 1. 5. Thus.

When adding numbers of opposite sign.32-BIT FLOATING POINT PROCESSOR TEC 7. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. 2. 2. The mantissa is always less than 2.-20 .2.25 becomes: The mantissas are added using integer addition: The result is already in normal form. Negative mantissas are handled by first converting to 2's complement and then performing the addition. Thus. resulting in a sum which is arbitrarily small. Subtraction . then the mantissa must be shifted one bit to the right and the exponent incremented.8. Consider addition of the numbers 2. the result is converted back to signmagnitude form. Normalization in this case may require shifting by the total number of bits in the mantissa. After the addition is performed. or even zero if the numbers are equal in magnitude. The number 2. resulting in a large loss of accuracy. so the hidden bits can sum to no more than 3 (11).25x and 1. If the sum overflows the position of the hidden bit.0625 in IEEE Floating Point Standard is: To align the binary points.25 in IEEE Floating Point Standard is: The number 134. DEPARTMENT OF ECE PAGE NO.340625x . cancellation may occur. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal.

Subtract the numbers with decimal points aligned. i.0225x . The normalised result may contain the required number of digits discarding the unwanted part.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2..-21 . 2. ExpA as exponent of number A . signB as sign of number B.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.8. Hence the value of number ‘a’ becomes 0. DEPARTMENT OF ECE PAGE NO..2. as the smaller number here is a=2.8.1.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .e. Normalize the result.2.340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal.. both the numbers are added. The mantissa of both numbers A and B are subtracted. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.25x and b= 1. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2.e. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if . ExpB as exponent of number B and ManB as mantissa of number B. then sign is represented according to the number i. ManA as mantissa of number A. Now as both the exponent values are same.1.

-22 .25 in IEEE Floating Point Standard is: The number 134. 5. Thus. Consider subtraction of the numbers 2.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign. the bias value must be subtracted from the sum 3.0625 in IEEE Floating Point Standard is: To align the binary points. DEPARTMENT OF ECE PAGE NO. 6. If there is an underflow or overflow. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. the significand is rounded to the appropriate number of bits required and again normalization is checked.25 become: The mantissas are subtracted using integer subtraction: . If not. 2.2. The number 2. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 2. 2.2. the exponent sum would have doubled the bias. exception is made. Subtraction of significands is done.25x and 1. The numbers are represented in IEEE floating point format. If the exponents are stored in biased form. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. 4.340625x .8. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. Thus.

32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. Flow chart for floating point subtraction: Subtract significand si Fig 2.8.. then the significands of numbers X and Y are subtracted.2. If number X is not ‘0’. then number Y is checked. If the significand is zero then it is returned if not significand overflow is checked.2.-23 .8. number X is checked. 2. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . If both the numbers X and Y are non zeros.e. If it is ‘0’ then the resultant solution Z would be Y i. If the exponents are same.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. If the sum overflows the position of the hidden bit. Z=Y.3. DEPARTMENT OF ECE PAGE NO. If it is ‘0’. then the result would be Z=X. In the first step. then the following steps can be followed: Exponents of both the numbers are checked. then the mantissa must be shifted one bit to the right and the exponent incremented. If overflow occurred then overflow is reported and returned. At this point. consider two numbers X and Y and the resultant be Z. If overflow occurs. If not then the result is normalized.

8. to multiply 1.0 in IEEE FPS format is: The number 9.5x : Perform unsigned integer multiplication of the mantissas. The number 18.-24 . Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.3. If underflow occurred then it is reported if not the normalized result is given out. DEPARTMENT OF ECE PAGE NO.3.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. if the significand is not zero then subtraction and further process is carried out. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.8x times 9. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers. 2.8.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.1.8 x 9. For example. 1. If the exponents are not same. 2.5 ----17.5 in IEEE FPS format is: .

32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in ().-25 . When the fields are assembled in IEEE FPS format. the mantissa is: The biased-127 exponents are added. DEPARTMENT OF ECE PAGE NO.8. the result is: 2. The sign of the result is the xor of the sign bits of the two numbers.2.3. Block diagram of floating point multiplication: . If the position of the hidden bit overflows. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form. the mantissa must be shifted right and the exponent incremented.

the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. DEPARTMENT OF ECE PAGE NO.8.3. XOR operation for sign bit can be given as follows: Table 2.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. manA as mantissa of number A. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. If the exponents are stored in biased form. At the first step.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . expA as exponent of number A .8. expB as exponent of number B and manB as mantissa of number B. The exponents of both the numbers are added and subtracted from the bias 127.8. the exponent sum would have doubled the bias. Resultant mantissa is truncated and normalized to fit for the IEEE format. . Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. signB as sign of number B. If both the numbers X and Y are not zero.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.3.3. then the exponents are added and a bias of 127 is subtracted from the result.3.-26 . Thus. The mantissa of both numbers A and B are multiplied. Sign of the result is given by performing xor operation of signA and signB.

.5 .8. Hence the result can be given as 1.3 0.3. Exponent of a is 2 and exponent of b is 3.4. i.5.e. The resultant sign bit would be the xor operation of sign bits of X and Y.2 .5.3 and b= 0. So resultant exponent would be 2-3=-1. Fig 2. 2.3: Flow Chart For Floating Point Multiplication. 0..8.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned. Division Consider an example of dividing a=0. When the division of both significands are done then the quotient would be 1.2 =1. in general floating point division the exponents of both the numbers are subtracted and the significands are divided.-27 . DEPARTMENT OF ECE PAGE NO.

-28 . Special . The mantissa of both numbers A and B are divided. 2. then the resultant sign is also positive and is represented by bit ‘0’. signB as sign of number B. Set the sign of the result. ExpB as exponent of number B and ManB as mantissa of number B. The exponents are subtracted and biased using the bias value. ExpA as exponent of number A . If anyone number of the two are negative. a 24 bit quotient is produced. When divided by a 24 bit divisor. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement.8.8.8. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. If both the numbers are either positive or negative. In the first step.1. Normalize the result. Block diagram for floating point division: Fig 2.4.4. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. DEPARTMENT OF ECE PAGE NO. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. then the result is also negative is represented by bit ‘1’. As in floating point multiplication. Subtract the exponent of the divisor from the exponent of the dividend. ManA as mantissa of number A.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .32-BIT FLOATING POINT PROCESSOR TEC 2.4.

Considering a=0. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. This value is called Not A Number. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2.Then the steps that occur are: 1.4.2 can be represented as M 010000001(0)11000000000000000000000 0.3 S E and b= 0. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero.8. .3. 2. Number X and Y are checked. For this. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity . 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned. DEPARTMENT OF ECE PAGE NO. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . or NaN.3 0.-29 . in this case as larger number has to be subtracted from smaller number.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted.

If they are present. Fig 2.9.g. rounding errors occur as a result of the limited precision of the mantissa . • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. . In some systems. • Significand underflow: In the process of aligning significands.4. 2.127). DEPARTMENT OF ECE PAGE NO. digits may flow off the right end of the significand.8.200 is less than . and it may be reported as 0. If not the mantissas are divided and truncated and normalized result is given out.32-BIT FLOATING POINT PROCESSOR TEC 3. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit.. some form of rounding is required.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. As we shall discuss. then those conditions are reported.This means that the number is too small to be represented. this may be designated as +∞ or -∞.-30 . Rounding Error In floating point arithmetic.

. the relative error is approximately since For denormalized numbers (E = 0). The least significant 24 bits are discarded. RP: Round toward Positive infinity. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. Same as truncation in sign-magnitude. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. RN is generally preferred and introduces less systematic error than the other rules. DEPARTMENT OF ECE PAGE NO. The size of the absolute error is proportional to the magnitude of the number.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. Normalization By normalization. Break ties by choosing the least significant bit = 0. For numbers in IEEE FPS format. RZ: Round toward Zero. relative errors increase as the magnitude of the number decreases toward zero. highest precision can be achieved. To efficiently use the bits available for the significand. For normalized floating point numbers. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). RM: Round toward minus infinity. Same as truncation in 2's complement. However.10.-31 . The value can be kept unchanged by adjusting the exponent accordingly.

Truncation To retain maximum accuracy.g. multiplication). the bits need to be truncated to guard bit Chopping: simply drop all . all extra bits during operation (called guard bits) are kept (e. Zero is represented by all 0's and is not (and cannot be) normalized. in the following the default normalization does not assume this implicit 1 unless otherwise specified. The first bit 1 before the decimal point is implicit.. By the end of the operation. it does not need to be shown explicitly. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. to avoid possible confusion. as the MSB of the significand is always 1.-32 .11. resulting 1. If we assume number. bits are used in final representation of a bits by one of the three methods. a 4-bit exponent field and a 9-bit significand field): 2.32-BIT FLOATING POINT PROCESSOR TEC Moreover. DEPARTMENT OF ECE PAGE NO. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. extra guard bits are kept during operation. The actual value represented is However.

-33 . Two worst cases Both two cases can be summarized as i.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. . set whether it is originally 0 or 1). otherwise do nothing. (no matter Von Neumann Rounding: If at least one of the guard bits is 1. add 1 to LSB . Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. DEPARTMENT OF ECE PAGE NO. Interpretation: Value represented by guard bits is greater than 0. is always greater than 0. the Von Neumann rounding error is unbiased. . 3.5 round up. we say this truncation error is biased.e..

round up: Interpretation: Value represented by guard bits is 0. round down: or if .5 either up or down with equal probability (50%). Interpretation: Value represented by guard bits is smaller than 0. it is randomly rounded . drop all guard bits. The rounding error of these cases can summarized as .-34 . c) If the highest guard bit is 1 and the rest guard bits are all 0. . the rounding depends on the LSB : if .5 round down.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0. DEPARTMENT OF ECE PAGE NO.

e.3 Floating Point Functions A floating-point number is the one. The MSB is the sign-bit i. Therefore zero is represented by 0111. which is capable of representing real and decimal numbers. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. I. subtraction. the exponent obtained by balancing operations is added to 0111.e. DEPARTMENT OF ECE PAGE NO. The logic for floating point addition. . Positive numbers are represented by binary values greater than 0111. The logic for these is different from the ordinary arithmetic functions. The next eight bits are that of the exponent. 1111. 1985 floating point standard representation before any sort of operations are conducted on them. The floating-point operations are incorporated into the design as functions. The above representation is the IEEE-784 1985 standard representation. The exponent in this IEEE standard is represented in excess-127 format.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . the sign of the floating point number. multiplication and division is presented in the following pages.-35 . 1111 and negative numbers are represented by binary values less than it. 1111. The numbers in contention have to be first converted into the standard IEEE 784.

we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. • • . This is done till the lower exponent becomes equal to the higher one.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. DEPARTMENT OF ECE PAGE NO. These numbers are distinct.-36 . So to add their mantissa’s. The mantissas are then added to each other and the result is then stored in a temporary register. Once the exponents are normalized.32-BIT FLOATING POINT PROCESSOR TEC 3. namely Accumulator and the Temp register that loads the value appearing on the data bus. So. These numbers are stored into the memory from which they are read and processed. we have to first normalize their exponents. Now the numbers from the memory are loaded into two registers. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.

The mantissas are then subtracted and the result is stored in a temporary register. So. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. These numbers are stored into the memory from which they are read and processed.-37 . The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. So to add their mantissa’s. Once the exponents are normalized.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. These numbers are distinct. Now the numbers from the memory are loaded into two registers. we have to first normalize their exponents. This is done till the lower exponent becomes equal to the higher one.32-BIT FLOATING POINT PROCESSOR 3. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. namely Accumulator and the Temp register that loads the value appearing on the data bus. . DEPARTMENT OF ECE PAGE NO. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out.

There is however a limitation to this operation. so that the result is restricted to not more than 24-bits.-38 .32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. The final output is obtained by concatenating the product of the mantissas. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. • • • . Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. So each input should not exceed 12-bits in length. the resulting exponent and the sign of the result that is calculated separately.

The convention here is that the Numerator should be always less than the denominator. if the MSB or the 49th bit is one than we add a one in the quotient.-39 . we append it with the exponent value and the Sign of the division that are calculated separately. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. Now since the greater of the two numbers is decided. First the exponents are directly added or subtracted depending on which is bigger. This is to ensure that whatever comes as the result is after the decimal point. DEPARTMENT OF ECE PAGE NO. till the quotient is full.32-BIT FLOATING POINT PROCESSOR TEC 3. The result is stored in Temp. And if it is zero. Apart from that the final sign of the division is calculated separately. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. The decimal is assumed to be before the MSB of the resulting quotient. The logic for floating point division is as follows. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. Once the quotient is full. Now both the numbers in the IEEE-784 standard format are compared. We initiate a counter and carry this process for 24 times.4 Floating Point Division • • • • This is more complicated then Multiplication. we put a zero in the quotient. • • • • • . Now the first 24-bits from the MSB are compared with the divisor.

consider a word processing program. When the processor executes instructions. the processor performs an action that corresponds to an instruction or a part thereof. With each clock peak. finding use in everything from cellular telephones to advanced scientific instruments. written in Hertz (Hz). the overall number of registers can vary from about ten to many hundreds.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. The clock speed (also called cycle). Clock frequency is generally a multiple of the system frequency. such as the size of the instruction set and how it interrupts are handled. 32 or 64 bits called registers.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. For instance. etc). The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. and so on. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. the program moves the data from . A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. data is temporarily stored in small. These devices have seen tremendous growth in the last decade.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. Consider another example of how a document is printed from a word processor.-40 . corresponds to the number of pulses per second. Computers are extremely capable in two broad areas 1. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. DSPs can perform the mathematical calculations needed in digital signal processing. Depending on the type of processor. 4. Data manipulations involve storing and sorting information. All microprocessors can perform both tasks. When this code is detected. These tasks are accomplished by moving data from one location to another. 16. engineering and digital signal processing. local memory locations of 8. A<B . Mathematical calculation used in science. meaning a multiple of the motherboard frequency. however it is difficult or expensive to make a device that is optimized for both. Data manipulation such as word processing and database management 2. There are technical tradeoffs in the hardware design. product life time. There are marketing issues involved: development and manufacturing cost. The basic task is to store the information. competitive position. DEPARTMENT OF ECE PAGE NO. and testing for inequalities (A=B. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing.

DEPARTMENT OF ECE PAGE NO.....e..32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. while the output signal is denoted by y [ ]. there may only be a few coefficients in the filter kernel. i. the math operations dominate the execution time. For example. depending on the application. . the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required.. The task is to calculate the sample at location n in the output signal. Using standard notation. y[n]. the most common DSP technique. consider the implementation of an FIR digital filter. it is infrequent and does not significantly affect the overall execution speed.. While mathematics is occasionally used in this type of application. the input signal is referred to by x [ ]..-41 .. While there is some data transfer and inequality evaluation in this algorithm.... such as to keep track of the intermediate results and control the loops. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: . In comparison. This is simply saying that the input signal has been convolved with a filter kernel consisting of: .

. with the advent of very fast floating point processing hardware.1: Graphical representation of FIR digital filter design. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. a geophysicist might use a seismometer to record the ground movement during the earthquake. say. the information may be read into a computer and analysed in some way. design difficulty and so on.000 samples per second.x[n-1]. Off-line processing is a realm of personal computers and mainframes. the traditional speed advantage of integer operations over floating point operations is decreasing.. but these items will appear as chip fabrication technology gets denser. 4. so as the cost . There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors.000 samples per second. After shaking is over. whereas 32-bit processors are naturally suited to the size of the data elements. converting a word processing document from one form to another.2. Difference between off-line processing and real time processing: In off-line processing.x[n-2]. floating point math must often be used to reduce the cost of programming a project. . is found by multiplying samples from the input signal.-42 . and to support code written in high level languages. In these cases a 16-bit processor may suffice.32-BIT FLOATING POINT PROCESSOR TEC Fig4.y[n]. If the digital signal is being received at 20. However. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. DEPARTMENT OF ECE PAGE NO. In FIR filtering . This is common in scientific research and engineering. You simply wait for the action to be completed before you give the computer its next assignment In comparison. Floating point calculations also require a 32-bit processor for good efficiency.by the filter kernel coefficients. the entire input signal resides in the computer at the same time.. and summing the products. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. . as well as the algorithms that can be applied. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. the DSP must be able to maintain a sustained throughput of 20. The disadvantages of 32-bit processors are cost and system complexity.. In addition to performing mathematical calculations very rapidly.. Hence execution time is critical for selecting the proper device. consider a designing of an audio signal in DSP system such as a hearing aid. There are a few reasons for why to not to make it faster than necessary because as speed increases.3. each sample in the output signal . Digital signal processors are designed to quickly carry out FIR filters and similar techniques. not having a defined start or end. Also. power consumption. most DSPs are used in applications where the processing is continuous. x[n]. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. DSPs must also have a predictable execution time. There is less room on-chip for extra features such as hardware multipliers. For example. If suppose you are launching your desktop computer on some task . For instance. The key point in off-line processing is that all of the information is simultaneously available to the processing program.

the output signal is produced at the same time that the input signal is acquired. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. Alternatively. two binary values (the numbers) must be passed over the data memory bus. For instance. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. improving the speed over the single bus design. the data transfer rate is an incredible 240Mbytes/second. Most present day DSPs use this dual bus architecture. 4. Harvard Architecture. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. Super Harvard Architecture (SHARC). . hearing aids and radar.4. we might place the filter coefficients in program memory. Harvard architecture has separate memories for data and program instructions. These are extremely high speed connections. there are two serial ports that operate at 40 Mbits/second each. two areas are important enough to be included are an instruction cache. we start by relocating part of the "data" to program memory. over and over. For instance. while keeping the input signal in data memory. This includes data. such as samples from the input signal and filter coefficients as well as program instructions. while six parallel ports each provide a 40 Mbytes/second data transfer. Real time applications input a sample. To improve upon this situation. When two numbers are multiplied. the binary codes that go into the program sequencer. with separate buses for each. The SHARC DSPs provides both serial and parallel communications ports. program instructions and data can be fetched at the same time.-43 . Since the buses operate independently. The basis of Harvard design is that the data memory bus is busier than the program memory bus. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). while only one binary value (the program instruction) is passed over the program memory bus. at a 40 MHz clock speed. For example. Most of the computers are using this architecture today. When all six parallel ports are used together. For example. Likewise.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. Different architectures available are: Von Neumann Architecture. DEPARTMENT OF ECE PAGE NO. This is the world of digital signal processors. and an I/O controller. this is needed in telephone communication. they may input a group of samples perform the algorithm and output a group of samples. perform the algorithm and output a sample. While the SHARC DSPs are optimized in dozens of ways. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator.

The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. This allows . the coefficient comes over the program memory bus. The first time through a loop.-44 . Some DSPs have on-board analog-to-digital and digital-toanalog converters. DSP algorithms generally spend most of their execution time in loops. This means that the same set of program instructions will continually pass from program memory to the CPU. However. providing higher speed. on additional executions of the loop. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. such as instructions. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC Figure 4.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. the Harvard architecture uses separate memories for data and instructions. all DSPs can interface with external converters through serial or parallel ports.4. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. providing an additional interface to off-chip memory and peripherals. In comparison. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. In the jargon of the field. the program instructions can be pulled from the instruction cache. This is a small memory that contains about 32 of the most recent program instructions. and the program instruction comes from the instruction cache. a feature called mixed signal. the program instructions must be passed over the program memory bus. However. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. this efficient transfer of data is called a high memory-access bandwidth.

Digital Signal Processors are designed to implement tasks in parallel. and similar functions. and so on. Fig 4. At the top of the diagram are two blocks labelled Data Address Generator (DAG). Compare this architecture with the tasks needed to implement an FIR filter. extracting and depositing segments. and places the result into another register.2: Typical DSP architecture. a multiplier. NOT). In simpler microprocessors this task is handled as an inherent part of the program sequencer. . data from registers 0-7 can be passed to the multiplier. an arithmetic logic unit (ALU). conversion between fixed and floating point formats. logical operations (AND. subtraction. absolute value. These control the addresses sent to the program and data memories. accessible at 40Mwords/second (160 Mbytes/second). and is quite transparent to the programmer. rotating. DEPARTMENT OF ECE PAGE NO. In a single clock cycle. All of the steps within the loop can be executed in a single clock cycle. such as shifting. The math processing is broken into three sections. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel.4. The ALU performs addition.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. OR. and a barrel shifter. The multiplier takes the values from two registers. for 32 bit data. This simplified diagram is of the Analog Devices SHARC DSP. specifying where the information is to be read from or written to. multiplies them. XOR. Elementary binary operations are carried out by the barrel shifter.-45 . and the two results returned to any of the 16 registers. one for each of the two memories. data from registers 8-15 can be passed to the ALU.

a result of the hardware being highly optimized for math operations. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. and signals coming from the ADC and going to the DAC. the multiplier and ALU must be able to quickly perform floating point arithmetic.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. The internal architecture of a floating point device is more complicated than for a fixed point device. TMS320C5x™ and TMS320C2x™ DSPs. the instruction set must be larger and so on. Comparison between Fixed Point and Floating Point System: TEC Both fixed. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. All the registers and data buses must be 32 bits wide instead of only 16. with DSPs the speed is about the same. DEPARTMENT OF ECE PAGE NO. Double-width precision achieves much greater precision and dynamic range at the expense of speed.For instance.5.or floating-point decision in the past. are based on single16-bit data paths. since it requires multiple cycles for each operation." fixed point arithmetic is much faster than floating point in general purpose computers. However. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. loops. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. though. floating point programs often have a shorter development cycle." rather than just “Floating Point. All floating point DSPs can also handle fixed point numbers. and an 8-bit exponent. underflow and round-off. the latter normalized in the form of scientific notation.32-BIT FLOATING POINT PROCESSOR 4. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. . a necessity to implement counters. since the programmer doesn’t generally need to worry about issues such as overflow. While fixed-point DSP hardware performs strictly integer arithmetic. For this reason. In addition. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. the SHARC DSPs are optimized for both floating point and fixed point operations. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). respectively. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. By contrast. Tradeoffs of cost and ease of use often heavily influenced the fixed. with architectures designed for handheld and control applications. However. and executes them with equal efficiency. it depends on the internal architecture . TMS320C64x™ DSPs. floating-point DSPs support either integer or real arithmetic. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. Fixed point DSPs are cheaper than floating point devices. Today.and floating-point indicate. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15.-46 . As the terms fixed. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. including a 53-bit mantissa and an 11-bit exponent). the SHARC devices are often referred to as "32-bit DSPs.

The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. Standard deviation of this quantisation noise is about one-third of the gap size. Fixed point DSPs are generally cheaper. this quantization noise will simply add. . while floating point devices have better precision. suppose we store the number 10. higher dynamic range. To store the number. For example. For instance. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. To avoid overflow. greatly lowering the signal-to-noise ratio of the system. It can be rated in the form of signal to noise ratio and quantisation noise. although it does limit how some algorithms must be carried out. DEPARTMENT OF ECE PAGE NO. The same thing happens when a number is stored as a 16-bit fixed point value. This strategy works very well. multiply it by the appropriate sample from the input signal. except that the added noise is much worse.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. while for a fixed point number it is only about ten-thousand to one. In traditional microprocessors. This is because the gaps between adjacent numbers are much larger. in a 500 coefficient FIR filter. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. The gap between numbers is one ten-thousandth of the value of the number we are storing. Noise is signal is usually represented by its standard deviation. we loop through each coefficient. Suppose we implement an FIR filter in fixed point. it must be round up or down by a maximum of one-half the gap size i.1: Fixed versus floating point. in a 16 bit DSP it may have 32 to 40 bits.000 as a signed integer. Here's the problem. To do this. and a shorter development cycle. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. floating point has such low quantization noise that these techniques are usually not necessary. it illustrates the main point when many operations are carried out on each sample. it's bad.. Suppose we store in a 32 bit floating point format.000 times less quantisation noise than fixed point.-47 . This is a special register that has 2-3 times as many bits as the other memory locations. while in the SHARC DSPs it contains 80 bits for fixed point use. floating point has roughly 3.5. This extended range virtually eliminates round-off noise while the accumulation is in progress.e. In comparison. each time we store a number in floating point notation. really bad. this accumulator is just another 16 bit fixed point variable. In other words. For instance. In the worst case. and add the product to an accumulator. we add noise to the signal. and will correspondingly add quantization noise on each step. Although this is an extreme case. we need to scale the values being added. DSPs handle this problem by using an extended precision accumulator. the noise on each output sample may be 500 times the noise on each input sample.

such as spectral analysis and FFT convolution. and almost certainly need floating point to capture the large dynamic range. 12-14 bits per sample is the crossover for using fixed versus floating point. are very detailed and can be much more difficult to program. floating point will generally result in a quicker and cheaper development cycle. For example. When fixed point is chosen. FIR filtering and other operations in the time domain only require a few dozen lines of code. professional audio applications can sample with as high as 20 or 24 bits. The next thing to look at is the complexity of the algorithm that will be run . but the development cost will probably be higher due to the more difficult algorithms. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. making them suitable for fixed point. and the precision of fixed point is acceptable. think floating point. In many applications. the cost of the product will be reduced. if it is more complicated. In the reverse manner. In comparison. television and other video signals typically use 8 bit ADC and DAC.-48 . DEPARTMENT OF ECE PAGE NO. The programmer needs to continuously understand the amplitude of the numbers. In fixed point. floating point systems are also easier to develop algorithms for. .If it is relatively simple. the development time will be greatly reduced if floating point is used. Most DSP techniques are based on repeated multiplications and additions. the possibility of an overflow or underflow needs to be considered after each operation. In comparison. these issues do not arise in floating point. frequency domain algorithms. In contrast. For instance. While they can be written in fixed point. and what scaling needs to take place. but a more expensive final product. think fixed point. the numbers take care of themselves. how the quantization errors are accumulating.

many options are needed for fixed point. It could not be any simpler. DEPARTMENT OF ECE PAGE NO. This describes the ways that multiplication can be carried out for both fixed and floating point formats. look at all the possible commands for fixed point multiplication. where Fn. In comparison. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. The vertical lines indicate options. Rn. These are the multiplication instructions used in the SHARC DSPs. The RND and SAT options are ways of controlling rounding and register overflow. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. This table also shows that the numbers may be either signed or unsigned (S or U). . These are the many options needed to efficiently handle the problems of round-off.-49 . and format. Fx. the floating point programmer can spend his time concentrating on the algorithm. and MRF and MRB are 80 bit accumulators. Rx. Fn = Fx * Fy. For instance. and Ry refer to any of the 16 data registers. In contrast. scaling. MRF = Rx * Ry. the value of any two registers can be multiplied and placed into another register. and Fy are any of the 16 data registers. While only a single command is needed for floating point.2: Fixed versus floating point instructions. and MRB = Rx * Ry. and may be fractional or integer (F or I). In other words.5. or into one of the extended precision accumulators.

Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. However. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. When you are in competition to sell millions of your product. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. In comparison. meaning there is a greater difference between the largest number and the smallest number that can be represented. 32-bit floating point has a higher dynamic range. In (b). This is mainly driven by consumer products that must have low cost electronics. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . About twice as many engineers currently use fixed point as use floating point DSPs. However.1: Major trends in DSPs. floating point is the fastest growing segment. and another 49% are considering the change. For instance. such a . suppose you are designing a medical imaging system. A good example of this is cellular telephones. about twice as many engineers use fixed point as use floating point DSPs. a cost difference of only a few dollars can be the difference between success and failure.-50 .6 Trends in DSP: TEC Figure 4. floating point is more common when greater performance is needed and cost is not important. as shown in (c).6. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. As shown in (c). this depends greatly on the application.32-BIT FLOATING POINT PROCESSOR 4. such as cellular telephones. As illustrated in (a). DEPARTMENT OF ECE PAGE NO.

Third. . there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). exponentiation vastly increases the dynamic range available for the application. 4. Only a few hundred of the model will ever be sold. Fortunately. or 32 bits for fixed-point DSPs. Finally. floating-point coefficients can be 24 bits or 53 bits of precision. which would go beyond most application requirements in accuracy. ensuring greater accuracy in end results. and can be 8. The first is the I/O signal word width. a 32-bit product would be needed. In spite of the larger number of fixed point DSPs being used.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. In fixed. First.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. DEPARTMENT OF ECE PAGE NO. but the performance is critical. the floating point market is the fastest growing segment. the same as the signal data in DSPs.-51 . the cost of the DSP is insignificant. 16 bits for fixed-point. iterated MACs require additional bits for overflow headroom. 16. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. For this application. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. depending whether single or double precision is used. Three data word widths are important to consider in the internal architecture of a DSP. which is 24 bits for floating-point. in integer as well as real values. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. Second. However.point devices. For a single 16-bit by 16-bit multiplication. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. The second word width is that of the coefficients used in multiplications. at a price of several hundred-thousand dollars each. the internal representations of data in floating-point DSPs are more exact than in fixed-point. or a 48-bit product for a single 24-bit by 24-bit multiplication. While fixed-point coefficients are 16 bits. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. this overflow headroom is 8 bits.

Designers felt need to automate these processes. This level is LSI (Large Scale Integration). and etc.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5.) on a chip. At this point design process started getting very complicated. I/O peripheral devices and etc. Using latest CAD tools could solve the problem. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. This way of designing (using CAD tools) is certainly a revolution in electronic industry. registers..e.. . At this point design process still became critical. i. Rapid advances in Software Technology and development of new higher level programming languages taken place. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). With advent of new technology. i. Using design at this level.-52 .) on an IC. This created new challenges to digital designers as well as circuit designers. using this scale of integration people succeeded to make digital subsystems (Microprocessor. This may be leading to development of sophisticated electronic products for both consumer as well as business. DEPARTMENT OF ECE PAGE NO. counters. for design electronics circuits with assistance of software programs. One can fabricate a chip contains more than Million of gates. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. In this process. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency.e. multiplexes. one can create digital sub blocks (adders. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. It became very easy to a designer to verify functionality of design at various levels. Later Integrated Circuits (ICs) were invented. because of manual converting the design from one level to other. CMOS (Complementary Metal Oxide Semiconductor) process technology.

3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language. .32-BIT FLOATING POINT PROCESSOR 5.-53 .2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5. DEPARTMENT OF ECE PAGE NO.

models written in this language can be verified using a VHDL simulator. this version of the language is known as the IEEE STD 1076-1987. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. According to IEEE rules. Therefore. documentation. Different chip vendors can provide VHDL descriptions of their components to system designers. Consequently. and many ambiguities present in the 1987 version of the language were resolved.3. The language has also been recognized as an American National Standards Institute (ANSI) standard. available from IEEE.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. a need for a standardized hardware description language for the design. however. the language was upgraded with new features. This new version of the language is known as the IEEE STD 1076-1993.-54 .     5. Thus. DEPARTMENT OF ECE PAGE NO. This subset is usually sufficient to model most applications .32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits.  The language can be used as a communication medium between different CAD and CAE tools .1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language  VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. The IEEE in the December 1987 standardized VHDL language.3.  The language can be used as exchange medium between chip vendors and CAD tool users. It is a hardware description language that can be used to model a digital system at many levels of abstraction. 5. the syntax of many constructs was made more uniform. The official language description appears in the IEEE standard VHDL language Reference manual.The complete language. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. ranging from the algorithmic level to the gate level. and verification of the digital systems was generated. Reprocurement and reuse was also a big issue.

Z:out BIT).  It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. and behavioral. N:outBIT). As a set of concurrent assignment statements (to represent data flow) 3. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X.32-BIT FLOATING POINT PROCESSOR TEC  The language supports hierarchy. The internal view of the device specifies functionality or structure.3.  Various digital modeling techniques. In VHDL each device model is treated as a distinct representation of a unique device. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. human-readable. DEPARTMENT OF ECE PAGE NO. can be modeled as a set of interconnected subcomponents.  Arbitrarily large designs can be modeled using the language. such as finite –state machine descriptions. End component. .  The language supports flexible design methodologies: top-down. It supports both synchronous and asynchronous timing models. Such a model for the HALF_ADDER entity. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. End component. or mixed. can be modeled using the language. bottom-up. 1. in turn. Y: in BIT. B. Dataflow. M: in BIT. and there are no limitations imposed by the language on the size of the design. Structural style of modeling: In this one an entity is described as a set of interconnected components. and machine-readable. called an Entity. Each Entity is described using one model. 5.-55 . This model specifies the external view of the device and one or more internal views. that is a digital can be modeled as asset of interconnected components. B.  The language is publicly available. Component And2 Port (L. which contains one external view and one or more internal views. The Entity is thus a hardware abstraction of the actual hardware device. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. CARRY). each component.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. As a set of interconnected components (to represent structure) 2. SUM) A1: AND2portmap (A.  The language supports three basic different styles: Structural. Begin X1: Xor2portmap (A. and Boolean equations.

It comprises three different design entry tools. The data flow model for the half adder is described using two concurrent signal assignment statements . which are specified inside a process statement.3. 13641995 standard. designs.4.4 INTRODUCTION TO HDL TOOLS 5. several debugging tools.In a signal assignment statement.1. do not explicitly specify the structure of the entity but merely its functionality.-56 . 5. graphical and textual simulation output viewers. DEPARTMENT OF ECE PAGE NO.3. The architecture body is composed of two parts: the declaration part and the statement part. and auxiliary utilities designed for easy management of resource files.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. 1076-1993 standard. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order.1.the entity declaration for half adder specifies the interface ports for this architecture body.32-BIT FLOATING POINT PROCESSOR TEC End ha. . Verilog.4 DATAFLOW STYLE OF MODELING: In this modeling style. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. and EDIF and mixed VHDL-Verilog-EDIF designs. The name of the architecture body is ha . SIMULATION TOOL 5. A process statement is a concurrent statement that can appear with in an architecture body. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. the symbol <=implies an assignment of a value to a signal. 5. and libraries. The declared components are instantiated in the statement part of the architecture body using component instantiation. 5. Verilog compiler. VHDL'93 compiler. Two component declarations are present in the declarative part of the architecture body.2. single simulation kernel.4.4. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position. 5. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. These sets of sequential statements.

SDF files must comply with OVI Standard Delay Format Specification Version 2. 4. 2.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language.-57 . modification and procurement of hardware system. The contents of the default-working library of the design. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. Design Browser: The Design Browser window displays the contents of the current design. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. b. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. The keyword coloring is also available when HDL Editor is used for editing macro files. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. the communication of hardware design and test verification data. The editor is tightly integrated with the simulator to enable debugging source code. It allows you to graphically edit waveforms so as to create desired test vectors.0. 5. 3. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. Resource files attached to the design. DEPARTMENT OF ECE PAGE NO.1/D1. . The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. the maintenance. 5. and Tcl scripts. that is: a. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). The VITAL-compliant models can be annotated with timing data from SDF files. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. It displays specific syntax categories in different colors (keyword coloring). Perl scripts. 1.0 May 1997). HDL Editor: HDL Editor is a text editor designed for HDL source files.1.4. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029.

-58 . respectively for VHDL.vhd) • Verilog file (. transistors or gates) and their interconnection. and scripts. • The Active-HDL simulator provides two simulation engines.asf) • Block diagram file (.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. or EDIF objects declared within a selected region of the current design.v) • EDIF net list file (.32-BIT FLOATING POINT PROCESSOR TEC c. Verilog. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. 5. Active-HDL provides three compilers. and EDIF. Verilog. The structure of the design unit selected for simulation. All Active-HDL tools output their messages to Console. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. DEPARTMENT OF ECE PAGE NO. A net list is a set of statements that specifies the elements of a circuit (for example. Verilog. macros. or EDIF file containing HDL code (or net list) generated from the diagram. In Active-HDL. VHDL. Cycle-based simulation is significantly faster than event-driven. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. Compilation: Compilation is a process of analysis of a source file. the compiler analyzes the intermediate VHDL.bde) In the case of a block or state diagram file. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. d.EDIF) • State diagram file (. . a source file can be on of the following: • VHDL file (. 6. When you choose a menu command or toolbar button for compilation.4.

Verilog HDL.3.4. DEPARTMENT OF ECE PAGE NO. including: • HDL (VHDL. This overview explains the general progression of a design through ISE from start to finish.2 Design Entry: • ISE Text Editor . HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. and finally produce a bit stream for your device configuration.32-BIT FLOATING POINT PROCESSOR TEC Fig4.4. .4.6 SYNTHESIS TOOL: 5.-59 .6. ISE enables you to start your design with any of a number of different source types.The ISE Text Editor is provided in ISE for entering design code and viewing reports. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities. 5. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD. including ModelSim Xilinx Edition and the HDL Bencher test bench generator.1: Simulation 5. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.6.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.5.

Place and Route (PAR) . The state machine will be created in HDL. PACE . Constraints Editor . view.State CAD allows you to specify states.-60 .4. and after fitting and routing a CPLD design.The Constraints Editor allows you to create and modify the most commonly used timing constraints. DEPARTMENT OF ECE PAGE NO. CORE Generator .The Floor planner allows you to view a graphical representation of the FPGA. Map . to system-level building blocks such as filters.The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. Floor planner . With Timing Analyzer.The PAR program accepts the mapped design.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. and pin assignments.The Map program maps a logical design to a Xilinx FPGA. placing or routing an FPGA design. Chip Viewer (CPLD only) . transitions.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. and memories. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow. • • • • • • • . including routing. and produces output for the bit stream generator. Timing Analyzer .The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. and Area Group constraints.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor . • • • • 5. macro cell details. FPGA Editor . equations.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. Fit (CPLD only) .3 Implementation: • Translate . and to view and modify the placed design. analysis can be performed immediately after mapping. FIFOs. Global logic.6.The Chip Viewer tool provides a graphical view of the inputs and outputs. transforms. places and routes the FPGA.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. State CAD State Machine Editor .The FPGA Editor allows you view and modify the physical implementation. and actions in a graphical editor.

Integration with ChipScope Pro.The iMPACT tool generates various programming file formats.-61 .6.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration. iMPACT . and subsequently allows you to configure your device.4. XPower .4 Device Download and Program File Formatting: • BitGen .XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices. • • • .32-BIT FLOATING POINT PROCESSOR TEC 5. DEPARTMENT OF ECE PAGE NO.

multiplication and division are done using active HDL tool and the results are as follows: 6.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .-62 . DEPARTMENT OF ECE PAGE NO.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. subtraction. .1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.

Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . .32-BIT FLOATING POINT PROCESSOR TEC 6. DEPARTMENT OF ECE PAGE NO.2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.-63 .

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6.-64 . . DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC 6.3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format.

4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.-65 . . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO.4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.

subtraction.-66 . multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. DEPARTMENT OF ECE PAGE NO. Basic arithmetic operations such as addition.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. The Functional-simulation has been successfully carried out with the results matching with the expected ones. • • Procedures for performing basic arithmetic operations are been formed. . • 7.

unpredictable events can occur on an assembly line. Many levels of signal input from light. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. x-rays. DEPARTMENT OF ECE PAGE NO.-67 .32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. but need to use only a small subset of the range for target acquisition and identification. or something might unexpectedly block its range of motion. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. feedback is well out of the ordinary operating range. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. however. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. However. enable imaging systems to achieve a much higher level of recognition and definition for the user. The wide dynamic range of a floating-point DSP. The radar system may be tracking in a range from 0 to infinity. Wide dynamic range also plays a part in robotic design. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. The greater precision of signal data. . In these cases. Since the subset must be determined in real time during system operation. For instance. Normally. together with the device’s more accurate internal representations of data. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. the robot might weld itself to an assembly unit.

computer. Williams.intel.ieeexplore. P. J.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY  Fraeman. Hayes.. 281-317  Yamamoto.-68 . In: Stone. (1975) Stack computers. (Ed. pp. DEPARTMENT OF ECE PAGE NO. Computer. M.1109/SNPD. T. W. July 1981. R. 14(7) 68-78 REFERENCES  www.. (1981) A survey of high-level language machines in Japan. M. pp. 1975. & Zaremba.2007.org/portal/web/csdl/doi/10. (1986) A 32 bit processor architecture for direct execution of Forth. 28-30 November 1986.com . In: 1986 FORML Conf. H. Proc. (1987) The Implementation of Functional Programming Languages. Pacific Grove CA. 197-210  Jones.) Introduction to Computer Architecture. Prentice-Hall.46  www. Chicago.ieee. S.org  www.. New York  McKeeman. Science Research Associates.

std_logic_arith.all.std_logic_unsigned.Compute Ea-Eb -2.all. variable Temp :Std_logic_vector(6 downto 0). use IEEE. begin temp:=x. b : in std_logic_vector(31 downto 0).32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. end Fadd.-69 . --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . y : out std_logic_vector(31 downto 0) ). --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc. use IEEE.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0. use IEEE. DEPARTMENT OF ECE PAGE NO.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.all.std_logic_1164.

Sign Of Resultant Mantissa variable W. b :=Data(31). -. Eb :=Data(30 downto 23). end loop. end loop.Number Of Shifts variable Ma. -. -.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0). Ma:=MaIn.Mangitude Of Two mantissas variable ES : std_logic.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. -. Ea :=Acc(30 downto 23).Sign Of Two exponents variable s1. end function.Sign Of Two mantissas variable Sign : std_logic.Z : std_logic_vector(1 downto 0).Resultant Exponent variable Ns : integer. variable X : std_logic_vector(31 downto 0). Z :=(a&b). -. -. a :=Acc(31). -.b : std_logic.Internal Register variable MbIn : std_logic_vector(22 downto 0).Mb : std_logic_vector(22 downto 0). IE:=Eb(6 downto 0).Subtraction of Exponents --*2. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). -. -. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).s2 : std_logic. else TEC Sum:=Sum.-70 . end if. -.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Sign Of Resulant Exponent variable a.Eb : std_logic_vector(7 downto 0). DEPARTMENT OF ECE PAGE NO.Internal Register variable Ea. -. -. --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0). MbIn:=Data(22 downto 0).Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. return sum. Es:=Eb(7) . --***************************************************************** --*Equalization of Exponents includes two steps --*1.Final Result begin MaIn:=Acc(22 downto 0).

end loop. ES:=Ea(7). Ma:=MaIn. Mb:=Mb. when "11" => Mb:=MbIn. IE:=Ea(6 downto 0). Ma:=MaIn. IE:=Ea(6 downto 0).-71 . when "01" => Mb:=MbIn. end if. Ma:=Ma. else NS:=Ns. Ma:=MaIn. . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7).32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Es:=Ea(7). DEPARTMENT OF ECE PAGE NO. end loop. ES:=Ea(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop. IE:=Eb(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). IE:=IE. end loop. IE:=Ea(6 downto 0). when "10" => Mb:=MbIn. ES:=Eb(7). NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)).

Mb:=Mb. elsif(Ma=Mb) then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. case W is when "00" => when "11" => when "01" => when "10" => .32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Eb(7). ES:=Ea(7).-72 . else NS:=Ns. end if. when others => Null. end loop. end case. elsif(Ea<Eb) then sign:='1'. IE:=IE. Ma:=Ma. end if. --******************Addition of Mantissas**************************** IR:=Ma+Mb. PAGE NO. s2:=Data(31). W :=(s1&s2). end if. --***********logic for the sign of the mantissa********************** s1:=Acc(31). else sign:=sign. if(Ea>Eb) then sign:='1'. DEPARTMENT OF ECE sign:='0'. IE:=Eb(6 downto 0). elsif(Ma<Mb) then sign:='1'. else sign:=sign. sign:='1'. if(Ea>Eb) then sign:='0'.

elsif(Ma=Mb) then sign:='0'.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end function.b). end if. else sign:=sign. begin process(a. else sign:=sign. when others => null. DEPARTMENT OF ECE PAGE NO. end Fadd. end if. elsif(Ma<Mb) then sign:='0'. end process. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'.b) begin y<=float_add(a. return X. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . end case. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)).-73 * .

DEPARTMENT OF ECE PAGE NO. use IEEE. y : out std_logic_vector(31 downto 0)).std_logic_arith.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.std_logic_unsigned. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout. end Fsub. use ieee. begin temp:=x. use ieee.Compute Ea-Eb 2.std_logic_1164.-74 .32-BIT FLOATING POINT PROCESSOR ----1.all. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). b : in STD_LOGIC_VECTOR (31 downto 0). .Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.Shift the that has lesser Exponent by Ea-Eb places to the right * 3.all.all. variable Temp : Std_logic_vector(6 downto 0).

Mangitude Of Two Mantissas variable ES : std_logic. else Sum:=Sum.s2 : std_logic.MbIn: std_logic_vector(22 downto 0).Number Of Shifts variable Ma.Resultant Exponent variable Ns : integer. end loop. -.Internal Register variable Ea. -. end function.Subtraction of Exponents * * . Eb :=Data(30 downto 23).Mb : std_logic_vector(22 downto 0).b : std_logic. MbIn:=Data(22 downto 0). DEPARTMENT OF ECE PAGE NO. -.Eb : std_logic_vector(7 downto 0). -. a :=Accout(30).Sign Of Two Mantissas variable sign : std_logic. b :=Data(30). -. --*********************variable Declarations*********************** TEC variable MaIn. -. -. -. -. Z :=(a&b). variable X : std_logic_vector(31 downto 0). -.Sign Of Resultant Mantissa variable W. --***************************************************************** --*Equalization of Exponents includes two steps * * --*1.-75 . -. return sum.Sign Of Resulant Exponent variable a. Ea :=Accout(30 downto 23).Final Result begin MaIn:=Accout(22 downto 0). end if.Z : std_logic_vector(1 downto 0).Two exponents Including Sign variable IR : std_logic_vector(22 downto 0).32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Sign Of Two Exponents variable s1.

ES:=Ea(7). Ma:=MaIn. end loop.-76 . end loop. Ma:=Ma. IE:=Ea(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Mb:=Mb. Ma:=MaIn.32-BIT FLOATING POINT PROCESSOR --*2. ES:=Ea(7). DEPARTMENT OF ECE PAGE NO. IE:=Eb(6 downto 0). ES:=Eb(7). when "01" => Mb:=MbIn. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. IE:=IE. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=Ea(6 downto 0). ES:=Ea(7). else NS:=Ns. end if. TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)).

when others => null. ES:=Eb(7). end loop.-77 . TEC Ma:=MaIn. ES:=Ea(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end loop. else NS:=Ns. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). IE:=Eb(6 downto 0). Mb:=Mb. IE:=Eb(6 downto 0). end loop. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end case. DEPARTMENT OF ECE PAGE NO. IE:=IE. ES:=Ea(7).32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). . --******************Subtraction of Mantissas************************ IR:=Ma-Mb. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). when "11" => Mb:=MbIn. Ma:=MaIn. end if. IE:=Ea(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). Ma:=Ma. ES:=Eb(7).

else sign:=sign. case W is when "00"=> sign:='0'.-78 . end if. end if. else sign:=sign. elsif (Ma=Mb) then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. when "01"=> if(Ea>Eb)then sign:='0'. s2:=Data(31). end if. DEPARTMENT OF ECE PAGE NO. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif(Ma<Mb) then sign:='1'. elsif(Ma<Mb) then sign:='0'. elsif(Ea<Eb) then sign:='1'. else sign:=sign. end if. else sign:=sign. when "10"=> if (Ea>Eb)then sign:='1'. elsif (Ea<Eb) then sign:='0'. elsif (Ma=Mb) then sign:='0'. when "11"=> sign:='1'. . W:=(s1&s2).32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31).

DEPARTMENT OF ECE PAGE NO. b: in STD_LOGIC_VECTOR (31 downto 0). . --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).-79 . use IEEE. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)).Addtion of the Exponents 5.b).std_logic_unsigned. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. end case. begin process(a. use IEEE. return X.32-BIT FLOATING POINT PROCESSOR TEC when others=> null.b) begin y<=float_sub(a.all. end process.all. y: out STD_LOGIC_VECTOR (31 downto 0) ). end function. end Fmul.Multiplication of the Mantissas * * -************************************************************************** library IEEE.std_logic_1164. end f_sub.

-. s2:=Data(31). m1 :=Accout(10 downto 0).-80 .m2 : std_logic_vector(10 downto 0).Carry variable W. end case. m2 :=Data(10 downto 0).e2 : std_logic_vector(7 downto 0). DEPARTMENT OF ECE PAGE NO. when others=> s:='1'.s2 : std_logic.Two Exponents Icluding Sign variable m1. Z :=(s1&s2). -. when "11" => s:='0'. -. -.Final Result begin Carry:='0'.Z : std_logic_vector(1 downto 0). -. -.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0).Sign Of Resultant Mantissa variable a.Eb : std_logic_vector(6 downto 0). -.Sign Two Exponents variable s1. e2 :=Data(30 downto 23). case Z is when "00" => s:='0'.Resultant exponent variable m : std_logic_vector(21 downto 0). --************logic for the sign of the Mantissa******************* s1:=Accout(31). -. e1 :=Accout(30 downto 23). -.Resultant Mantissa variable carry : std_logic.b : std_logic. -. variable x : std_logic_vector(31 downto 0).32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout. .Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1.sign Two Mantissas variable Ea. -.Magnitude O Two Mantissas variable s : std_logic.Magnitude Of Two Exponents variable c : std_logic.

when "01" => if(Ea>Eb) then c:='0'. a :=Accout(30). end if. Eb:=e2(6 downto 0). e:=Ea+Eb. else c:='0'. e:=Ea+Eb. W :=(a&b). e:="0000000". e:="0000000". elsif(Ea<Eb) then c:='1'. --*************logic for multiplication************************* m:=m1*m2. b :=Data(30). e:=Ea-Eb. case W is when "00" => c:='0'. . e:=Eb-Ea. else c:='0'. DEPARTMENT OF ECE PAGE NO. c:='1'. e:=Ea-Eb. elsif(Ea<Eb) then c:='0'.-81 . end if. when "11" => when others => null.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). e:=Eb-Ea. end case. when "10" => if(Ea>Eb) then c:='1'.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

end if. else c:='0'. elsif(Ea<Eb) then c:='0'. e:=Ea+Eb. e:=Eb-Ea. if(Ea>Eb) then c:='0'. e:=Ea-Eb. e:="0000000". e:="0000000". elsif(Ea<Eb) then c:='0'. else c:='0'. Eb:=e2(6 downto 0).32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. elsif(Ea<Eb) then c:='0'. elsif(Ea<Eb) then c:='1'. e:=Ea+Eb. a :=e1(7). when "10"=> if(Ea>Eb) then c:='1'. e:=Eb-Ea. e:=Eb+Ea. . else c:='0'. end if. e:="0000000". end if. e:=Ea-Eb. Z :=(a&b).-86 . case Z is when "00" => if(Ea>Eb) then c:='0'. b :=e2(7). if(Ea>Eb) then c:='1'.

return X. DEPARTMENT OF ECE PAGE NO. end function. e:="0000000". end if.b) begin Y<=float_div(a. begin process(a. else c:='0'. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)).b).-87 .32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. when others=> null. end F_div. end case. TEC . end process.

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