Hitachi LCD 32LD8700

No.
0210
32LD8700C
32LD8700U
32LD8700TU
32LD8600
SERVICE MANUAL 32LD8A10
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH 37LD8600
37LD8700C
37LD8700U
CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual. Data contained within this Service
manual is subject to alteration for
improvement.
ATTENTION: Les données fournies dans le présent

manuel d’entretien peuvent faire l’objet
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité»
de modifications en vue de perfectionner
et les «Notices de sécurité du produit» présentés dans le présent manuel.
le produit.
Die in diesem Wartungshandbuch

enthaltenen Spezifikationen können sich
VORSICHT: zwecks Verbesserungen ändern.
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
COLOUR TELEVISION
October 2006
TABLE OF CONTENTS
1 INTRODUCTION 1
2 TUNER 1
3 IF PART (TDA9886) 1
4 MULTI STANDARD SOUND PROCESSOR 2
5 VIDEO SWITCH TEA6415 2
6 AUDIO AMPLIFIER STAGE WITH TPA3004D2 2
7 MICROCONTROLLER 3
8 EEPROM 24C32 3
9 CLASS AB STEREO HEADPHONE DRIVER TDA1308 3
10 SAW FILTERS 3
11 IC DESCRIPTIONS 4
11.1. TEA6415C 5
11.1.1. General Description 5
11.1.2. Features 5
11.1.3. Pinning 5
11.2. 24LC02 6
11.2.1. Description 6
11.2.2. Features 6
11.2.3. Pinning 6
11.3. TCET1102G Optocoupler 7
11.3.2. General Features 7
11.3.3. Applications 8
11.4. SVP-EX 52 8
11.5. TL431 8
11.5.2. Features 8
11.6. 24C32 8
11.6.2. Features 8
11.6.3. Pinning 9
11.7. 74LVC14A 10
11.7.2. Features 10
11.7.3. Pinning 10
11.8. TEA6420 11
11.8.1. Features 11
11.8.3. Pin Connections 11
11.9. CS4334 11
11.9.1. Features 11
11.9.3. Pin Descriptions 12
11.10. GAL16LV8 12
11.10.2. Features 12
11.11. K6R4008V1D 13
11.11.3. Pin Description 14
11.12. L6562 14
11.12.3. Pin Description and Descriptions 15
i
TFT TV Service Manual
11.13. LM1117 15
11.13.3. Applications 15
11.13.4. Connection Diagrams 16
11.14. LM317 16
11.15. LM809 16
11.15.3. Pinning 17
11.16. MSP34X1G 17
11.16.1. Introduction 17
11.17. M29W040B 20
11.17.3. Pin Descriptions 21
11.18. MC33202 21
11.19. PCF8574 22
11.19.3. Pinning 22
11.20. PI5V330 23
11.21. SDA55XX (SDA5550) 23
11.22. Sil 9993 23
11.23. NCP1014 24
11.23.3. Pin Description and Descriptions 25
11.24. SN74CB3Q3305 25
11.25. ST24LC21 26
11.26. LM2576 27
11.27. TDA1308 27
11.27.3. Pinning 28
ii
11.28. TDA9886 28
11.28.3. Pinning 28
11.29. TPA3004D2 29
11.29.3. Pinning 30
11.30. µPA672T 31
11.30.3. Pin Connection 31
11.31. VPC3230D 31
11.31.2. Pin Connections and Short Descriptions 32
12 SERVICE MENU SETTINGS 33
12.1. Picture Adjust 33
12.2. SOUND1 34
12.3. SOUND 2 34
12.4. Options 34
12.5. TV Norm 35
12.6. Features 35
12.7. Teletext 35
12.8. Source 35
12.9. Menu Languages 1 & 2 35
13 BLOCK DIAGRAM 36
14 SCHEMATIC DIAGRAMS 37
14.1. Main Board 37
14.2. Power Board 45
14.3. Front AV Board 50
14.4. Amplifier Board 51
15 CIRCUIT BOARD DIAGRAMS 52
15.1. Main Board 52
16 SPARES PARTLIST 53
17 WALL MOUNT TEMPLATE DIAGRAM (32-INCH MODELS ONLY) 54
iii
1. INTRODUCTION
TFT TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a
1366*768 panel with 16:9 aspect ratio. The TV is capable of operation in PAL, SECAM, NTSC
(playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including
German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8ȍ
speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a
media system.
It supports the following peripherals:

2 SCART sockets
1 AV input (CVBS + Stereo Audio)
1 SVHS input
1 Stereo Headphone input
1 Component input (YPbPr + Stereo Audio)
1 D-Sub 15 PC input
1 HDMI input
1 Stereo audio input for PC
Audio line out is taken from the scart with given scart-to-line out connector
2. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’,
I/I’, and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info on one of the Tuners in use.
General description of UV1316:

The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low
IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient
suppression of triple transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I2C-bus
4. Off-air channels, S-cable channels and Hyper band
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1. Gain control voltage (AGC) : 4.0V, Max: 4.5V
2. Tuning voltage
3. I²C-bus address select : Max: 5.5V
4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V
5. I²C-bus serial data : Min:-0.3V, Max: 5.5V
6. Not connected
7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V
8. ADC input
9. Tuner supply voltage : 33V, Min: 30V, Max: 35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal
PLL. The following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector,
VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap,
SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and
1
acquisition help, Audio amplifier and mute time constant, I²C-bus transceivers and MAD (module
address), Internal voltage stabilizer.
external reference signal
CAGC(pos) VIF-PLL or 4MHz crystal
filter
(1)
TOP TAGC VAGC VPLL REF AFC
9(8) 14(15) 16 19(21) 15(16) 21(23)
CAGC(neg) CBL
TUNER AGC VIF-AGC RC VCO DIGITAL VCO CONTROL AFC DETECTOR
VIF2 2(31)
SOUND TRAPS (18)17 CVBS
VIF1 1(30) VIF-PLL
4.5 to 6.5 MHz video output: 2Vp-p
TDA9885 (1.1Vp-p without trap)
TDA9886
(7)8 AUD
SINGLE REFERENCE QSS MIXER AUDIO audio output
SIF2 24(27) INTERCARRIER MIXER PROCESSING (3)5 DEEM
AND AM DEMODULATOR AND SWITCHES
SIF1 23(25)
de-emphasis
MAD network
(4)6 AFD
NARROW-BAND
OUTPUT IIC-BUS FM-PLL
SUPPLY SIF AGC CAF
PORTS TRANSCEIVER DEMODULATOR
CAGC
(6, 12, 13, 14,

17, 19, 25, 28,
20(22) 18(20) 29, 32) 13 3(1) 22(24) 11(10) 10(9) 7(5) 12(11) 4(2)
VP AGND n.c. OP1 OP2 SCL SDA DGND SIGMAD FMPLL
sound intercarrier output FM-PLL

and MAD select filter
(1) Not connected for TDA9885
4. MULTI STANDARD SOUND PROCESSOR
The MSP34x1G family of single-chip Multistandard Sound Processors covers the sound processing of
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on
a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard
(EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments.
5. VIDEO SWITCH TEA6415

In case of three or more external sources are used, the video switch IC TEA6415 is used. The main
function of this device is to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level
of the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment
is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used
as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching
possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible
to have the same input connected to several outputs.
6. AUDIO AMPLIFIER STAGE WITH TPA3004D2

The TPA3004D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3004D2 can drive stereo speakers as low as 8 . The high efficiency of the
TPA3004D2 eliminates the need for external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a
range of gain from –40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are
also dc voltage controlled with a range of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
2
7. MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and
provides dedicated graphic features designed for modern low class to mid range TV sets. The SDA
55xx provides also an integrated general purposefully 8051-compatible microcontroller with specific
hardware features especially suitable in TV sets. The microcontroller core has been enhanced to
provide powerful features such as memory banking, data pointers and additional interrupts, etc. The
internal XRAM consists of up to 16 kBytes. The microcontroller provides an internal ROM of up to 128
kBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The 8-bit
microcontroller runs at 33.33 MHz internal clock. SDA 55xx is realized in 0.25 micron technology with
2.5 V supply voltage for the core and 3.3 V for the I/O port pins to make them TTL compatible. Based
on the SDA 55xx microcontroller the MINTS software package was developed and provides dedicated
device drivers for many Micronas video & audio products and includes a full blown TV control SW for
the PEPER application chassis. The SDA 55xx is also supported with powerful design tools like
emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and TEDIpro OSD development SW
by Tara Systems.
8. EEPROM 24C32
The Microchip Technology Inc. 24C32 is a 4Kx8 (32 Kbit) Electrically Erasable PROM. This device has
been developed for advanced, low power applications such as personal communications or data
acquisition. The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte
pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that
changes frequently. The 24C32 is capable of both random and sequential reads up to the 32K
boundary. Functional address lines allow up to 8 - 24C32 devices on the same bus, for up to 256K bits
address space. Advanced CMOS technology makes this device ideal for low-power non-volatile code
and data applications.
9. CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package.
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital
audio applications.
10. SAW FILTERS

K9656M:
Standard:
• B/G
• D/K
•I
• L/L’
Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40.40 MHz (L’) and 39.75 MHz (L’- NICAM)
• Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz
Terminals
• Tinned CuFe alloy
Pin configuration
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output
K3958M:
Standard:
• B/G
• D/K
•I
• L/L’
3
Features
• TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
• Constant group delay
Terminals
Tinned CuFe alloy
Pin configuration
1 Input
2 Input - ground
3 Chip carrier - ground
4 Output
5 Output
11. IC DESCRIPTIONS
TEA6415C
24LC02
TCET1102G OPTOCOUPLER
SVP-EX 52
TL431
24C32
74LVC14A
TEA6420D
CS4334
GAL16LV8
K6R4008V1
L6562D
LM1117
LM317T
LM809
MSP3410G
M29W040B
MC33202
PCF8574
PI5V330
SDA5550
SII9993
NCP1014
SN74CB3Q3305
ST24LC21
LM2576
MC34063
TDA1308
TDA9886T
TPA3002D2
μPA672T
VPC3230D
4
11.1. TEA6415C
11.1.1. General Description

The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be
switched on only one of each input. On each input an alignment of the lowest level of the signal is made
(bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input
and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an
external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or
Chroma input (with external resistor bridge). All the switching possibilities are changed through the
BUS. Driving 75 load needs an external transistor. It is possible to have the same input connected to
several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In
this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16
bits is necessary to determine one configuration.
11.1.2. Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor
bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
11.1.3. Pinning
1. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
2. Data : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
4. Clock : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
7. Prog
8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
9. Vcc : 12V
12. Ground
13. Output : 5.5Vpp, Min : 4.5Vpp
19. Ground
20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
5
11.2. 24LC02
11.2.1. Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby and active currents of only 1μA and 1mA,
respectively. The 24XX02 also has a page write capability for up to 8 bytes of data.
11.2.2. Features
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
• Organized as 1 block of 256 bytes (1 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C
11.2.3. Pinning
6
11.3. TCET1102G Optocoupler

The TCET110. / TCET2100/ TCET4100 consist of a phototransistor optically coupled to a gallium
arsenide infrared-emitting diode in a 4-lead up to 16-lead plastic dual inline package.
The elements are mounted on one lead frame using a coplanar technique, providing a fixed distance
between input and output for highest safety requirements.
11.3.2. General Features

x CTR offered in 9 groups
x Isolation materials according to UL94-VO
x Pollution degree
(DIN/VDE 0110 / resp. IEC 664)
x Climatic classification 55/100/21 (IEC 68 part 1)
x Special construction:
x Therefore, extra low coupling capacity of typical 0.2 pF, high Common Mode Rejection
x Low temperature coefficient of CTR
x G=Leadform10.16mm; provides creepage distance > 8 mm,
for TCET2100/ TCET4100 optional;
x suffix letter 'G' is not marked on the optocoupler
x Coupling System U
7
11.3.3. Applications
Circuits for safe protective separation against electrical shock according to safety class II (reinforced
isolation):
For appl. class I – IV at mains voltage 300 V
For appl. class I – III at mains voltage 600 V
According to VDE 0884, table 2, suitable for: Switch-mode power supplies, line receiver, computer
peripheral interface, microprocessor system interface.
11.4. SVP-EX 52

SVP EX52 supports two CVBS and one Svideo,two HD YPbPr component or PC RGB input and one
24-bit digital input ports.Supports HD YPbPr de-interlacing mode and 3D-comb video mode.
LVDS "single" port is built-in, supporting output resolution up to SXGA, 1280x1024x60P.
11.5. TL431

The TL431/TL431Aare three-terminal adjustable regulator series with a guaranteed thermal stability
over applicable temperature ranges. The output voltage may be set to any value between Vref
(approximately 2.5 volts) and 36 volts with two external resistors These devices have a typical dynamic
output impedance of 0.2W Active output circuitry provides a very sharp turn-on characteristic, making
these devices excel lent replacement for zener diodes in many applications.
11.5.2. Features
x Programmable Output Voltage to 36 Volts
x Low Dynamic Output Impedance 0.20 Typical
x Sink Current Capability of 1.0 to 100mA
x Equivalent Full-Range Temperature Coefficient of
50ppm/°C Typical
x Temperature Compensated For Operation Over Full Rated
Operating Temperature Range
x Low Output Noise Voltage
x Fast Turn-on Response
11.6. 24C32

The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This
device has been developed for advanced, low power applications such as personal communications or
data acquisition. The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte
pages, or 64 bytes. It also features a fixed 4K-bit block of ultra-high endurance memory for data that
changes frequently. The 24C32 is capable of both random and sequential reads up to the 32K
boundary. Functional address lines allow up to 8 - 24C32 devices on the same bus, for up to 256K bits
address space. Advanced CMOS technology makes this device ideal for low-power non-volatile code
and data applications.
11.6.2. Features
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150μA at 5.5V
- Standby current 1μA typical
• Industry standard two-wire bus protocol, I2C™ compatible
-Including 100 kHz and 400 kHz modes
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
8
- 10,000,000 Erase/Write cycles guaranteed for High Endurance Block
- 10,000,000 E/W cycles guaranteed for Standard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• Temperature ranges:
-Commercial (C): 0°C to +70°C
-Industrial (I): -40°C to +85°C
11.6.3. Pinning
PIN Function Table
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
The A0...A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire
bus standard. The levels applied to these pins define the address block occupied by the device in the
address map. A particular device is selected by transmitting the corresponding bits (A2, A1, and A0) in
the control byte.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an
open drain terminal; therefore the SDA bus requires a pull-up resistor to VCC (typical 10KQ for 100
kHz, 1KQ for 400 kHz).
9
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
11.7. 74LVC14A
11.7.1. Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This
feature allows the use of these devices as translators in a mixed 3.3 and 5V environment. The
74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
11.7.2. Features
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.
11.7.3. Pinning
10
11.8. TEA6420
11.8.1. Features
• 5 Stereo Inputs
• 4 Stereo Outputs
• Gain Control 0/2/4/6dB/Mute for each Output
• Cascadable (2 different addresses)
• Serial Bus Controlled
• Very low Noise
• Very low Distortion
11.8.2. Description
The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are
changed through the I2C bus.
11.8.3. Pin Connections
11.9. CS4334
11.9.1. Features
• Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering
• 24-Bit Conversion
• 96 dB Dynamic Range
• -88 dB THD+N
• Low Clock Jitter Sensitivity
• Single +5V Power Supply
• Filtered Line Level Outputs
• On-Chip Digital De-emphasis
• Popgaurd® Technology
• Functionally Compatible with CS4330/31/33

The CS4334 family members are complete, stereo digital-to-analog output systems including
interpolation, 1-bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9
support all major audio data interface formats, and the individual devices differ only in the supported
interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output
controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for
infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock
frequency. The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power
supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players,
SVCD players, and A/V receivers.
11
11.9.3. Pin Descriptions
11.10. GAL16LV8
11.10.1. Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance
available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The
GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which
combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and
supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are
specified.
11.10.2. Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
- I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
12
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
11.10.3. Pin connections
11.11. K6R4008V1D
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288
words by 8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin
which operates faster than address access time at read cycle. The device is fabricated using
SAMSUNGƍs advanced CMOS process and designed for high-speed circuit technology. It is particularly
well suited for use in high-density high-speed system applications. The K6R4008V1D is packaged in a
400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
11.11.2. Features
• Fast Access Time 8, 10ns(Max.)
• Low Power Dissipation
- Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
- Operating K6R4008V1D-08 : 80mA(Max.)
K6R4008V1D-10 : 65mA(Max.)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008V1D-J : 36-SOJ-400
K6R4008V1D-K : 36-SOJ-400(Lead-Free)
K6R4008V1D-T : 44-TSOP2-400BF
K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
13
11.11.3. Pin Description
11.12. L6562
11.12.1. Features
• TRANSITION-MODE CONTROL OF PFC PRE-REGULATORS
• PROPRIETARY MULTIPLIER DESIGN FOR MINIMUM THD OF AC INPUT CURRENT
• VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION
• ULTRA-LOW (70μA) START-UP CURRENT
• LOW (4 mA) QUIESCENT CURRENT
• EXTENDED IC SUPPLY VOLTAGE RANGE
• ON-CHIP FILTER ON CURRENT SENSE
• DISABLE FUNCTION
• 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE
The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible
with the predecessor L6561, it offers improved performance. The highly linear multiplier includes a
special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with
an extremely low THD, even over a large load range.
14
11.12.3. Pin Connections and Descriptions
11.13. LM1117

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load
current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is
available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two
external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-
223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the
output to improve the transient response and stability.
11.13.2. Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
11.13.3. Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
15
11.13.4. Connection Diagrams
SOT-223 TO-220 TO-252
Top View Top View

Top View
11.14. LM317

This monolithic integrated circuit is an adjustable 3-terminal positive voltage regulator designed to
supply more than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V. It employs
internal current limiting, thermal shut-down and safe area compensation.
11.14.2. Features
• Output Current In Excess of 1.5A
• Output Adjustable Between 1.2V and 37V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting
• Output Transistor Safe Operating Area Compensation
• TO-220 Package
11.14.3. Pin Description
11.15. LM809

The LM809/810 microprocessor supervisory circuits can be used to monitor the power supplies in
microprocessor and digital systems. They provide a reset to the microprocessor during power-up,
power-down and brown-out conditions. The function of the LM809/810 is to monitor the VCC supply
voltage, and assert a reset signal whenever this voltage declines below the factory-programmed reset
threshold. The reset signal remains asserted for 240 ms after VCC rises above the threshold. The
LM809 has an active-low RESET output, while the LM810 has an active-high RESET output. Seven
standard reset voltage options are available, suitable for monitoring 5V, 3.3V, and 3V supply voltages.
With a low supply current of only 15μA, the LM809/810 are ideal for use in portable equipment.
11.15.2. Features
• Precise monitoring of 3V, 3.3V, and 5V supply voltages
• Superior upgrade to MAX809/810
• Fully specified overtemperature
• 140 ms min. Power-On Reset pulse width, 240 ms typical
Active-low RESET Output(LM809)
Active-high RESET Output(LM810)
16
• Guaranteed RESET Output valid for VCC1V
• Low Supply Current, 15μAtyp
• Power supply transient immunity
11.15.3. Pinning
11.16. MSP34X1G
Multistandard Sound Processor Family
11.16.1. Introduction
The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on
a single chip. Figure shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound
feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G
includes the Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1)
Laboratories for with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the
“PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo
Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard
automat-ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can
be evaluated internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is
necessary (Automatic Sound Selection).
17
Source Select
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling
cycle (32 kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
11.16.2. Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
• Spatial effect for loudspeaker channel
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Dolby Pro Logic with DPL 351xA coprocessor
• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard
• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
• Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
• ASTRA Digital Radio (ADR) together with DRP 3510A
• All NICAM standards
• Korean FM-Stereo A2 standard

NC = not connected; leave vacant
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
DVSS: if not used, connect to DVSS
AHVSS: connect to AHVSS
18
Connection
Pin No. Pin Name Type Short Description
(if not used)
PLCC PSDIP PSDIP PQFP PLQFP
68-pin 64-pin 52-pin 80-pin 64-pin
1 16 14 9 8 ADR_WS OUT LV ADR word strobe
2 - - - - NC LV Not connected
3 15 13 8 7 ADR_DA OUT LV ADR Data Output
2
4 14 12 7 6 I2S_DA_IN1 IN LV I S1 data input
2
5 13 11 6 5 I2S_DA_OUT OUT LV I S data output
2
6 12 10 5 4 I2S_WS IN/OUT LV I S word strobe
2
7 11 9 4 3 I2S_CL IN/OUT LV I S clock
2
8 10 8 3 2 I2C_DA IN/OUT OBL I C data
2
9 9 7 2 1 I2C_CL IN/OUT OBL I C clock
10 8 - 1 64 NC LV Not connected
11 7 6 80 63 STANDBYQ IN OBL Stand-by (low-active)
2
12 6 5 79 62 ADR_SEL IN OBL I C bus address select
13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0
14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1
17 - - - - NC LV Not connected
Audio clock output
18 1 2 74 57 AUD_CL_OUT OUT LV
(18.432 MHz)
19 64 1 73 56 TP LV Test pin
20 63 52 72 55 XTAL_OUT OUT OBL Crystal oscillator
21 62 51 71 54 XTAL_IN IN OBL Crystal oscillator
22 61 50 70 53 TESTEN IN OBL Test pin
IF Input 2 (can be left
AVSS via
23 60 49 69 52 ANA_IN2+ IN vacant, only if IF input 1 is
56 pF/LV
also not in use)
IF common (can be left
AVSS via
24 59 48 68 51 ANA_IN- IN vacant, only if IF input 1 is
56 pF/LV
also not in use)
25 58 47 67 50 ANA_IN1+ IN LV IF input 1
26 57 46 66 49 AVSUP OBL Analog power supply 5V
- - - 65 - AVSUP OBL Analog power supply 5V
- - - 64 - NC LV Not connected
27 56 45 62 48 AVSS OBL Analog ground
- - - 61 - AVSS OBL Analog ground
28 55 44 60 47 MONO_IN IN LV Mono input
Reference voltage IF A/D
29 54 43 58 46 VREFTOP OBL
converter
30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right
31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left
32 51 - 55 43 ASG1 AHVSS Analog Shield Ground 1
39 44 - 48 36 SC4_IN_R IN LV SCART 4 input, right
40 43 - 47 35 SC4_IN_L IN LV SCART 4 input, left
41 - - 46 - NC LV or AHVSS Not connected
42 42 36 45 34 AGNDC OBL Analog reference voltage
43 41 35 44 33 AHVSS OBL Analog ground
- - - 43 - AHVSS OBL Analog ground
44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN
45 39 33 39 31 AHVSUP OBL Analog power supply 8V
46 38 32 38 30 CAPL_A OBL Volume capacitor AUX
47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left
48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right
49 35 29 35 27 VREF1 OBL Reference ground 1
50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left
51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right
52 - - 32 - NC LV Not connected
54 31 26 30 23 DACM_SUB OUT LV Subwoofer output
19
56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left
57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right
58 27 23 26 19 VREF2 OBL Reference ground 2
59 26 22 25 18 DACA_L OUT LV Headphone out, left
60 25 21 24 17 DACA_R OUT LV Headphone out, right
61 24 20 21 16 RESETQ IN OBL Power-on-reset
64 21 19 18 13 NC LV Not connected
2
65 20 18 17 12 I2S_DA_IN2 IN LV I S2-data input
66 19 17 16 11 DVSS OBL Digital ground
- - - 15 - DVSS OBL Digital ground
- - - 14 - DVSS OBL Digital ground
67 18 16 13 10 DVSUP OBL Digital power supply 5V
- - - 12 - DVSUP OBL Digital power supply 5V
- - - 11 - DVSUP OBL Digital power supply 5V
68 17 15 10 9 ADR_CL OUT LV ADR clock
11.17. M29W040B
The M29W040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On
power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or
EPROM. The M29W040B is fully backward compatible with the M29W040.The memory is divided into
blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
Each block can be protected independently to prevent accidental Program or Erase commands from
modifying the memory. Program and Erase commands are writ-ten to the Command Interface of the
memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the
memory by taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions identified. The
command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output
Enable and Write Enable signals control the bus operation of the memory. They allow simple
connection to most microprocessors, often without additional logic.
11.17.2. Features
• SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
• ACCESS TIME: 55ns
• PROGRAMMING TIME
- 10μs per Byte typical8
• UNIFORM 64 Kbytes MEMORY BLOCKS
• PROGRAM/ERASE CONTROLLER
- Embedded Byte Program algorithm
- Embedded Multi-Block/Chip Erase algorithm
- Status Register Polling and Toggle Bits
• ERASE SUSPEND and RESUME MODES
- Read and Program another Block during Erase Suspend
• UNLOCK BYPASS PROGRAM COMMAND
- Faster Production/Batch Programming
• LOW POWER CONSUMPTION
- Standby and Automatic Standby
• 100,000 PROGRAM/ERASE CYCLES per BLOCK
• 20 YEARS DATA RETENTION
- Defectivity below 1 ppm/year
• ELECTRONIC SIGNATURE
- Manufacturer Code: 20h
- Device Code: E3h
20
11.17.3. Pin Descriptions
11.18. MC33202

The MC33201/2/4 family of operational amplifiers provide railítoírail operation on both the input and
output. The inputs can be driven as high as 200mV beyond the supply rails without phase reversal on
the outputs, and the output can swing within 50 mV of each rail. This railítoírail operation enables the
user to make full use of the supply voltage range available. It is designed to work at very low supply
voltages (±0.9 V) yet can operate with a supply of up to +12V and ground. Output current boosting
techniques provide a high output current capability while keeping the drain current of the amplifier to a
minimum. Also, the combination of low noise and distortion with a high slew rate and drive capability
make this an ideal amplifier for audio applications.
11.18.2. Features
• Low Voltage, Single Supply Operation (+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Overídriven Input Signals
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ)
• 600 Output Drive Capability
• Extended Operating Temperature Ranges (í40° to +105°C and í55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
• PbíFree Packages are Available
21
11.19. PCF8574

The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most
microcontroller families via the two-line bidirectional bus (I2C).The device consists of an 8-bit quasi-
bidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes
latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt
line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports
without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple
slave device.
11.19.2. Features
• Operating supply voltage 2.5 to 6V
• Low standby current consumption of 10 μA maximum
• I2C to parallel port expander
• Open-drain interrupt output
• 8-bit remote I/O port for the I2C-bus
• Compatible with most microcontrollers
• Latched outputs with high current drive capability for directly driving LEDs
• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
• DIP16, or space-saving SO16 or SSOP20 packages.
11.19.3. Pinning
22
11.20. PI5V330

The PI5V330 is well suited for video applications when switching composite or RGB analogue. A
picture-in-picture application will be described in this brief. The pixel-rate creates video overlays so two
or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by
superimposing the output of a character generator on a standard composite video background.
11.21. SDA55XX (SDA5550)
11.21.1. General description

The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as
Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling
(WSS) data used for PAL plus transmissions (Line 23). The device also supports Closed caption
acquisition and decoding. The device provides an integrated general-purpose, fully 8051-compatible
Microcontroller with television specific hardware features. Microcontroller has been enhanced to provide
powerful features such as memory banking, data pointers, and additional interrupts etc. The on-chip
display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen
displays. Internal XRAM consists of up to16 Kbytes. Device has an internal ROM of up to 128 KBytes.
ROMless versions can access up to 1 MByte of external RAM and ROM. The SDA 55XX supports a
wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX
and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5
TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented
characters (DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does
most of the internal TTX acquisition processing, transfers data to/from external memory interface and
receives/ transmits data via I2C-firmware user-interface. The slicer combined with dedicated hardware
stores TTX data in a VBI buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition
tasks (hamming and parity-checks, page search and evaluation of header control bits) once per field.
Additionally, the firmware can provide high-end Teletext features like Packet-26-handling, FLOF, TOP
and list-pages. The interface to user software is optimized for minimal overhead. SDA 55XX is realized
in 0.25 micron technology with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and
hardware development environment (TEAM) is available to simplify and speed up the development of
the software and On Screen Display. TEAM stands for TVT Expert Application Maker. It improves the
TV controller software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.
11.22. Sil 9993

The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High
Definition Multimedia Interface) specification. DTVs, plasma displays, LCD TVs and projectors can now
provide the purest level of protected digital audio/video over a simple, low cost cable. Backwards
compatibility with DVI 1.0 allows HDMI systems to connect to any DVI 1.0 host (DVD players, HD set
top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a flexible audio and video
interface. The receiver can connect to RGB input and output YCbCr using an integrated color space
converter. This allows full backward compatibility to DVI, and interfaces to all major video processors.
A S/PDIF port can output PCM encoded data as well as Dolby Digital, DTS and all other formats
capable of being sent over S/PDIF. A 2-channel I2S port outputs data converted from S/PDIF. The SiI
9993 comes pre-programmed with HDCP keys, greatly simplifying the manufacturing process, lowering
costs, all the while providing the highest level of HDCP key security. Silicon Image’s PanelLink
23
receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores pass
all HDMI compliancy tests.
11.22.2. Features
• HDMI 1.0 and DVI 1.0 compliant receiver
• Integrated PanelLink core supports DTV resolutions (480i/576i/480p/576p/720p/1080i)
• Digital video interface supports video processors:
o 24-bit RGB 4:4:4
o 24-bit YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 embedded syncs
• Analog RGB and YPbPr output:
o 10-bit DAC
o Separate or Composite Syncs (Sync on G)
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC
60958 and IEC 61937.
• Programmable I2S interface for connection to low-cost audio DACs.
• Integrated HDCP decryption engine for receiving protected audio and video content
• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
• Programmable registers via slave I2C interface
• 3.3V operation in 100-pin TQFP package
• Flexible power management
11.23. NCP1014

The NCP101X series integrates a fixedífrequency currentímodecontroller and a 700 V MOSFET.
Housed in a PDIPí7 or SOTí223package, the NCP101X offers everything needed to build a rugged
and lowícost power supply, including softístart, frequency jittering, shortícircuit protection, skipícycle,
a maximum peak current setpoint and a Dynamic SelfíSupply (no need for an auxiliary winding). Unlike
other monolithic solutions, the NCP101X is quiet by nature: during nominal load operation, the part
switches at one of the available frequencies (65í100í130 kHz). When the current setpoint falls below a
given value, e.g. the output power demand diminishes, the IC automatically enters the soícalled skip
cycle mode and provides excellent efficiency at light loads. Because this occurs at typically 1/4 of the
maximum peak value, no acoustic noise takes place. As a result, standby power is reduced to the
minimum without acoustic noise generation. Shortícircuit detection takes place when the feedback
signal fades away, e.g. in true shortícircuit conditions or in broken Optocoupler cases. External
disabling is easily done either simply by pulling the feedback pin down or latching it to ground through
an inexpensive SCR for complete latchedíoff. Finally softístart and frequency jittering further ease the
designer task to quickly develop lowícost and robust offline power supplies. For improved standby
performance, the connection of an auxiliary winding stops the DSS operation and helps to consume
less than100 mW at high line. In this mode, a builtíin latched overvoltage protection prevents from
lethal voltage runaways in case the Optocoupler would brake.
11.23.2. Features
• Builtíin 700 V MOSFET with Typical RDSon of 11 and 22
• Large Creepage Distance Between HighíVoltage Pins
• CurrentíMode Fixed Frequency Operation: 65 kHz–100 kHzí130 kHz
• SkipíCycle Operation at Low Peak Currents Only: No Acoustic Noise!
• Dynamic SelfíSupply, No Need for an Auxiliary Winding
• Internal 1.0 ms SoftíStart
• Latched Overvoltage Protection with Auxiliary Winding Operation
• Frequency Jittering for Better EMI Signature
• AutoíRecovery Internal Output ShortíCircuit Protection
• Below 100 mW Standby Power if Auxiliary Winding is Used
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient Analysis
24
11.23.3. Pin Connections and Descriptions
11.24. SN74CB3Q3305

The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate
voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-
state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data
input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive
loading and signal distortion on the data bus. Specifically designed to support high-bandwidth
applications, the SN74CB3Q3305 provides an optimized interface solution ideally suited for broadband
communications, networking, and data-intensive computing systems.
11.24.2. Features
• High-Bandwidth Data Path (Up To 500 MHz)
• 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
• Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Typical)
• Rail-to-Rail Switching on Data I/O Ports
í 0- to 5-V Switching With 3.3-V VCC
í 0- to 3.3-V Switching With 2.5-V VCC
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
• Fast Switching Frequency (fOE = 20 MHz Max)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (ICC = 0.25 mA Typical)
• VCC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
í 2000-V Human-Body Model (A114-B, Class II)
25
í 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus
Isolation, Low-Distortion Signal Gating
11.25. ST24LC21
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.
This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered,
the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal
applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal
applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power supply value as
low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
11.25.2. Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances
DIP Pin connections CO Pin connections
NC: Not connected
Signal names
SDA Serial data Address Input/Output

SCL Serial Clock (I2C mode)
Vcc Supply voltage
Vss Ground
VCLK Clock transmit only mode
26
11.26. LM2576

The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and
convenient design of a step–down switching regulator (buck converter). All circuits of this series are
capable of driving a 3.0 A load with excellent line and load regulation.
These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable
output version. These regulators were designed to minimize the number of external components to
simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are
offered by several different inductor manufacturers.
Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in
comparison with popular three–terminal linear regulators, especially with higher input voltages. In many
cases, the power dissipated is so low that no heatsink is required or its size could be reduced
dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different
manufacturers. This feature greatly simplifies the design of switch–mode power supplies.
The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input
voltages and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C).
External shutdown is included, featuring 80 mA (typical) standby current. The output switch includes
cycle–by–cycle current limiting, as well as thermal shutdown for full protection under fault conditions.
11.26.2. Features
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load
Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1
11.26.3. Pin description
11.27. TDA1308

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for
portable digital audio applications.
11.27.2. Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
27
• Short-circuit resistant
• High performance
• high signal-to-noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.
11.27.3. Pinning
SYMBOL PIN DESCRIPTION PIN VALUE

OUTA 1 Output A (Voltage swing) Min : 0.75V, Max : 4.25V
INA(neg) 2 Inverting input A Vo(clip) : Min : 1400mVrms
INA(pos) 3 Non-inverting input A 2.5V
VSS 4 Negative supply 0V
INB(pos) 5 Non-inverting input B 2.5V
INB(neg) 6 Inverting input B Vo(clip) : Min : 1400mVrms
OUTB 7 Output B (Voltage swing) Min : 0.75V, Max : 4.25V
VDD 8 Positive supply 5V, Min : 3.0V, Max : 7.0V
11.28. TDA9886

The TDA9886 is an alignment-free single standard (without positive modulation) vision and sound IF
signal PLL.
11.28.2. Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear
demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all
negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating
as crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for
negative modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analogue
converter; AFC bits via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high
performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).
11.28.3. Pinning
SYMBOL PIN DESCRIPTION

VIF1 1 VIF differential input 1
VIF2 2 VIF differential input 2
OP1 3 output 1 (open-collector)
FMPLL 4 FM-PLL for loop filter
28
DEEM 5 de-emphasis output for capacitor
AFD 6 AF decoupling input for capacitor
DGND 7 digital ground
AUD 8 audio output
TOP 9 tuner AGC TakeOver Point (TOP)
SDA 10 I2C-bus data input/output
SCL 11 I2C-bus clock input
SIOMA 12 sound intercarrier output and MAD select
n.c. 13 not connected
TAGC 14 tuner AGC output
REF 15 4 MHz crystal or reference input
VAGC 16 VIF-AGC for capacitor; note 1
CVBS 17 video output
AGND 18 analog ground
VPLL 19 VIF-PLL for loop filter
VP 20 supply voltage (+5 V)
AFC 21 AFC output
OP2 22 output 2 (open-collector)
SIF1 23 SIF differential input 1
SIF2 24 SIF differential input 2
11.29. TPA3002D2
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied
stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 O. The high efficiency of the
TPA3002D2 eliminates the need for external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal
offering a range of gain from -40 dB to 36 dB. Line outputs, for driving external headphone amplifier
inputs, are also dc voltage controlled with a range of gain from -56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
11.29.2. Features
x 9-W/Ch into an 8-Q Load from 12-V Supply
x Efficient, Class-D Operation Eliminates
Heatsinks and Reduces Power Supply
Requirements
x 32-Step DC Volume Control From -40 dB to
36 dB
x Line Outputs for External Headphone
Amplifier with Volume Control
x Regulated 5-V Supply Output for Powering
TPA6110A2
x Space-Saving, Thermally-Enhanced
PowerPAD™ Packaging
x Thermal and Short-Circuit Protection
Applications
x LCD Monitors and TVs
x Powered Speakers
29
11.29.3. Pinning
Terminal Functions
TERMINAL I/O DESCRIPTION

NO. NAME
AGND 26, 30 - Analog ground for digital/analog cells in core
AVCC 33 - High-voltage analog power supply (8.5 V to 14 V)
AVDD 29 O 5-V Regulated output capable of 100-mA output
AVDDREF 7 O 5-V Reference output—provided for connection to adjacent VREF terminal.
BSLN 13 I/O Bootstrap I/O for left channel, negative high-side FET
BSLP 24 I/O Bootstrap I/O for left channel, positive high-side FET
BSRN 48 I/O Bootstrap I/O for right channel, negative high-side FET
BSRP 37 I/O Bootstrap I/O for right channel, positive high-side FET
COSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
LINN 6 I Negative differential audio input for left channel
LINP 5 I Positive differential audio input for left channel
LOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channel
LOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel
MODE 34 I Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D
outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs
are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as
line-level outputs for external amplifiers.
MODE_OUT 35 O Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT
pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is
intended for MUTE control of an external headphone amplifier. Leave unconnected when not used for
headphone amplifier control.
PGNDL 18, 19 - Power ground for left channel H-bridge
PGNDR 42, 43 - Power ground for right channel H-bridge
PVCCL 14, 15 - Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC.
PVCCL 22, 23 - Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC.
PVCCR 38,39 - Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC.
PVCCR 46, 47 - Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC.
REFGND 12 — Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
ground to this terminal.
30
RINP 3 I Positive differential audio input for right channel
RINN 2 I Negative differential audio input for right channel
ROSC 27 I/O Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channel
ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel
SD 1 I Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
VARDIFF 9 I DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or
AVDDREF if VAROUT outputs are unconnected.
VARMAX 10 I DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF if
VAROUT outputs are unconnected.
VAROUTL 31 O Variable output for left channel audio. Line level output for driving external HP amplifier.
VAROUTR 32 O Variable output for right channel audio. Line level output for driving external HP amplifier.
VCLAMPL 25 - Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR 36 - Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME 11 I DC voltage that sets the gain of the Class-D and VAROUT outputs.
VREF 8 I Analog reference for gain control section.
V2P5 4 O 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.
— Thermal - Connect to AGND and PGND—should be center point for both grounds.
Pad
11.30. µPA672T

The μPA672T is a super-mini-mold device provided with two MOS FET elements. It achieves high-
density mounting and saves mounting costs.
11.30.2. Features
• Two MOS FET circuits in package the same size as SC-70
• Automatic mounting supported
11.30.3. Pin Connection
11.31. VPC3230D

The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-
Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such
as DDP 331x) and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
• multi-standard colour decoder PAL/NTSC/SECAM including all substandards
• four CVBS, one S-VHS input, one CVBS output
• two RGB/YCr Cb component inputs, one Fast Blank (FB) input
• integrated high-quality A/D converters and associated clamp and AGC circuits
31
• multi-standard sync processing
• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’
• PAL+ preprocessing
• line-locked clock, data and sync, or 656-output interface
• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS
• high-quality soft mixer controlled by Fast Blank
• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution
• 15 predefined PIP display configurations and expert mode (fully programmable)
• control interface for external field memory
• I2C-bus interface
• one 20.25-MHz crystal, few external components
• 80-pin PQFP package
11.31.2. Pin Connections and Short Descriptions

NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V
Pin No. Pin Name Type Connection Short Description

PQFP (if not used)
80-pin
1 B1/CB1IN IN VREF Blue1/Cb1 Analog Component Input
2 G1/Y1IN IN VREF Green1/Y1 Analog Component Input
3 R1/CR1IN IN VREF Read1/Cr1 Analog Component Input
4 B2/CB2IN IN VREF Blue2/Cb2 Analog Component Input
5 G2/Y2IN IN VREF Green2/Y2 Analog Component Input
6 R2/CR2IN IN VREF Read2/Cr2 Analog Component Input
7 ASGF X Analog Shield GNDF
8 FFRSTWIN IN LV or GNDD FIFO Reset Write Input
9 VSUPCAP OUT X Digital Decoupling Circuitry Supply Voltage
10 VSUPD SUPPLYD X Supply Voltage, Digital Circuitry
11 GNDD SUPPLYD X Ground, Digital Circuitry
12 GNDCAP OUT X Digital Decoupling Circuitry GND
13 SCL IN/OUT X I2C Bus Clock
14 SDA IN/OUT X I2C Bus Data
15 RESQ IN X Reset Input, Active Low
16 TEST IN GNDD Test Pin, connect to GNDD
17 VGAV IN GNDD VGAV Input
18 YCOEQ IN GNDD Y/C Output Enable Input, Active Low
19 FFIE OUT LV FIFO Input Enable
20 FFWE OUT LV FIFO Write Enable
21 FFRSTW OUT LV FIFO Reset Write/Read
22 FFRE OUT LV FIFO Read Enable
23 FFOE OUT LV FIFO Output Enable
24 CLK20 IN/OUT LV Main Clock output 20.25 MHz
25 GNDPA OUT X Pad Decoupling Circuitry GND
26 VSUPPA OUT X Pad Decoupling Circuitry Supply Voltage
27 LLC2 OUT LV Double Clock Output
28 LLC1 IN/OUT LV Clock Output
29 VSUPLLC SUPPLYD X Supply Voltage, LLC Circuitry
30 GNDLLC SUPPLYD X Ground, LLC Circuitry
31 Y7 OUT GNDY Picture Bus Luma (MSB)
32 Y6 OUT GNDY Picture Bus Luma
35 GNDY SUPPLYD X Ground, Luma Output Circuitry
36 VSUPY SUPPLYD X Supply Voltage, Luma Output Circuitry
40 Y0 OUT GNDY Picture Bus Luma (LSB)
41 C7 OUT GNDC Picture Bus Chroma (MSB)
32
42 C6 OUT GNDC Picture Bus Chroma
45 VSUPC SUPPLYD X Supply Voltage, Chroma Output Circuitry
46 GNDC SUPPLYD X Ground, Chroma Output Circuitry
50 C0 OUT GNDC Picture Bus Chroma (LSB)
51 GNDSY SUPPLYD X Ground Sync Pad Circuitry
52 VSUPSY SUPPLYD X Supply Voltage, Sync Pad Circuitry
53 INTLC OUT LV Interlace Output
54 AVO OUT LV Active Video Output
55 FSY/HC/HSYA OUT LV Front Sync/ Horizontal Clamp Pulse/Front-End
Horizontal Sync Output
56 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Pulse
57 VS OUT LV Vertical Sync Pulse
58 FPDAT/VSYA IN/OUT LV Front End/Back-End Data/Front-End Vertical Sync
Output
59 VSTBYY SUPPLYA X Standby Supply Voltage
60 CLK5 OUT LV CCU 5 MHz Clock Output
61 NC - LV or GNDD Not Connected
62 XTAL1 IN X Analog Crystal Input
63 XTAL2 OUT X Analog Crystal Output
64 ASGF X Analog Shield GNDF
65 GNDF SUPPLYA X Ground, Analog Front-End
66 VRT OUTPUT X Reference Voltage Top, Analog
67 I2CSEL IN X I2C Bus Address Select
68 ISGND SUPPLYA X Signal Ground for Analog Input, connect to GNDF
69 VSUPF SUPPLYA X Supply Voltage, Analog Front-End
70 VOUT OUT LV Analog Video Output
71 CIN IN LV Chroma/Analog Video 5 Input
72 VIN1 IN VRT Video 1 Analog Input
76 VSUPAI SUPPLYA X Supply Voltage, Analog Component Inputs Front-End
77 GNDAI SUPPLYA X Ground, Analog Component Inputs Front-End
78 VREF OUTPUT X Reference Voltage Top, Analog Component Inputs
Front-End
79 FB1IN IN VREF Fast Blank Input
80 AISGND SUPPLYA X Signal Ground for Analog Component Inputs, connect
to GNDAI
12. SERVICE MENU SETTINGS

To enter the service menu, first enter the MENU by pressing “MENU” button and then press the digits 4, 7, 2
and 5 respectively.
12.1. Picture Adjust

x Source => All possible sources given with the chasis as a list.
x Mode => Three items as a list; NATURAL, DYNAMIC, CINEMA
x Colour Temp => Three items as a list; COOL, NORMAL, WARM
x Contrast => Slider Bar. Changing value between 0 to 63.
x Brightness => Slider Bar. Changing value between 0 to 63.
33
x Sharpness => Slider Bar. Changing value between 0 to 31.
x Colour => Slider Bar. Changing value between 0 to 99.
x R => Slider Bar. Changing value between 0 to 31.
x G => Slider Bar. Changing value between 0 to 31.
x B => Slider Bar. Changing value between 0 to 31.
x Backlight => Slider Bar. Changing value between 0 to 255.
In this menu preset values for each Mode (Contrast, Brightness, Sharpness, Colour values for each
Mode-NATURAL, DYNAMIC, CINEMA) and for each Colour Temp. (R, G, B values for each Colour
Temp- COOL, NORMAL, WARM) are determined for each source.
12.2. SOUND1
x Menu Subwoofe => If ON, Subwoofer option is available in TV set, and the item is
visible in sound menu, else Subwoofer is not available.
x Subwoofer Level (dB) => This value is gain value of Subwoofer output in dB. -30...12
x Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40
x Menu Equalizer => If ON, visible in sound menu, else invisible.
x Menu Headphone => If ON, visible in sound menu, else invisible.
x Menu Effect => If ON, visible in sound menu, else invisible.
x Menu Wide Sound => If ON, visible in sound menu, else invisible.
x Menu Dynamic Bass => If ON, visible in sound menu, else invisible.
x Menu Virtual Dolby => If ON, visible in sound menu, else invisible.
x Carrier Mute => If ON, in the absence of an FM carrier the output is muted,
else not.
x Virtual Dolby Text => Active if VIRTUAL DOLBY is ON. According to the selection;
seen in sound menu as 3D PANORAMA or VIRTUAL DOLBY.
12.3. SOUND 2
x AVL => AVL is controlled from this menu by service user. ON/OFF
x Menu AVL => If ON, AVL item is visible in sound menu, and AVL can be controlled
from sound menu by normal user, else AVL is invisible to normal user.
x FM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale
value for the related standard. 0...127
x NICAM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale
x SCART PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale
value for scart outputs. 0...127
x SCART VOLUME AVL ON => If AVL ON, set value in this item is used as volume
value for scart1 and scart2. 0...127
x FM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale
x NICAM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale
x SCART PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale
value for scart outputs. 0...127
x SCART VOLUME AVL OFF => If AVL OFF, set value in this item is used as volume
value for scart1 and scart2. 0...127
12.4. Options
x Burn-In Mode => If ON, When TV is powered ON Green, Blue, Red is displayed in
sequence until Menu button is pressed.
x FIRST APS => If ON, “First APS” menu is displayed when the TV is switched on
with the factory default settings.
x APS Volume => After First APS function finishes, the volume of the TV is that
value.
x AGC (dB) => Tuner AGC value.
x Power-Up Mode => Mode defines the TV set power on state.
Stand-by : When TV is ON set is in stand-by mode
Normal : When TV is ON set is in normal mode
Last State: When TV is ON set is in Last State mode
34
x Factory Reset => OK to activate. When OK is pressed on this item, factory defaults
loaded.
x Enter Flash Mode => Before uploading SW this mode must be selected.
x Reset Eeprom => Initialize default settings
12.5. TV Norm
x BG => If ON, supported, else not supported
x DK => If ON, supported, else not supported.
x I => If ON, supported, else not supported.
x L => If ON, supported, else not supported.
x LP => If ON, supported, else not supported.
x M => If ON, supported, else not supported.
12.6. Features
x PIP/PAP => If ON, PIP/PAP available else not.
x Blue Background => If ON, Blue Background is visible in Feature Menu else not.
x Menu Transparency => If ON, Menu Transparency is visible in Feature Menu else not.
x Menu Timeout => If ON, Menu Timeout is visible in Feature Menu else not.
x Backlight => If ON, Backlight is visible in Feature Menu else not.
x Single Tuner => If TV set has one tuner Single Tuner must be ON.
If TV set has double tuner Single Tuner must be OFF.
x Dynamic WB => Dynamic White Balance
12.7. Teletext
x TOP TXT => If ON, Top Text feature is available else not.
x Fast TXT => If ON, Fast Text feature is available else not.
x Teletext Language => Teletext Language may be controlled from this menu by service
user.
x Menu Teletext Language => If ON, Teletext Language item is visible in Feature Menu, and
Teletext Language can be controlled from Feature Menu by normal user, else Teletext Language is
invisible to normal user.
12.8. Source
x TV
x SC1
x SC2
x SC2 SVHS
x SC3
x SC3 SVHS
x YPBPR
x FAV
x SVHS
x HDMI
x PC
This menu is related with the options of the chassis. These items may be ON or OFF. If ON, the source is available
in TV set, and the item is visible in source menu, else the source may be available but invisible to user.
12.9. Menu Languages 1 & 2

The language options for the Language item in Feature menu can be set ON or OFF from this menu.
35
13. BLOCK DIAGRAM
MAIN BOARD
AUDIO AMP BOARD
AUDIO MAIN_L, MAIN_R
DECODING
MSP3411G AUDIO
MICRONAS AMPLIFIER
D-CLASS
AUDIO / VIDEO / GRAPHICS IN / OUT
IDTV, SVHS,MMC(RGB), PC IN
SVP-EX59
LVDS OUT
VPC3230D 8-BIT YUV

VIDEO PROCESSOR
PIP PICTURE
MICRONAS SDA5550
MCU
MICRONAS
24-BIT RGB
HDMI DECODER
SIL9993
PSU
No. 0210 BLOCK DIAGRAM

36
14. SCHEMATIC DIAGRAMS
S1004
VCC5V_FILTERED
L1003
22u
8V_FILTERED
26R_100MHZ_1.5A
L2000
C1014
C2004
R1053
R1059
50V
Q2002
47u
470p
2k 4
R1013
15k
1N4148
BC848B
R1036
TU1000
IC204
100R 12 SIOMAD NC 13 50V
12k
CTF5543_HOR
TUN2_CVBS C1056 50V 22u
QSS_TUN2
R1004 R1029 SC1_AUDIO_L_OUT
100R
QSS_TUN1
AGC 1 11 SCL TAGC 14 C1053
33p
C1020
25V
Q2001 C2005
100R 22n
SCL BC848B
R1032
R1037
R1043
50V 22u
10k
47k
C1034 X1000
75R
10p BC848B
SDA
R1008 SC3_AUDIO_L_OUT
25V Q1006
100R
R2006
TU 2 10 SDA REF 15
33p
C1021
25V
C2006
FB_CONTROL
R1054
1k
22p 4MHz
R2009
VCCA_3V3
4k 7
VCC_5V
R1060
25V
1k
75R
C1036 C1128
R2004
56p
AS 3 9 TOP VAGC 16 R1042 AUDIO_L_OUT 100R
QSS_TUN2 C1123 Q2003
C1122
470n BC848B
C1120
56p
50V
VCC_5V
50V
63V 220R
R1061
C1057
560R
50V 22u
22n
50V
Q1003
8 AUD CVBS 17 R1025 SC1_AUDIO_R_OUT
SCL 4 BC848B R2005
C1007
47R C1130 Q2004
C1125
AUDIO_R_OUT 100R
33p
25V
BC848B C2007
R104
C1113 56p
4k7
50V 50V 22u
100n
18.432MHz
47u
56p
25V SC3_AUDIO_R_OUT
X1002
R1078
C1013
R2007
SDA 5 7 DGND AGND 18
33p
25V
1p8
N.C
100R L1018 C2008
C1042
1k
R2008
1p8
C2200
R2200
1n5
50V
VCC_5V
47R
1k
C1028
TDA9885T C1037 C1137
22u
C1144
R1038
1n5
16V 560p
C1152
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC 6 6 AFD VPLL 19
10u
100n R1070
C1002
C1011
C1045
100n
330R C1195
10u
10n
470n 100n
25V
50V
SCL 100R
50V
D_CTR_I/O_1
ANA_IN2+
ANA_IN1+
TESTEN
ANA_IN-
NC5
C_CTR_I/O_0
XTAL_IN
NC6
NC4
TP
AVSUP
STANDBYQ
ADR_SEL
AUD_CL_OUT
XTAL_OUT
63V 25V
C1084
C1029
50V
39p
100n
VS 7 VCC_5V 5 DEEM VP 20 VCC5V_FILTERED
R1022
C1048
22k
10n
10u
16V
R1071 C1166
50V 10u
C1024 R1128 SDA 100R
C1035 1
C1085
R1011 VCC_33V 12C_CL AVSS 48
4R7 33V_FILTERED
C1006
4 FMPLL AFC 21
39p
NC/ADC 8
10u
50V
5k6 2 12C_DA MONO_IN 47 N.C C1169

10n 100n VCC5V_FILTERED L1019
R1104
50V 25V
C1201
C1203
C1204
C1202
100n
100n
1k SC1_AUDIO_R_IN
R1031
100n
10u
C1025
50V
50V
50V
50V
33V_FILTERED I2S_CL 3 12S_CL VREFTOP 46 C1156
R1000
6k8
22k 1n
VST 9 2k2 3 OP1 OP2 22 R1028
390p I2S_WS 4 12S_WS SC1_IN_R 45
C1138
R1068
S1008 50V SAW_SW2 330n C1174 R1105 L1022
I2S_DA_OUT
1k
C1005 3 5 1k SC1_AUDIO_L_IN
12S_DA_OUT SC1_IN_L 44
1n
IF2 10 GND 2 VIF2 SIF1 23 Q1007 330n
2 IN2 OUT2 5 BC858B I2S_DA_IN1 C1177
L1002
1n 6 12S_DA_IN1 ASG1 43 C1157

R1069 R1106 L1020
1u
BZT55C3V6
50V
R1127 470R 1k AV_AUDIO_R_IN
7 1n
IC206
C1057 ADR_DA SC2_IN_R 42
1 IN1 OUT1 4 VCC_5V 4R7 VCC5V_FILTERED 330n
IF1 11 1 VIF1 SIF2 24 C1148 C1176
Z1000 8 ADR_WS IC208 SC2_IN_L 41
R1107
1k
L1023
AV_AUDIO_L_IN
1n SF_63962 1n
C1197
C1198
C1199
C1206
IC207
C1200
C1205
50V
MSP3452G
100n
100n
100n
100n
100n
50V
IC200 330n
50V
50V
50V
50V
9
10u
50V
ADR_CL ASG2 40 C1170
470R R1108 L1021
S1009 C1158
R1067 1N4148 1k AUDIO_R
IF1
10 DVSUP SC3_IN_R 39 1n S2011

270p 470p
C1080 C1171 AUDIO_R2
3 100u 50V 50V C1140 330n R1110 L1024
R1124 11 DVSS SC3_IN_L 38
GND C1081 C1086 1k AUDIO_L
CC5V_FILTERED 100R 2 IN2 OUT2 5 1n S2008
L1008 C1153 SC3_AUDIO_R_IN
C1192
C1194
330n
100n
V 12 12S_DA_IN2 ASG3 37
16V
16V
VCC_5V L1025
1u
S1003 C1164 R1111 S2007

R1125
R1126
22u
10k
1k IDTV/MMC/DVD_R_IN
1k
1 IN1 OUT1 4 13 NC1 SC4_IN_R 36 1n

C1079
50V VCC5V_FILTERED C1078 1n5 330n C1147 R1109 L1026 S2005
10n Z1003 10u 14
C1175
1k IDTV/MMC/DVD_L_IN
50V NC2 SC4_IN_L 35
IF1
K9356M 50V 1n
D1003
D1007
BA782
BA591
15 330n S2006
NC3 AGNDC 34
R1048
R1050
C1193 SC3_AUDIO_L_IN
L1032
15k
2k4
C1163
ESD 16 RESETQ AHVSS 33
RESETQ_MSP
SC2_OUT_R
SC1_OUT_R
SC2_OUT_L
SC1_OUT_L
S2013 C1145
DACM_SUB
C1055 C1149 S2010
C1087
DACM_R
DACM_C
DACM_S
AUDIO_L2
DACM_L
DACA_R
AHVSUP
DACA_L
CAPL_M
CAPL_A
QSS_TUN1 470p 100n
VREF2
VREF1
S1010
Q1015 R1123 3u3

C1052 1kV
BC848B 47k Q1005 22n
C1191
50V
100n
BC848B
16V
Q1016 10p
25V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
BC848B
R1049
4k7
R1121 R1122 HP_R
R1051
C1118
75R
SAW_SW2 10k 10k
1n
C1116
HP_L
1n
PL1002
R1052
PL1001 C1112
560R
1n 50V
1
L1001 1n VCC_8V 4R7 8V_FILTERED
50V
5 MUTE_AMP C1114 R1130 HEADPHONE
C1054
R1089
C1010
C1134
100R
R1093
C2202
22n
50V
100R
100u
47u
50V
4
50V
10u
100n
50V
R1010 10u C1154
C300
C295
16V
10u
1N4148
D1000 D1001
R1039
IC205
100R 12 SIOMAD NC 13
12k
3 50V
R1114 MAIN_R
CTF5543_HOR C1097
2k2
R2202
220R
50V
2 1n
R1005 R1030 50V C1182 C1185
SCL 100R 11 SCL TAGC 14 1n5 2n2 2n2
C1119
AGC 1
33p
25V
C1022
C1121
PL1003 1 50V
50V
TUN1_CVBS 50V
L1030
100R 50V
L1029
50V
1n
MAIN_L C1126
1n
R1034
R1040
C1133
1n
50V
50V
10k
47k
SUBW
SDA
1n
C1038 X1001 1 IDTV/MMC/DVD_L_IN C1106 C1150
R1009 1u
R1103
TU 2 100R 10 SDA REF 15 4k7
33p
C1023
16V
25V
R1095
R1098
R1044
100R
100R
2
75R
22p 4MHz 100u

C1165
VCC_5V
HP_R
25V
IDTV/MMC/DVD_R_IN 50V C1178 22u
C1039 3
C1167
1n
100u
S1000 C1117 50V C1151
AS 3 9 TOP VAGC 16 R1035 470p L1028
AUDIO_L_OUT
AUDIO_R_OUT
R1090
R1094
470n 63V 2k2
100R
100R
R1129 1n
L1027
4R7
C1136
BC848B C1196 22u
8 AUD CVBS 17 47R VCC5V_FILTERED 100u
SCL 4 Q1002 100n
C1008
C1180
C1183
R1026 C1172
IC209
33p
25V
100u
IC2000
1n
AGND 50V
SDA 5 7 DGND 18 R2017 C1162 8 VDD OUTA 1
47u
C1043
R1112
C1015
C1184
100R 100n
1n5
50V
1 GND SDA 28 C1179
47k
33p
25V
2n2
C1030
TDA9885T C1040 47p
SDA 220p
R2201
R1041 C2201
R1102
47R
R1101
C2009 C2025 8V_FILTERED
47k
NC 6 6 AFD VPLL 19 7 OUTB INA- 2
10k
R2018
C1181
C1047
R1092 R1096
C1173
150R 100R 22u
10n
220p
470n 220n 2 CAPACITANCE SCL 27
C1003
C1012
50V
100n
10u
1k 1k
TDA1308
50V
10u
63V 16V SCL

C1031 22u C2026 L1017
BC848B BC848B
50V
VCC5V_FILTERED 47p Q1009 Q1011
VS 7 VCC_5V 5 DEEM VP 20 C2010 8V_FILTERED 4k7 6 INB- INA+ 3
C1049
S2000
R1023
10u
16V
10n R1100
22k
3 VS ADDR 26
C1168
50V
100n
2n2
C1159
R1012 C1026 C1041
50V
50V
16V
1n
1u
50V
C1009
C2027
1n
NC/ADC 8 4 FMPLL AFC 21 C2011 C2012 C2028 5 INB+ VSS 4

10u
50V
VCC_5V R2010 R2019

5k6 10n 100n SC2_AUDIO_L_IN 1k 1k SC2_AUDIO_R_IN
4 L1 R1 25
50V 25V
33V_FILTERED 330n 330n IDTV/MMC/DVD_R_IN
R1024
C1027 S2002 S2009

6k8
R1001 10k
50V
50V
IDTV/MMC/DVD_L_IN C2029
1n
1n
C1124
C1132
VST 9 2k2 3 OP1 OP2 22 22k C2013 C2014 C2030 R1113
R2011 R2020
50V
S2001 S2003
22u
50V
22u
HP_L
R1027 SC3_AUDIO_L_IN
390p 1k 5 L2 R2 24 1k
50V
C1004 S1007 330n 330n SC3_AUDIO_R_IN
3 SAW_SW1 C2015 C2032
50V
50V
1n
1n
IF2 10 GND 2 VIF2 SIF1 23 C2016 C2031
2 IN2 OUT2 5 R2012 R2021
L1000
1n PC_AUDIO_L_IN 1k 1k PC_AUDIO_R_IN
6 L3 R3 23
1u
50V
330n 330n
C1056
S1006
16V
SC2_AUDIO_L_OUT
SC2_AUDIO_R_OUT
1 IN1 OUT1 4
R1097
1 VIF1 SIF2 24
100R
IF1 11
R1091
100R
1n Z1001 7 NC1 NC4 22
50V K3953M
IC201 3
STBY_3V3
GND
2 IN2 OUT2 5
TEA6420 C1001 C1000
8 NC2 NC3 21
IF
1n 1n
1 IN1 OUT1 4 C2033 50V 50V
1n
C2017
1n
C2018 C2034
Z1002 R2013 R2022
K9356M YPBPR_AUDIO_L_IN 1k 9 L4 R4 20 1k YPBPR_AUDIO_R_IN
SW01=H L’ 10k 10k SAW_SW1 330n 330n
SW01=L BG,DK,I,L R1120 R1119
C2036
1n
C2020 C2037
R2014 R2023
R100
R101
BC848B
C1189
4k7
4k7
AUDIO_L_LINE_OUT
100n
DAC_AOL 1k 10 L5 R5 19 1k DAC_AOR
C2019
AUDIO_R_LINE_OUT
16V
Q1014
S1005
1n
330n 330n
47k BC848B S107
L2001 C2022 MUTE_AMP
R1118 R2015
Q1013
AUDIO_L 100R
BZT55C5V1
11 L0UT1 ROUT4 18
BLM21B201S R102
Q100
1n
D1005
S2012 C2021 22u
C255
4k7 HEADPHONE
L1031
BC848B
50V
4n7
D1006
D1002
BA591
BA782
L2002 C2024
R2016
AUDIO_R 100R S108
12 ROUT1 LOUT4 17
BLM21B201S L216 MUTE_AMP
1n
C1187 C2023 22u PC_AUDIO_R_IN
R103
50V S2010 & R2208 are for mute option
4k7
JACK-AK16
IF
L2018 22u
R2203 Mute is active high
JK200
10n AUDIO_L2 100R
123
13 LOUT2 ROUT3 16
50V L219 PC_AUDIO_L_IN
R1117
R1116
C247
C1186
C254
10k
50V
C257
BZT55C5V1
1n
1k
C1188
16V
50V
100n
1u
16V
D1004
L2019 22u
R2204
50V
L218
AUDIO_R2 100R 14 ROUT2 LOUT3 15
BLM21B201S
VCC5V_FILTERED
C249
100R C251
50V
1n
4n7
R1115
No. 0210 MAIN BOARD - TUNER/IF/AUDIO CIRCUIT

37
VCCA_3V3
VCCA_3V3
VCCA_3V3
VIDEO SWITCH TEA6415C
SC3_AUDIO_R_OUT
SC3_AUDIO_L_OUT
SC3_AUDIO_R_IN
SC3_AUDIO_L_IN
39p VCC_8V 4R7 V8
SVHSfromSC2_C
C304 R229
LG_1/IRQPDP
5V
PANEL_VCC
SC3_V_OUT
VCCA_3V3
VCC_12V
SC3_V_IN
PIN8_SC3
C298
C294
100n
10u
16V
SDA_PANEL
75R
SCL_PANEL
V8
BZT55C10
R264
DISP_EN/PDWN
D2101
IC210
R250
R251
4k7
4k7
150p
C301
C270
BZT55C10
50V
50V
1n
IDTV/MMC/DVD_CVBS
S111
C274 C282 D221
S113
S112
Q200
SC1_V_IN 1 INPUT1 INPUT8 20 BC848B
N.C 330R
220n 220n R235
PL203
S648
L203 R249
PDP_GO/BL_ON_OFF
CVBS_SVP
C285
R203
16V 16V 75R
S109
39p
75R
50V
C284
R206 MAIN PICTURE
V8
2 DATA GND2 19 1k BZT55C10 SC2_AUDIO_R_OUT
SDA 100R TO SVP PANEL_VCC
47p
C303
25V
S638
S639
R239 D2003 4n7
10k
CPU_GO
S642
1
S643
L207 50V
VCC_12V
R220
S641
C260 D2004 BZT55C10 BZT55C10 SC2_AUDIO_R_IN
R226
2
Q203 N.C L209 R253
SC2_V_IN 3 INPUT2 OUTPUT6 18 100R BC848B
N.C 47p D2000 BZT55C10 D2105 D2104 330R SC2_AUDIO_L_OUT
C292
R204
R240
39p
220n
75R
50V
3
S640
R2024
25V
R2025
330R
330R
VxtoVPC 4n7 150p
16V C287 10k 75R BZT55C10
C264 C277
L2006
BZT55C10 50V C2045
BZT55C10
R207 R221 R227 1n
4
GOES TO VPC3230
D2002
BZT55C10
L211
L2005
SCL 100R 4 CLOCK OUTPUT5 17 100R 1k FOR PIP PICTURE 4n7
11
21
13
15
23
25
17
19
27
29
C2040
9
R241 C2044 1n D2103
10k
5
L212
R222 PL103 C2042 50V
C266
D223
L2003
D2001
10
12
20
30
14
16
18
22
24
26
28
C265 SC2_AUDIO_L_IN
C2039
S636
2
8
TUN1_CVBS
150p
C2038 1n
L2004
6
5 INPUT3 OUTPUT4 16 150p L2008 L214
R200
C259
39p
75R
50V
N.C 50V D203

220n 4n7
7
V8
16V L2007
TEA6415C
S646
S647
C279 PIN8_SC2
R230
8
D205
AV1_V_IN 6 INPUT4 OUTPUT3 15 100R
TXOUT3+
TXCLKOUT+
TXOUT2+
TXOUT1+
TXOUT0+
TXOUT3-
TXOUT2-
TXOUT1-
TXOUT0-
TXCLKOUT-
N.C SC2_B
C280
R205
D2100
39p
220n
75R
50V
9
Q202 23 25 27 29 31 33 35 37 39 41 75R R288 BZT55C5V1
16V 10k SELECTABLE VIDEO OUT
BC848B
R223 FOR SCART 2
S201 R237
10
7 PROG OUTPUT2 14 SC2_V_OUT 22 24 26 28 30 32 34 36 38 40 42 D207 TV_LINK
75R
N.C
PARITY
BZT55C10
V8
S200
11
D222
C258
VCC_8V R289 75R
4n7
50V
10k 1k L213
CONNECT C288 R224 R242
PL205 75R R290 SC2_G
R1033 Q1004
12
SVHS_Y_IN 8 INPUT5 OUTPUT1 13 100R BC848B R1046
LVDS OUTPUT
C297
39p
50V
2 4 6 8 10 12 14 16 18 20 D208
N.C
R201 220n 75R SC1_V_OUT
13
L204 S204 SC2_R
75R 16V 10k R1045 C2049
V8
R225 1k 1 3 5 7 9 11 13 15 17 19 21
100n
14
9 VCC S205 SVHSfromSC2_C
L206
VCC_8V GND1 12 C293
L200
50V
100u
220n
C283
C299
C273
R2001 150p 16V

16V
16V
22u
15
50V
Q2000 150p
100R BC848B C252
C275 75R SC2_FB
L208
16
BZT55C10
D212
C267
R275
150p
C250
C248
150p
75R
10 INPUT6
50V
INPUT7 11 TUN2_CVBS R2002
1n
D204
R286
75R
L210
330R
R252
75R
75R SC3_V_OUT
C276
220n
39p
N.C
17
R276
S221
R287
D218
D202
C291
D209
75R
R231
16V R2003
75R
1n
R260
1k SC2_V_OUT
L205
SC3_V_IN
C268
18
39p
50V
D2102
S220
R202 220n
D214
D206
D210
75R 16V C296
19
BZT55C10 BZT55C10 D211
R254
330R
R285
50V SC2_V_IN
75R
20
4n7 C286
S212
BZT55C10
MMC_CVBS IDTV/MMC/DVD_CVBS BZT55C10
D220
21
D213
N.C
C269 150p
D219
D2500 50V
R261 BZT55C10 150p
C253
150p
50V
75R
D224 C278
PIN8_SC1
SC1_V_IN
SC1_AUDIO_L_IN
SC1_AUDIO_R_IN
SC1_G
SC1_FB
SC1_B
SCSDA
SC1_V_OUT
SCSCL
SC1_R
SC1_AUDIO_L_OUT
SC1_AUDIO_R_OUT
C261
150p
50V
AV1_V_IN CHROMA SWITCH
V8
BZT55C5V1
D215
S635
1 N.C
SVHS_Y_IN
2 C263 R267
39p 10k
R266
3 D217
18k
220n
4 CIN BC848C MMC/DVD
R232 C262
C245
R270 Q204 Q205 I2C BUFFER FOR PANEL
5 D216 75R CIN 100R C246
BC848C VIDEO INPUTS
220n
6 16V 220n
1 MMC_CVBS DIMMING SELECTION
R268
16V
R273
L202
47k
10k
IC215
R274
7 AV_AUDIO_R_IN
2
1k
C271
1n
8 S213 S651
3 DVD_12V_SENSE
SVHSfromSC2_C S633 4k7 VCC_5V SDA2 1 NC1 VCC 8 VCC_5V
L201 C_SELECTED
PL201 R271
S645
AV_AUDIO_L_IN
4 MMC_B
2 NC2 VCLK 7 SCL2
C272
50V
1n
R269
S644
Q206 5 MMC_R
S652 ST24LC21
CHROMA_SW 47k BC848C VCCA_3V3 SDA_PANEL 3 NC3 SCL 6
C2050
100n
16V
6 MMC_G SCL_PANEL
4 VSS SDA 5
SEL
EXTERNAL INPUT S634
PL1
VCC_5V IC214
VCCA_3V3
STBY_3V3
1 Q1 VCC 16 STBY_5V
C2053
C2051
C2052
100n
100n
100n
R211
R212
2k
2k
PL200
C290 IC211 2 Q2 Q0 15
gnd 15 DDC_CLK_PC
100n
C281
R280
150k
R215
IC213 100n
14 22R 1 1A VCC 14 VCCA_3V3 1N4148
S650
S637
16V R279
VCC_5V
C289
100n
Q3 10k
VCCA_3V3
3 DSERIAL 14
16V
1 A0 VDD 16 STBY_3V3 13 D200
1N4148
STBY_3V3
DDC_5V
100n
C302
12 DDC_DATA_PC 2 1Y 6A 13
16V
BZT55C12
BZT55C12
SDA2 D201 VGA_VSIN Q4

4 OE 13
D2501
D2502
2 A1 SDA 15 330R 11
R255
R216
R217
R213
74HC595D
10k
10k
10 22R 3 2A 6Y 12
SCL2
S223
S649
VGA_HSIN
R277
R265
R246
R248
5 Q5 STOP 12
4k7
4k7
4k7
4k7
9 DDC_5V IC212
3 A2 SCL 14 330R 74LVC14A
R256
8 4 2Y 5A 11
8 VCC NC1 1 Q6
6 SHCP 11
7 PGAGND
VCCA_3V3
CHROMA_SW 4 P0 INT 13
R257
4k7
VGA_VSIN 7 VCLK NC2 2

R258
R259
4k7
4k7
6 5 3A 5Y 10
PCF8574 ST24LC21
R214 DDC_CLK_PC 100R 6 SCL NC3 3 7 Q7 MR 10
DISP_EN/PDWN P7 LG_1/IRQPDP 5 VGA_HSIN 22R 22R VGA_VSIN R218
R283
5 P1 12
R281
10k
10k
R238 DDC_DATA_PC 100R 5 SDA VSS 4
4 6 3Y 4A 9 R219
8 GND Q7OUT 9
RGB_SW2 P6 RGB_SW3 3 75R PC_STBY
R282
6 P2 11
10k
R208
2 75R 7 GND 4Y 8
R209 Q207
BC848C
RGB_SW1 7 P3 P5 10 SW_ENABLE 1 75R PGAGND
R210
Q208
BC848C
R284
47k
gnd 8 VSS 4 9 PANEL_VCC_ON/OFF
VGA_GIN
VGA_RIN
VGA_BIN
PORT EXPANDER PC STAND-BY

D-SUB 15 PC INPUT & DDC CIRDUIT
No. 0210 MAIN BOARD - I/O CIRCUIT

38
VCC_5V
I2S_DA_OUT
I2S_DA_IN1
DHS_2EX
DVS_2EX
S303
VCCD2_3V3
VCCD2_3V3 VCCD_3V3
BLM21B201S
I2S_WS
I2S_CL
L2009
IC316
VCCD2_3V3
RESETQ_MSP
100n
C331
C333
R2030 C362
10u
2n2
50V
25V
RGB_SW3 1k 1 A R 16 VCC_5V
VCC_5V
SDA
YPBPR_AUDIO_L_IN
YPBPR_AUDIO_R_IN
SCL
S302
L2010
BLM21B201S
C2046
AUDIO_R_LINE_OUT
AUDIO_L_LINE_OUT
STBY_5V R2032 SC1_R 2 B O 15
8
5
BLM21B201S
R2028
33R
L313
10R
R1
R2
R3
R4
L308 R2031 SC2_R 3 C N 14 SC1_FB
10u
50V VCC_5V 16V 33R
1
4 BLM21B201S 220n
R2026
R2027
RGB_R_VPC 4 D M 13 SC2_FB
100R
100R
C330
C332
3p3
3p3
50V
50V
C2047 C2048
PI5V330_SOIC
R316
R317
BLM21B201S
22R
22R
BLM21B201S
25V SC1_G 5 E L 12 FB_VPC
C318
47n
L311
L314
10n 100n
50V 25V 50V 20.25MHz SC2_G 6 F K SC1_B
11
1n5
C340
44
43
42
41
40
39
38
37
36
35
34
RGB_G_VPC 7 G J 10 SC2_B
X300
C319 50V
1n5
I2S_DEL_OUT1
I2S_DEL_IN1
DVSUP1
DVSS1
I2S_DEL_WS
RESETQ 8
SDA
SCL
ADR_SEL
I2S_DEL_CL
TEST
50V H I 9 RGB_B_VPC
S331
S330
S323
S324
50V 68n
R315
10k
390p
C341
C343
C320
1 NC1 NC25 33
C317 RGB SWITCHING FOR VPC
61
51
41
63
55
53
45
43
62
60
59
58
57
52
50
49
47
42
48
56
46
64
54
44
BLM21A601S
BLM21A601S
BZT55C10
BZT55C10
2 NC2 NC24 32
D225
D226
C1
XTAL1
C3
CLK5
C5
ASGF2
NC2
C0
C2
AVO
C7
VS
MSY/HS
C6
XTAL2
C4
L316
L317
FSY/HC
GNDC
VSUPC
INTLC
VSTBY
VSUPSY
GNDSY
FPDAT
10u
3 NC3 NC23 31 50V
25V
47n
4 NC4 NC22 30 R322
33R
C359
C360
470p
470p
SVHSfromSC2_C
DIN[0]
50V
50V
65 18 R1
5 NC5 NC21 29 C323 GNDF Y0 40
IC2001
DIN[0-23]
DIN[1]
66 2 R2 7
6 NC6 NC20 28 VRT Y1 39
MAD4868A
VxtoVPC
2 3 1 2 3 1 3 DIN[2]
67 R3 6
7 NC7 NC19 27 I2CSEL Y2 38
CIN
DIN[3]
68 4 R4 5
8 NC8 NC18 26 ISGND Y3 37
A A BACK RIGHT
BACK LEFT L2011
NC17 JK303 JK304 69 VSUPY C344 VCCD2_3V3
9 NC9 25 VSUPF 36
BLM21B201S
L AUDIO FAV R AUDIO FAV
SVP ENTEGRESINE
10 NC10 NC16 24 70 VOUT GNDY 35 100n R323
C321 16V 33R
DIN[4]
I2S_DEL_OUT2
I2S_DEL_OUT3
I2S_DEL_OUT4
1 R1 8
11 NC11 NC15 23 75R 71 CIN Y4 34
I2S_DEL_IN2
I2S_DEL_IN3
I2S_DEL_IN4
R304 C361 1n
2 7 DIN[5]
75R 72 VINI Y5 33 R2
IC216
DVSUP2
C322
DVSS2
R305
1n 3 DIN[6]
NC12
NC13
NC14
R3 6
75R 73 VIN2 Y6 32
R306
VPC323XD
680n 4 5 DIN[7]
75R 74 VIN3 Y7 31 R4
12
13
14
15
16
17
18
19
20
21
22
R307
100n
C346
75R 75 VIN4 GNDLLC 30
16V
L300 R300
VCC_5V 76 VSUPAI VSUPLLC 29 L315
100u
220n
390p
C350
C348
C349
C305
VCCD2_3V3
1n8
16V
16V
50V
VCC_5V
BLM21B201S
77 GNDAI LLC1 28
R321
C306
C316
47n
10u
25V
50V
N.C 78 22R CLK_2EX
VREF LLC2 27
PL301
R2029
79 FB1IN VSUPPA 26
10k
AUDIO_R_LINE_OUT
C345
C347
1
1n5
47n
50V
25V
S325
R312
80 AISGND GNDPA 25
4k
2 FB_VPC
R1/CR1IN
R2/CR2IN
B1/CB1IN
B2/CB2IN
VSUPCAP
S316
G1/Y1IN
G2/Y2IN
GNDCAP
FFRSTW
YCOEQ
VSUPD
ASGF1
CLK20
AUDIO_L_LINE_OUT
GNDD
3 C363
RESQ
VGAV
FFWE
FFOE
TEST
FFRE
220n
FFIE
SDA
S326
NC1
SCL
4 SUBW RCA_Y
220n C364
220p
C356
11
21
13
10
15
23
12
17
19
20
22
18
16
14
24
RCA_PB
5
2
9
8
6
4
JK300
50V
R331
75R
50V
123
WHITE_FAV RCA_PR 330p N.C 16V

A
S301
Y C311 220n
C365
30032233 220n RGB_B_VPC
SCART RGB
R313
100R
R318
100R
R319
100R
R320
JK301 C327
1k
123
WHITE_FAV
220p
C357
R332
50V 50V
50V
50V
A
75R
Pb N.C 270p 390p C342

330p 16V
C312 220n
VCC_5V
30032234
RGB_G_VPC
JK302 C334 C337 220n
Pr 16V
C328
123
1P_RED_FAV 25V N.C

220p
C358
A
50V
560p 50V
1n5
IC317
C352
100n
50V
16V
330p N.C 16V C335 R325
C313 220n
R333
RGB_SW1 1k 1 A R 16 VCC_5V
75R
C338
SDA3
RGB_R_VPC 16V
SCL3
RX1_RST#
D102 D104 D106 100n
BAV99 BAV99 BAV99 C329 16V SC1_R 2 B O 15
220n
330p
C308
C336 SC2_R 3 C N 14 SC1_FB

50V
N.C
BLM21B201S
C339
S340
C324 SC2_FB
R309 4 D M 13
MMC_B 75R S310
L312
PI5V330_SOIC
SC1_G
MMC RGB INPUTS
220n 5 E L 12
16V
330p
C309
IC318 SC2_G 6 F K 11 SC1_B

50V
N.C
100n
C353 C325
R326 R310 7 G J 10 SC2_B
MMC_G
VCCD2_3V3
RGB_SW2 1k 1 A R 16 VCC_5V 75R S311
220n 8 H I 9
RCA_PR 2 B O 15 16V RGB_GIN S312
S309
330p
C310
VGA_RIN 3 C N 14
50V
N.C
S314 C326
RIN2 4 D M 13 R311
MMC_R 75R
PI5V330_SOIC RGB_RIN
RCA_Y 5 E L 12 220n
16V
S308
VGA_GIN 6 F K 11 RCA_PB
GIN2
S307
7 G J 10 VGA_BIN RGB_BIN
S336
S337
8 H I 9
FB
BIN2
RGB SWITCHING FOR SVP

VGA & YPbPr SWITCHING
No. 0210 MAIN BOARD - VPC3230 CIRCUIT

39
CLK_2EX
ODD_PINK
DHS_2EX
100n
100n
C434
C435
VDDMQ_2V5
VDDMQ_2V5
R435
PAVDD1 22R VL1_8
VD1_8
VD1_8
R2210 IC107
CAS#
RAS#
CS0#
WE#
C2206
C2203
C2204
C2205
100n
100n
100n
100n
100n
C440
C444
10k
10u
16V
16V
16V
16V
16V
16V
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
74LX1G86STR
STBY_3V3
R431
22R
C438
MLF1 R2214
R430
22R
CLKE
1 8
R1
R429
BA1
BA0
2n7
22R
GND
VCC
S110
50V
1A
1B
1Y
2 7
VD1_8
R436 R2
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
PAVDD2 22R 3 6
C2207
C2208
C2209
C2210
C2211
5
100n
100n
100n
100n
100n
C443
R432 R3
10u
16V
16V
16V
16V
16V
16V
VD1_8
10k ODD_PINK
C425 C428 4 5 C470 C471
R433 R4 R434 DVS_2EX
PLF2 10k 16V R2216 1k
2n7 100n 100n 100n 33R 100n 100n
5
8
C424
R2213
50V 16V 16V 16V
R1
R2
R3
R4
C439 C418
10
11
12
1
9
PL104 S437
VDDMQ_2V5
VCCA_3V3
MCLK0#
100n
MCLK0
16V
26R_100MHZ_1.5A
DIGITAL IDTV INPUTS [ITU 601]
DQM[3]
DQM[2]
MD[31]
MD[30]
MD[29]
MD[28]
MD[27]
MD[26]
MD[25]
MD[24]
MD[23]
MD[22]
MD[21]
MD[20]
MD[19]
MD[18]
MD[17]
MD[16]
DQS[3]
DQS[2]
MVREF
MPUGPIO4
L407 MD[0]
PDVDD VL1_8 MD[1]
R2215
33R
MD[2]
C437
C2216
C2217
C2218
C2219
100n
100n
100n
100n
100n
C455
C459
MD[3]
10u
16V
16V
16V
16V
16V
16V
MD[4]
100n MD[5]
S413 16V MD[6]
MCA[14]
MCA[15] MD[7]
MD[8]
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
R236 S411
MD[9]
100R
MCAD[0] MD[10]
1 8
MPUGPIO1
MD31
MD21
VDDM11
VSSM11
BA1
CS1
MPUGPIO3
DQM3
DQS3
MD23
VDDM13
VDDM15
MPUGPIO2
VDDC10
MD29
VSSM15
MD25
VSSM13
VSSC10
VSSC9
MD30
MD27
VDDC9
MD22
MD20
DQM2
VDDM12
DQS2
MD19
BA0
VDDM10
VDDM9
MD28
VSSM12
MD17
VDDC7
MCK0
MD18
VDDC8
VSSC7
VSSM10
VSSM9
VDDM16
MD26
VSSC8
MPUGPIO4
VSSM16
MD16
CLKE
WE
CAS
RAS
VDDM14
VSSH4
VDDH4
VSSM14
MD24
NC
MVREF
CS0_
MCK0_
VSSR
VDDR
R1 MD[11]
MCAD[1] MD[12]
2 R2 7
MD[13]
MD[0-31]
MCAD[2] 3 MD[14]
6
MCAD[0-7]
C403 R3 VDDMQ_2V5
193 128 MD[15]
GIN2 Y_G2 MPUGPIO0 VDDL VDDL
MCAD[3] MD[16]
MCA[0-19]
4 5 194 VSSL 127
100n R4 A_D0 MD[17]
195 126 MA[0]
MA0
R406
16V VD1_8 A_D1

75R
R234 196 125 MA[1] MD[18]

MA1
100n
C413
100R A_D2
16V
MCAD[4] 197 124 MD[19]
1 R1 8 VDDM8
A_D3 MD[20]
198 123 MA[2]
VDDC12 MA2
R233 MCAD[5] MA[3] MD[21]
100R 2 7 199 MA3 122
MCA[0] R2 VSSC12 MD[22]
1 8 200 VSSM8 121
R1 A_D4 MD[23]
MA[0-11]
MCAD[6] 3 6 201 120 MA[4]
C404 R3 MA4 C447
MCA[1] A_D5 MD[24]
BIN2 2 7 202 VDDM7 119
PB_B2 R2 A_D6 100n 16V MD[25]
MCAD[7] 4 5 203 118 MA[5]
MCA[2] R4 A_D7 MA5
100n 3 MA[6] MD[26]
6 204 MA6 117
C446
R407
16V R3 STBY_3V3 VDDH5

75R
205 116 MD[27]

MCA[3] VSSH5 VSSM7
206 115 MA[7] MD[28]
4 R4 5 MA7
ADDR0
207 114 100n 16V MA[8] MD[29]
ADDR1 MA8
R228 MD[30]
100R 208 VDDC6 113
ADDR2 VD1_8 MD[31]
MCA[4] 209 112 MA[9]
1 R1 8 MA9
ADDR3
DQM[0-3]
C405 210 111 MA[10]
ADDR4 MA10
MCA[5] 211 110
RIN2 PR_R2 2 R2 7 VSSC6
ADDR5 DQM[0]
212 109 MA[11]
ADDR6 MA11
100n MCA[6] 3 DQM[1]
6 213 MD15 108 MD[15]
R408
16V R3 R243 ADDR7

75R
214 107 DQM[2]

100R VD1_8 VDDC11 VDDC5 VD1_8
MCA[7] 215 106 DQM[3]
4 R4 5 RD_EMU 1 R1 8 100n MD14 MD[14] C448
VSSC11
216 105
PC & YPbPr INPUT 2 7 217
RD VSSM6
MD13 104 MD[13]
WR_EMU R2 C411 WR 100n DQS[0]
218 VDDM6 103
ALE 16V 16V DQS[1]
3 6 R244 219 102 100n
ALE_EMU R3 MPUCSON MD12 MD[12]
220 101 DQS[2]
INT# 100R INT VSSM5
221 100 DQS[3]
4 5 DQS[1]
DQS[0-3]
C401 MPUCSON R4 AVDD_ADC3 AVDD_ADC3 DQS1
C456
222 VDDM5 99 VDDMQ_2V5
S430 AVSS_ADC3 DIN[0]
C_SELECTED 223 VSSM4 98
C VREFN_3 VREFN_3 DIN[1]
VREFP_3
224
VREFP_3 IC224 DQM1 97 DQM[1]
225 96 DIN[2]
PR_R1 MD11 MD[11]
R401
100n PR_R1
75R
DIN[3]
MAIN PICTURE PR_R2 226
227
PR_R2 SVP_EX_51 VDDM4 95
94 DIN[4]
AVDD_ADC2 AVDD_ADC2 MD10 MD[10]
228 93 DIN[5]
C400 MD9 MD[9] C449
AVSS_ADC2 DIN[6]
229 VSSC5 92
CVBS_SVP CVBS2 VREFN_2 VREFN_2
230 91 DIN[7]
MD[8]
DIN[0-23]
VREFP_2 VREFP_2 MD8
100n 100n DIN[8]
C 231 MD7 90 MD[7]
R400
16V C 16V
75R
232 89 DIN[9]
S431 C402 PB_B1 VDDC4 VD1_8
PB_B1 DIN[10]
CVBS3 PB_B2 233 MD6 88 MD[6]
CVBS_SVP PB_B2 DIN[11]
234 VSSM3 87
100n AVDD3_AVSP2 AVDD3_AVSP2 DIN[12]
235 MD5 86 MD[5]
16V AVSS3_BG_ASS
R402
DIN[13]
75R
R427 236 85
75R CVBS_OUTP VDDM3
237 84 DIN[14]
CVBS_OUTN MD4 MD[4]
S441 238 83 DIN[15]
AVDD_ADC1 AVDD_ADC1 VSSM2
239 82 DIN[16]
AVSS_ADC1 DQS0 DQS[0]
240 81 DIN[17]
VREFN_1 VREFN_1 VDDM2
241 80 DIN[18]
VREFP_1 VREFP_1 VSSM1
S439 242 79 DIN[19]
CVBS1 DQM0 DQM[0]
243 78 DIN[20]
CVBS2 CVBS2 MD3 MD[3]
S438 244 77 DIN[21]
CVBS3 CVBS3 VDDM1 VDDMQ_2V5
245 76 DIN[22]
C406 MD2 MD[2]
100n
C451
S425 AIN_N1
16V
246 75 DIN[23]
RGB_GIN Y_G1 Y_G1 Y_G1 MD1 MD[1]
247 VSSC4 74
100n AIN_N2
248 MD0 73 MD[0]
16V Y_G2 Y_G2
R403
249 72
75R
AIN_N3 DIN20 DIN[20]

100n 250 71
DIN21
100n
C452
VSSC13 DIN[21]
251 DIN22 70
C409 VDDC13 DIN[22]
252 DIN23 69
VD1_8 PDVDD PDVDD DIN[23]
253 VSSC3 68
PDVSS
254 VDDC3 67
PAVDD PAVDD VD1_8
S426
RGB_RIN PR_R1 255 VSSH3 66
PAVSS
256 VDDH3 65
100n XTALI VDDH
R404
VREFP_1
VREFP_2
VREFP_3
VREFN_1
VREFN_2
VREFN_3
75R
16V C407
TESTMODE
LVDSVDDP
LVDSGND
LVDSVCC
PLL_GND
50V
PLL_VCC
PAVDD1
PAVDD2
AIN_HS
PAVSS1
PAVSS2
AIN_VS
FLD_IO
20p
VDDH1
VDDH2
VDDC1
VDDC2
VSSH1
VSSH2
VSSC1
VSSC2
TCLK+
RESET
XTALO
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
TCLK-
TD1+
TB1+
TC1+
TA1+
MLF1
V5SF
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
TD1-
PWM
TB1-
TC1-
PLF2
TA1-
14.31818MHz
GPO
SDA
SCL
CLK
DE
H
V
C414
X400
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
S427
RGB_BIN PB_B1 50V
R418
R419
20p
100n
R405
75R
16V C408
10k
100n
100n
100n
100n
100n
100n
C450
C457
C460
C462
C463
C467
C415
22R
22R
16V
16V
16V
16V
16V
16V
VDDH
DIN[19]
DIN[18]
DIN[17]
DIN[16]
DIN[15]
DIN[14]
DIN[13]
DIN[12]
DIN[11]
DIN[10]
DIN[9]
DIN[8]
DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
R422
MLF1
PAVDD1
PLF2
PAVDD2
MAIN RGB INPUT
TXOUT3+
TXOUT2+
TXOUT1+
TXOUT0+
TXCLKOUT+
RST_H
SCL_EX
SDA_EX
R2217
TXCLKOUT-
TXOUT3-
TXOUT2-
TXOUT1-
TXOUT0-
33R
VGA_HSIN
VGA_VSIN
VCCA_3V3
R2218 2u2
PARITY
4k7
R420
33R L404
VCCA_3V3
VCCA_3V3
AVDD_ADC3
DVS_2EX
DHS_2EX
26R_100MHZ_1.5A LVDS OUT VA1_8
L401 C436
C2234
C2231
C426
C2232
VDDL
C2233
100n
100n
C442
C445
100n
VD1_8
100n
100n
10u
16V
16V
16V
16V
16V
16V
PWM2
100n
C2404
C2401
C2402
C2403
C2212
C2213
C2214
C2215
C2400
C429
100n
100n
100n
100n
100n
100n
100n
100n
100n
C431
C433
16V
CLK_2EX
100n
C420
S440
10u
16V
S415
16V
16V
16V
10u
100n
16V
16V
16V
16V
16V
16V
16V
16V
100n
C422
16V
C427
VCCA_3V3
100n
DIGITAL SINC
R423
R425
16V
10k
10k
VDDH
100n
TXCLKOUT+
26R_100MHZ_1.5A
1N4148
D101
DE_2EX
FB_CONTROL
L406
SC2_FB_SVP
AVDD_ADC1
VD1_8
MPUCSON MPUGPIO4 VA1_8
VD1_8
STBY_3V3
TXCLKOUT-
R424
R426
10k
1k
C2239
C2242
C2241
C2240
100n
100n
100n
C454
C458
100n
100n
16V
10u
16V
16V
16V
16V
26R_100MHZ_1.5A
AVDD_ADC2 L409
VA1_8
R2211
R2212
10k
10k
C2230
C2229
C2228
100n
100n
100n
C465
C468
100n
16V
10u
16V
16V
16V
16V
C2227
100n
R428
16V
1k
TXCLKOUT+
TXCLKOUT-
R413
100n
C472
68R SDA3
R439
SDA_EX
STBY_5V
1k
VCCA_3V3
Q402
R414 BC848B
SCL_EX 68R SCL3 150R 600mA lik ferit R440 26R_100MHZ_1.5A
L400 1R SC2_FB_SVP 150R 600mA lik ferit L408
VCCA_3V3 PAVDD
C410
C412
VDDH L402 VL1_8

68p
68p
C473
AVDD3_AVSP2 VCCA_3V3
10p
S442 Q401
C2220
C2221
C2254
C2222
C2235
C2236
C2238
100n
100n
100n
100n
100n
100n
100n
100n
100n
FB
C421
C423
C466
C2237
10u
BC848B
16V
16V
16V
16V
16V
16V
100n
C2226
C469
C2224
C2225
100n
10u
100n
C430
C2223
C432
100n
100n
100n
16V
10u
16V
16V
16V
16V
16V
S445
No. 0210 MAIN BOARD - VIDEO DECODER CIRCUIT

40
VDDMQ_2V5_FLT
VDDMQ_2V5_FLT
MVREF
MD[28]
MD[29]
MD[30]
MD[31]
VCCA_2V5_FLT
VDDMQ_2V5_FLT
R500
10R
MD[27] 1 8 100n
R1
1
C505
VCCA_2V5_FLT
MD[26]
R1
R3
R2
R4
2 7 10R
R2 R508 C518
C501
R512
R510
100u
8
MD[25] 3
1u
1k
R3 6 1k 16V
C517
100n
50V
MD[24] 4 5 C502 4n7
R4
MD[0-31]
R501
DQM[2]
DQM[3]
DDQS2
DDQS3
10R 1u C525
MD[23] 1 R1 8 50V 50V
4n7
MD[22] 2 7 C516
R2
MD[21] 3 C524
R3 6 50V
107
108
144
106
100u
24
35
36
48
59
60
71
72
95
96
11
83
12
84
14
16
18
19
21
23
38
47
51
63
87
99
58
70
94
31
30
46
4n7 16V
MD[20] 4 5
R4 16V
100n
DQ26_C11
DQ15_E11
DQ13_F11
DQ11_H11
DQ9_J11
DM3_A11
DM1_G11
VDDQ_B11
VDDQ_D11
VDDQ_E3
VDDQ_F3
VDDQ_H3
VDDQ_J3
DQ27_B12
DQ25_C12
DQ24_D12
DQ14_E12
DQ12_F12
DQ10_H12
DQ8_J12
DQS3_A12
DQS1_G12
VREF_M12
VDDQ_B2
VDDQ_B9
VDDQ_D2
VDDQ_E10
VDDQ_F10
VDDQ_H10
VDDQ_J10
VDD_D10
VDDQ_B7
VDD_C7
VDDQ_B6
VDD_C6
VDDQ_B4
R502 C523
10R 50V
MD[19] 1 R1 8 4n7
C532
16V
MD[18] 2 7 100n
R2 C522
9 39
DQ28_A9 VDD_D3 50V
MD[17] 3 6 8 118 4n7
R3 DQ29_A8 VDD_K10 C531
20 115
DQ30_B8 VDD_K7 16V
MD[16] 4 5 7 114 100n
R4 DQ31_A7 VDD_K6 C521
22 111
NC_B10 VDD_K3 50V
82 92 4n7
NC_G10 VSS_H8 C530
120 91
R513 NC_K12 VSS_H7 16V
DQS[0-3]
DQS[0] 119 90 100n

15R DDQS0 NC_K11 VSS_H6 C506
MCLK01# 123 89
R514 NC_L3 VSS_H5 50V
DQS[1] 134 80 4n7
15R DDQS1 NC_M2 VSS_G8 C529
122 79
R515 NC_L2 VSS_G7 16V
DQS[2] 75 78 100n
15R DDQS2 NC_G3 VSS_G6 C507
15 77
R516 MCLK01 NC_B3 VSS_G5 25V
DQS[3] 116 68 10n
15R DDQS3 NC_K8 VSS_F8 C528
129 67
NC_L9 VSS_F7 16V
131 66 100n
CK-_L11 VSS_F6 C508
R503 130 65
R517 CK_L10 VSS_F5 25V
WE# 1 R1 8 CLKE 33R
143
CKE_M11 EM6A9320 VSS_E8
56 10n
C527
110 55
WE-_K2 VSS_E7 16V
CAS# 2 R2 7 109
CAS-_K1 IC1 VSS_E6
54
C509
100n
121 53
RAS-_L1 VSS_E5
3 6 133 45
RAS# R3 CS-_M1 VSS_D9 25V C515
BA0 R518 135 43 10n
33R BA0_M3 VSS_D7 16V
4 5 124 42 100n
CS0# R4 BA1_L4 VSS_D6
MA[11] 126 40
A11_L6 VSS_D4 C510
MA[10] 113 104
R519 A10_K5 VSS_J8 25V C504
BA1 MA[9] 127 103 10n
MA[0-11]
33R A9_L7 VSS_J7 16V

MA[8] 142 102 100n
A8/AP_M10 VSS_J6
MA[7] 141 101
R520
R521
A7_M9 VSS_J5
33R
33R
C511
MA[6] 140 117
A6_M8 VSS_K9 C503
MA[5] 128 112
A5_L8 VSS_K4 25V 16V
MA[4] 139 105 10n 100n
A4_M7 VSQ_J9
MA[3] 138 93
A3_M6 VSSQ_H9
MA[2] 125 100
A2_L5 VSSQ_J4 C512 C2253
MA[1] 137 88
A1_M5 VSSQ_H4 25V 16V
MA[0] 136 81 10n 100n
A0_M4 VSSQ_G9
DQM[0-3]
VSSQ_C10
VSSQ_A10
DQS2_G1
VSSQ_G4
VSSQ_D5
VSSQ_D8
DQ20_H2
DQ21_H1
DQS0_A1
VSSQ_C3
VSSQ_C4
VSSQ_C5
VSSQ_C8
VSSQ_C9
VSSQ_A3
DQ16_E2
DQ17_E1
VSSQ_E4
VSSQ_E9
DQ18_F2
DQ19_F1
VSSQ_F4
VSSQ_F9
DQ22_J1
DQ23_J2
DM2_G2
DQ7_D1
C513 C2252
DM0_A2
DQ5_C2
DQ6_C1
DQ0_A6
DQ1_B5
DQ2_A5
DQ4_B1
DQ3_A4
NC_L12
DQM[0] 25V
DQM[1] 10n 16V
DQM[2] 100n
DQM[3] C514
61
41
13
73
33
5
25
85
50
49
62
132
10
29
32
52
69
17
37
97
27
57
98
28
6
26
86
76
4
74
34
44
64
25V C2251
10n 16V
100n
C519
DQM[1]
DQM[0]
DDQS1
DDQS0
R2209 25V C2250

MCLK0 10R MCLK01 10n 16V
R2 7
R3 6
R4 5
R1 8
100n
R506
10R
R504
47R
C520
BLM21B201S
C526
BLM21B201S
1
R2 7
R3 6
R4 5
R1 8
C500
R507
L501
L500
10R
10n
1
R2 7
R3 6
R4 5
R2 7
R3 6
R4 5
R1 8
R1 8
R509
R511
R505
25V
10R
10R
47R
VDDMQ_2V5
VCCA_2V5
MD[15]
MD[14]
MD[13]
MD[12]
MD[11]
MD[10]
MD[7]1
MD[6]2
MD[5]3
MD[4]4
MD[3]1
MD[2]2
MD[1]3
MD[0]4
MD[9]
MD[8]
R2208
MCLK0# 10R MCLK01#
No. 0210 MAIN BOARD - DDR RAM CIRCUIT

41
PWM
1 44
PWM2
NC1 NC10
RD_EMU
WR_EMU
GAL_IAP
PSEN_UP
MCA[19]
MCA[18]
MCA[17]
2 NC2 NC9 43
S412
S414
S621
S620
R415
S622
1k2 VCCA_2V5
MCA[0] 3 A0 NC8 42
8
7
6
5
4
22R
R412
50V
10u
I6
I5
I4
I3
I2
MCA[1] 4 A1 A18 41 MCA[19]
C416
R416
4k7 VCC_5V MCA[2] 5A A2 A17 40 MCA[18]
9 7 I I1 3 MCA[16]
Q400
BC337
22R
R417
16V MCA[3] 6 A3 A16 39 MCA[17]
10 GND I0 2 MCA[15]
100u
11 OE CLK 1 MCA[14]
C417
IC622
MCA[4] 7 A4 A15 38 MCA[16]
12 Q0 VCC 20
C419
GAL16LV8
13 Q1 Q7 19
100n S623
16V MCA[15] 8 CS OE 37 SRAM_OE
No. 0210
MCAD[0] 9 I/O1 I/O8 36 MCAD[7]

FL_A14
FL_A15
Q2
Q3
Q4
Q5
Q6
14
15
16
17
18
CONTROL
BRIGHTNESS
MCAD[1] 10 I/O2 I/O7 35 MCAD[6]
BRT_CNTL
STBY_3V3
IR
STBY_3V3 11 VCC VSS1 34
FL_OE
16V
16V
FL_WE
FL_A16
FL_A17
C600
C601
100n
100n
IC217
SRAM_OE
SRAM_WE
12 VSS VCC1 33 STBY_3V3
4k7
R604
STBY_5V
R6018
LED1 BC848B
K6R4008V1C-I/C-P
22k 5
Q6006 MCAD[2] 13 I/O3 I/O6 32 MCAD[5]
R6019
BC848B 3
LED2 22k S6300 MCAD[3] 14 I/O4 I/O5 31 MCAD[4]
Q6007
2
1 S624
S6310 SRAM_WE 15 WE A14 30 MCA[14]
220R
R6015
MCA[5] 16 A5 A13 29 MCA[13]
PL600
220R
R6016
MCA[6] 17 A6 A12 28 MCA[12]
S6312 S6311
STBY_5V STBY_3V3
1 2 MCA[19] MCA[7] 18 A7 A11 27 MCA[11]
3 4 MCA[18]
PL607
5 6 MCA[17] MCA[8] 19 A8 A10 26 MCA[10]
S605 S6315
7 8 MCA[16]
MCA[0] 9 10 MCAD[0] MCA[9] 20 A9 NC7 25

SCSCL 100R SCL3
R6006
MCA[1] 11 12 MCAD[1]
4k7
MCA[2] 13 14 MCAD[2] 21 NC3 NC6 24
R600
Q600
10k
Q604
R6007
MCA[3] 15 16 MCAD[3]
STBY_5V R6005
MCA[4] 17 18 MCAD[4] 22 NC4 NC5 23
47k SW_ENABLE
MCA[5] 19 20 MCAD[5]
Q605
MCA[6] 21 22 MCAD[6]
10k
4k7
Q601
R601
R6010
FROM SCART2
MCA[7] 23 24 MCAD[7]
SCSDA 100R SDA3
R6011 25 26 MCA[8]
S606 S6316
CIRCUIT OF SW UPDATE
STBY_3V3 27 28 MCA[9]
MCA[0]
MCA[1]
MCA[2]
MCA[3]
MCA[4]
MCA[5]
MCA[6]
MCA[7]
MCAD[0]
29 30 MCA[10]
31 32 MCA[11]
33 34 MCA[12]
35 36 MCA[13]
37 38 MCA[14]
Q602
BSN20
39 40 MCA[15]
SCL 100R SCL3
R606 41 42 FL_OE
S6320
43 44 PSEN_UP
10k
R607
45 46 SRAM_OE
9
8
6
7
5
12
10
13
11
S6319
FL_A16
FL_A15
STBY_5V VCCA_3V3 47 48 RD_EMU

A0
A1
A2
A3
A4
A5
A6
A7
DQ0
49 50 SRAM_WE
S6318
10k
R610
51 52 WR_EMU
MCAD[1] 14 DQ1 A12 4

53 54 STBY_3V3 MCA[12]
LEVEL SHIFTER
SDA 100R SDA3 S6317
MCAD[2] 15 DQ2 A15 3
R611 55 56 RST#
16 VSS A16 2
BSN20
Q603
57 58 ALE_EMU
MCAD[3] 17 DQ3 A18 1
59 60 MCA[18]
IC219
CORRESPONDS TO
MCAD[4] 18 DQ4 VCC 32 STBY_3V3

& ST M29F040 Flash
M29W040B
MCAD[5] 19 DQ5 W 31
25V
100n
C605
Winbound W27E040 EPROM
MCAD[6] 20 DQ6 A17 30

S604
SDA2 5 SDA VSS 4

A14
E
A8
DQ7
A10
A9
G
A13
A11
E2
24
26
22
27
28
23
25
29
21
SCL2 6 SCL A2 3
FL_WE
SCL2
SDA2
FL_A17
24LC32A
NVM_WP 7 WP A1 2
42
FL_A14
FL_OE
S608
S607
S603 8 A0 1
VCC
STBY_3V3
S602
16V
VCCA_3V3
16V
100u
C603
C604
100n
IC218
MCAD[7]
VCCD3.3V_FLT
MCA[0]
MCA[1]
MCA[2]
MCA[10]
SCL3
SDA3
MCA[9]
MCA[8]
MCA[10]
MCA[11]
MCA[13]
MCAD[5]
MCAD[0]
MCAD[6]
MCAD[7]
MCA[3]
MCA[5]
MCA[4]
MCA[9]
MCA[6]
MCA[8]
MCA[7]
MCA[11]
PSEN_UP
8
7
6
ALE_EMU
25V
100n
C606
5 R4
R2
R3
R1
3
10R
R625
1
2
3
4
4 R4
R3
2 R2
1 R1
10R
R624
PDP_GO1/BL_ON_OFF
5 R4
7 R2
7 R2
6 R3
6 R3
8 R1
10R
10R
5
6
7
R626
R627
5 R4 4
3
2
1
4
3
2
8 R1 1
LOC_KEY
R629
1k
10R
R6037
D600
1 R1 8 MCA[13]
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BZT55C5V1
2 R2 7 MCA[12]
A0
A1
A2
A3
A4
A5
A9
A6
A8
100 D5
D0
D6
D7
ALE
A10
A11
3
S600
PSEN
VSS3
R3 6
Q6009
MCA[14]
FL_CE
1
2
R6035
BC848B
4k7 STBY_3V3 10R

R628 5
VDD3_3_3
4 R4 MCA[15]
PL606
MCAD[1] R4 D1
5 4 1 FL_RST 80
MCAD[4] R3
6 3 2 D4 A7 79
3
2
1
STBY_3V3
MCAD[2] R2 D2
7 2 3 A13 78
PL604
MCAD[3] R1
CPU_GO1/STBY
8 1 4 A12
1k
D3 77
R6038
STBY_2V5
L600
PDP_GO/BL_ON_OFF
5 XROM A14 76
L601
R6036
STBY_3V3 6 VDD2_5 VDD3_3_2 75 VCCD3.3V_FLT
4k7
BLM21B201S
50V
22u
C613
100n
25V
C607
C608
100n
SCL
SDA
7 VSS VSS2 74 STBY_3V3

25V
C609
100n
Q6008
22u
R688 8
25V
VDD3_3 VDD2_5_1 73
BC848B
C611
C612
100n
STBY_3V3 4k7
STBY_2V5
16V
100n
C610
9 P0_0 FL_PGM 72
4k7
SDA2
R632
R689
4k7
CPU_GO
10 A15 R639
SCL2 P0_1 71 10R
R6013
R6030 4k7 1 8
R1 MCA[17]
AC_INFO 47R 11 P0_2 A17 70
R690
R6031 4k7 2 7
R2 MCA[16]
MAIN BOARD - MCU INTERFACE CIRCUIT
MUTE_AMP 47R 12 P0_3 A16 69 WR_EMU

R694
4k7 3 6
R3 MCA[18]
RX1_RST# 13 P0_4 A18 68
R695
4k7 4 5
R4 MCA[19]
RX1_INT 14 P0_5 A19 67
UP_IRQ
R696
UP_TXD
UP_RXD
4k7
RD_EMU R640
CPU_GO1/STBY 15 P0_6 NC5 66
4k7 STBY_3V3
DVD_12V_SENSE 15k
C615
R698 16 P0_7 RD 65
IC220
100n
S610
WR 64
3k9
17
SDA5550M
ENE
R697
S627
S628
S629
S615 18 STOP NC4 63

R648
19 OCF P1_7 62 4k7 STBY_3V3
4
3
2
1
PL308
20 EXTIF NC3 61
21 CVBS BLANK_COR 60 R6042 S601

R684 1k
UART SOCKET FOR IDTV
STBY_2V5 22 VDDA2_5 B 59 75R

L603
R685
25V
C621
100n
R6043
50V
22u
23 VSSA G 58 75R
C620
4k7 STBY_3V3
R686
PIN8_SC1 15k 24 P2_0 R 57 75R
R654 L604
STBY_2V5
Q6011
25 P2_1 VDDA2_5_1 56
BC848B
25V
3k9
R653
C622
100n
25V
26 P2_2 VSSA1 55
C623
100n
2
1
PIN8_SC2 15k
15k 27 P2_3 NC2 54 50V
R655
R656 33p
PL605
RST_H
28 NC
25V
3k9 XTAL1 53
C625
100n
25V
3k9
R660
C626
100n
R657
C624
R2305 29 HS_SSC XTAL2 52
LOC_KEY
X600
6MHz
10k C627
STBY_2V5 1k
30 VS NC1 51
R661
50V
33p
Q2299
BC848B
25V
MMC_IR GIRISI
100n
C628
RST
P3_4
P1_4
P3_6
P1_6
P3_0
P3_2
P3_7
P1_0
P1_2
P4_2
P3_5
P1_5
P3_3
P1_3
P4_3
P3_1
VSS1
VDD3_3_1
P1_1
100R
R2306
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
STBY_3V3
VCC_8V
PIN8_SC3
IR
S6313
25V
C633
100n
VCCD3.3V_FLT
100n
4k7
BC848B
Q6010
R6040
25V
R6014
4k7
C630
100n
R692
4k7
4k7
R691
4k7
C631
R693
RST#
3
VCCD3.3V_FLT
R679
1
PC_STBY
4k7
100R
R6039
IC221
LM809
L609
STBY_5V
4k7
2
STBY_3V3
STBY_3V3
R680
BLM21B201S
VCCA_2V5
4k7
TV-LINK
R2301 S614 R681 100k 4k7

VCCD_3V3
47k SC2_FB
Q2300
4k7 R687 R676

SDA_TVLINK
BC848B
R682
10k
R2303
R6017
R2304 S613 4k7
FB
TV_LINK 100R
R6041
4k7
R2302
2k7
47k S6314
R2300
RST#
HDMI_CEC R6044
Q2301
VCCD_3V3
BC848B
4k7
IR
PDP_GO1/BL_ON_OFF
STBY_3V3
PWM
LED2
LED1
SCL3
INT#
PORT
SDA3
UP_IRQ
UP_TXD
UP_RXD
GAL_IAP
PROTECT
NVM_WP
STBY_3V3
SDA_TVLINK
P1_5V IC3000
LM1117
R2070
HDMI_3V3
1k
P1_EVCC5
IC2013 IN OUT 2
R2066
R2067
VCC_5V 3 HDMI_3V3_PLL
470k
470k
GNDVOUT
C3000 C3001 1 4
1 S1 D1 6 P1_HPD 100n 100u C3003 C3004
16V 16V C3002 100n 100u
DSDA
100n 16V 16V
R2069
IC2012 UPA672T 16V
10k
RX1_RST#
VCC_5V 4k7 2 G1 G2 5
C2072
R2062
R2068
100n
1 S1 D1 6
4k7
25V
IC3001
R2063
UPA672T LM1117
47k
IC2003 3 D2 S2 4
VCC_5V IN OUT 2
2 G1 G2 5 DSCL 3 HDMI_3V3
GNDVOUT
R2098 C3005 C3006 1 4
1 A0 VCC 8 100R SW_ENABLE 100n 100u C3008 C3009
16V 16V C3007 100n 100u
Q2 100n 16V 16V
BC848B 3 D2 S2 4 16V
AUDIO_AGND
AUDIO_AGND
2 A1 WP 7
24LC02 DIN[0-23]
3 A2 SCL 6
AMP_PIN7
DIN[10]
DIN[11]
DIN[12]
DIN[13]
DIN[14]
DIN[15]
DIN[8]
DIN[9]
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
DIN[16]
DIN[17]
DIN[18]
DIN[19]
DIN[20]
DIN[21]
DIN[22]
DIN[23]
HDMI_3V3_PLL
R2064
P1_DDC_SCL 56R
4 VSS SDA 5
C2100
R2088
100k
2n7
50V
1 R1 8
1 R1 8
7
5
R2050
R2052
R2065
33R
33R
R3
R3
R2
R2
R4
R4
P1_DDC_SDA 56R
SDA3
SCL3
C2101
4
DAC_AOR 560R
1 R1 8
1 R1 8
7
5
R2051
R2087
R2049
C2068 10u R2091
33R
33R
R3
R3
R2
R2
R4
R4
AUDIO_AGND
RX1_RST#
25V 50V 20k
RX1_INT
100n
AMP_PIN6
OGND_SII
4
OGND_SII
AUDIO_AVCC5
0VCC_SII
0VCC_SII
S818
S819
GND_SII
VCC_SII
60R_100MHZ_3A
C2103
R2053
AUDIO_AGND
4k7
L2014
10u
50V
C2104
25V AUDIO_AGND
100n C2102
71
61
51
75
73
65
63
72
70
69
55
53
62
60
59
52
68
67
58
57
74
66
64
56
54
100n R2089
AUDIO_AGND 25V 47k
C2069 AUDIO_AVCC
Q1
Q11
GND3
VCC3
Q3
OGND3
OVCC3
Q13
Q5
RSVDL2
Q0
Q2
Q9
Q10
Q7
Q12
Q8
Q6
OVCC4
OGND4
Q4
CSDA
CSCL
RESET
INT
10u C2099 270p R2090
50V 50V 47k
5
8
6
C2070
E
CLK_2EX
F
100n
TP100
DSDA
AMP_PIN3
25V 76 DSDA Q14 50
R2094
DSCL 77 DSCL Q15 49 33R
C2071
1n IC2008
PL2001 50V OGND_SII 78 OGND5 Q16 48
MC33202
19 P1_HPD 79 PGND1 OVCC2 47 0VCC_SII
R2048
18 P1_CBL5V 80 PVCC1 ODCK 46 33R
R2047
D
C
A
B
17 RX1_AVCC3 OGND_SII 1 R1 8
81 EXT_RES OGND2 45
4
16 P1_DDC_SDA AVCC_SII 2 R2 7
82 AVCC Q17 44
50V
3 6 10u C2093
15 P1_DDC_SCL 83 RXC- Q18 43 R3 R2081 AUDIO_AGND
DAC_AOL 560R
AMP_PIN3
AMP_PIN6
AMP_PIN7
S817
14 4 R4 5
84 RXC+ Q19 42 C2092 270p
C2091
R2080
100k
33R 50V
2n7
S816
50V
13 CEC 85 AGND1 GND2 41 GND_SII
AGND_SII
S815
12 86 RX0- VCC2 40 VCC_SII
R2046
S814
11 1 R1 8
87 RX0+ Q20 39
R2085
R2086
AUDIO_AGND
AUDIO_AGND
1k2
5k6
10 AGND_SII 88 AGND2
IC2002 Q21 38
2 R2 7
R2078
R2079
5k6
1k2
9 AVCC_SII 89 AVCC1
SII9993 Q22 37
3
R3 6 C2098
AUDIO_AGND
8 AGND_SII 4 R4 5 C2090
90 AGND3 Q23 36 2n7
R2084
S813 R2045 33R AUDIO_AGND 50V
4k7
7 91 RX1- DE 35 33R DE_2EX
2n7
AUDIO_AVCC5
R2077
AUDIO_AGND
S812 R2044 50V
4k7
6 33R DVS_2EX C2097
92 RX1+ VSYNC 34
R2043 AUDIO_AGND
S811
5 AVCC_SII 33R DHS_2EX C2089
93 AVCC2 HSYNC 33 2n7
R2042 AUDIO_AGND 50V
S810
R2082
1 R1 8
R2083
AGND_SII
2k32
2k32
4 94 AGND4 SCK 32 DAC_SCK 2n7
50V
R2075
R2076
3 AVCC_SII 2 7
2k32
2k32
95 AVCC3 WS 31 R2 DAC_WS
C2095
3
C2096
2 R3 6 DAC_SD0
96 RX2- SDO 30
3u3
50V
10u
4 5
C2088
1 97 RX2+ SPDIF 29 R4 50V R2074
3u3
50V
33R 25V 270k AUDIO_AGND
AGND_SII OGND_SII 100n
98 AGND5 OGND1 28
AUDIO_AGND 270k
GND_SII 99 GND4 MCLKIN 27 33R 33R DAC_MCLK R2073 C2094
R2040 R2041
5
VCC_SII 100 VCC4 MCLKOUT 26
AGND
VA
AOUTL
AOUTR
DACGNDG
DACGNDR
DACGNDB
DACVCCG
DACVCCR
DACVCCB
DACGND
RSVDO1
RSVDO2
DACVCC
RSVDL1
PGND2
ANRPR
ANBPB
PVCC2
COMP
GND1
PLLIN
OVCC
ANGY
VCC1
RSET
NC1
NC2
NC3
IC2006
HDMI_3V3
CS4334
11
21
13
10
15
23
25
12
17
19
20
22
16
18
14
24
1
5
2
9
6
8
4
DEM/SCLK
0VCC_SII
RX1_AVCC3
R2035
SDATA
100R
MCLK
LRCK
60R_100MHZ_3A
R2038
HDMI_3V3
4k7
TOCOMP
C2054
C2055
C2056
C2057
C2058
C2059
100n
100n
100n
HDMI_3V3
VCC_SII
L2012
10u
25V
1n
1n
VCC_5V
50V 25V
10u
4
1n
C2062
GND_SII
3k9
R2039
C2067
25V 25V
100n 47n
DAC_SD0
DAC_WS
DAC_SCK
DAC_MCLK
IC2014
S805
L2016 C2063
AUDIO_AVCC5 C2060
S809
S808
VCC_5V
L2015 330R_100MHZ_3A C2066
60R_100MHZ_3A 50V 1 1OE A8 8
R2095
HDMI_3V3 AVCC_SII 10u
10n
10k
C2073
C2074
C2075
C2076
C2077
C2064
60R_100MHZ_3A
L2017
100n
100n
100n
25V TOCOMP
10u
25V
16V
25V
25V
50V
1n
AUDIO_AGND C2061
330R_100MHZ_3A
R2097
R2096
1A
330k
2
L2013
S800 2OE 7
27k
AGND_SII
10u
16V SN74CB3Q3305
VCC_5V
S807
HDMI_CEC 3 1B 2B 6
S801
HDMI_3V3 VCC_SII Q1
2N7002
C2078
C2079
C2080
C2081
C2082
P1_5V
100n
100n
10u
16V
25V
25V
50V
50V
C2065
1n
1n
100n
25V 4 A4 2A 5
S802
1N5817
D2022
GND_SII
D2021
HDMI_3V3_PLL
R2071
S803 P1_CBL5V 10R P1_EVCC5 S806
BZT55C5V6
HDMI_3V3 0VCC_SII 1N5817 CEC
BZT55C5V6
D2020
C2083
C2084
C2085
C2086
C2087
100n
100n
10u
16V
25V
25V
50V
50V
1n
1n
D2023
S804
OGND_SII
No. 0210 MAIN BOARD - HDMI/DAC CIRCUIT

43
L918
PL903
1
VCC_12V PL904 VCC_5V
1
PDP_GO1/BL_ON_OFF
S908
PANEL_VCC1 PL902 VCCA_3V3
L917
2 S909
VCCA_3V3
STBY_3V3
LG_1/IRQPDP
3 S910
STBY_5V
AC_INFO
L906
5V 4
MMC
VCC_12V
100u
C900
SUPPLY
16V
5V
L909 STBY_5V
N.C
S903
FAN1616AS-3.3 STBY_3V3
S904
STBY_5V
1 IC902 D905
L905 SOT 223 L923
L913
2 +12V 1N4007
3 2 STBY_2V5 10u
L920 D906
1000u
100n
220u
C906
C908
C920
C916 1
16V
50V
16V
220u
C914
3
16V
100n
L900 16V 1N4007 IC904
L907
4
L901 R918
5 1 SW.COLL. DRI.COL. 8
L902
LM317
IC900
6 STBY_3V3
R916
100R
R917
100R
2 EMITTER SENSE 7
L903 3 IN OUT 2 C942
R922
MC34063A
3k3
ADJ
7 3 CAP. VCC 6
C901 1
47u
C904
50V
R914
L904 VCC_8V 56p
10k
100n
8 4 GND COMP. 5
16V
100p
C944
R902 C910
9
R907
1k 100n
10k
C909
47u
16V
50V
VCC_12V
1N4148
10 R912 D907
D912
R903
BC858B
5k6
10k VCC_5V
PROTECT Q901
11 1N4148 56k
1.8V_ON/OFF R921
R908
Q900 D908
12 10k
BC848B VCCA_3V3 C945
R920
R919
R910
6k8
2k2
10k
1N4148
PL900 L919
VCC_5V D909 22u
22u
1000u
100n
100n
100n
100n
C912
C932
C933
C934
C935
C903 100n VCCD_3V3
16V
N.C 56p
1N4148
R900 CS52015-3
470R IC901 D910
C943
PANEL_VCC1
PANEL_VCC
VCC_8V
L924
22u
STBY_3V3 47u 3 VIN VOUT2
R901 GND 1N4148
1 C919
100u
C931
470R C915
16V
R909
120R
C902 L912 100u
100n 16V
16V VDDMQ_2V5
C922
100n
22u C917
D900
16V
100n
16V R915 10u
STBY_2V5
PL901 470R STBY_2V5
C918
1N4007 C946
50V
N.C 120R 1R N.C
PDP_GO/BL_ON_OFF 1 D901 R911 R913 S907
A_DIM_PWM 2 1N4007
VCC_33V
L921
6
DIG_DIM_PWM 3 D902
BLM21B201S
IC223 3 2 VCCA_2V5
SEL 4 1N4007 L922
R925
SAP 30030067 ADJ TYPE 1
10k
1N4148
C921
IC903
47u
C923
50V
D913
D903 BLM21B201S
PROTECT 5 LM2576 100n
LD1117 16V
SOT 223
FEEDBACK
1N4007
CPU_GO1/STBY 6
1
OUTPUT
VCCA_3V3
D914
ON/OFF
C947
GND
VCC_33V 7 L915
VIN
1_8VMAIN VL1_8
FDC642P
100n
100n
100u
C925
C936
C939
22u
16V
16V
16V
VCC_12V
100u
C927
8 1.8V_ON/OFF
330R
R923
10u
16V
S905 Q902
1
S913 16V
S912
PORT 9 S911
Q903
VCCD_3V3
L908
D915
160R 1_8VMAIN
10 VCC_12V R905 S902
22u R904 L914
L911
330R 1_8VMAIN VD1_8
100u
100n
100n
100u
C905
C924
C937
C940
22u
16V
16V
16V
16V
22uH_3.9A_SMD
100u
C928
16V
R924
L910
10k
S900
STPS745
A_DIM_PWM BRT_CNTL 22u

SS33
D911
1000u
D904
100n
C911
C913
S901 L916
16V
16V
DIG_DIM_PWM 1_8VMAIN VA1_8
100n
100u
100n
100u
C926
C929
C930
C938
C941
22u
22u
16V
16V
16V
PANEL_VCC_ON/OFF
No. 0210 MAIN BOARD - POWER SUPPLY CIRCUIT

44
No. 0210 POWER BOARD - SHEET 1
45
46
47
48
49
4P
JK100
12
33p
50V
C100
D100
BZT55C10
L101 L100
SVHS_Y 34
No. 0210
600R_100MHZ_200mA 600R_100MHZ_200mA

D101
50V
33p
C101
BZT55C10
L103 L102
SVHS_C
600R_100MHZ_200mA 600R_100MHZ_200mA
S100
PL103
S101
D102
1
33p
50V
BZT55C10
C102
L105 L104
FRONT_VIDEO
600R_100MHZ_200mA 600R_100MHZ_200mA
A
23 1
JK101
YELLOW_FAV
D103
50V
100p
C103
BZT55C10
1 FRONT_VIDEO L107 L106

1 FRONT_AUDIO_R R100
2 600R_100MHZ_200mA 600R_100MHZ_200mA
A
PL100
23 1
2
JK102
SVHS_C R109
PL104
3 R107 SVHS_C
SVHS_Y R110 3
1P_RED_FAV
4 R108 SVHS_Y
4
5
D104
FRONT_VIDEO 5
50V
C104
100p
BZT55C10
6 FRONT_AUDIO_R L109 L108

6 FRONT_AUDIO_L R101
600R_100MHZ_200mA
7 600R_100MHZ_200mA
A
23 1
7
JK103
FRONT_AUDIO_R
8 FRONT_AUDIO_L
FRONT_AUDIO_L 8
WHITE_FAV
9
600R_100MHZ_200mA
LINE_OUT_R 10 1 LINE_OUT_R HEADPHONE
50
L110
9 6
11
50V
LINE_OUT_L 2
PL102
C105
8 5
LINE_OUT_SUB 12 3 LINE_OUT_L
600R_100MHZ_200mA L111
7 4
D105
4 LINE_OUT_SUB HP_R R102

100p BZT55C10
L112
600R_100MHZ_200mA 3
50V
4n7
C106
2
JK104
1
PHJACK
FRONT AV BOARD
50V
4n7
HP_R 1 1 HP_R L114 600R_100MHZ_200mA

C107
HP_L R103
L113
2 2 600R_100MHZ_200mA
PL105
PL101
HP_L 3 3 HP_L
D106
BZT55C10
HEADPHONE 4 4 HEADPHONE
D107
50V
100p
C108
L116 L115
BZT55C10
LINE_OUT_SUB R104
600R_100MHZ_200mA
A
600R_100MHZ_200mA
23 1
JK105
WHITE_FAV
D108
50V
100p
C109
BZT55C10
L118 L117
LINE_OUT_L R105
600R_100MHZ_200mA
600R_100MHZ_200mA
A
231
JK106
WHITE_FAV
D109
50V
100p
C110
BZT55C10
L120 L119
LINE_OUT_R R106
600R_100MHZ_200mA
600R_100MHZ_200mA
A
23 1
JK107
1P_RED_FAV
No. 0210
4
3
2
1
PL700
1 VIN
35V
STPS745
470u D901
N.C
22u
L729
2 OUTPUT
C821 D904
S730
SS33
3 GND
IC708
LM2576
L109
22u
L904
4 FEEDBACK
25V
22u
1
2
22uH_3.9A_SMD
L727
25V 1000u
1000u
PL702
5 ON/OFF
C822
C820
R754 R755
C808 C807
1k8 22k
C826
470n 470n
63V 63V
100n
25V
L726
40uH
L725
40uH
C815 C816
15V_AUD
15V_AUD
15V_AUD
100n 100n
25V 25V
50V 50V
1n 1n
C796 C795
L722
L721
C803
50R_100MHZ_3A
50R_100MHZ_3A
50V 220u 50V

10n 25V 10n
C818
C794 C793
C802 C801
22n
50V 100n 100n
2 50V 50V
R766 R767
12k 3k3 1
PL707
vcc 5v
24
23
22
21
20
19
18
17
16
15
14
13
S737
BSLP
BSLN
Q709
1u
PVCCL4
PVCCL3
PVCCL2
PVCCL1
LOUTP2
LOUTP1
C817
LOUTN2
LOUTN1
PGNDL2
PGNDL1
BC848B
16V
C792
22n 25 VCLAMPL REFGND 12 33k
50V
2
R745
26 AGND1 VOLUME 11
S723
S724
1
R742
51
120k 27 ROSC VARMAX 10
IC703
LM809
220p
3
50V
R756 28 COSC VARDIFF 9
100k 25V 100n
50V C779
1k
100u
S732
29 AVDD VREF 8 18k

R770
R746
C778
C811 30 AGND2 AVDDREF 7
1u
31 VAROUTL LINN 6 1
S734 S733 MAIN_OUT_L
IC702
1u
C790
32 VAROUTR LINP 5 2
TPA3004D2
PL701
1u
C789
Q710
33 AVCC V2P5 4 3
BC848B
1u
MUTE_3V3
C791
MUTE 34 MODE RINP 3 4
RESET OUT
1u
C788
35 MODE_OUT RINN 2 5
C776 MAIN_OUT_R
C787
36 VCLAMPR SD_NOT 1
1u
S736
1k
15V_AUD 16V
C824
R771
S735
HIGH=ON
LOW=OFF
BSRP
PVCCR4
PVCCR2
ROUTP2
PGNDR2
ROUTN2
PVCCR3
BSRN
PVCCR1
ROUTP1
PGNDR1
ROUTN1
50V
9k1
100n
R768
25V 100n
37
38
39
40
41
42
43
44
45
46
47
48
BC848B
Q715
S738 C777
25V
MUTE_3V3
220u
AMPLIFIER BOARD (D-CLASS)

Q604
Q603
50V 50V
BSN20
BSN20
C775
4k
100n 100n
S739
25V
100n
R772
C825
50V C783 C782 50V

MUTE
10n C813 10n

R773
3k3
C814
C781 100n C780 R765
25V C823 12k
220u
100n
25V 100n
C784 25V
L719
L718
15V_AUD
50V 50V
15V_AUD
1n 1n
50R_100MHZ_3A
50R_100MHZ_3A
C786 C785
L724
L723
40uH
40uH
15V_AUD
15V_AUD
C806 C805
470n 470n
63V 63V
2
1
PL703
15. CIRCUIT BOARD DIAGRAMS
R6018 R259 IC213
Q903
A
R248 Q6006 251005
17MB15E-5
PL903
PL200
R246 S6300 R924 PL600
VER
R277 R6015 S907
A
R265 S6312 IC901
S637 R6016 R258
Q902
S908 PL902 C945
S6311 S6310
C2052
C942
C944
S650 Q6007 S909 R257
C2051
R922
R6019 S910 C914
R925
R923
R208
IC900
R209 R256
D201 L909
C947
R210 D912
S608
IC904
R255
L924
R284 R280 L913 S607
R921
R281
R282 C943
D200
C916
IC214
D906
D905
Q208 C290
L923
R913
R916 S223
R283 C917 C931
PL904
R902
R903
C904
D2502
R212 R215 R218
IC902
C903
R918
R211 R213
IC212
R920
R919
R917 S649
C915
Q207 R279
D2501
L907
R911
D903
D902
D901
D900
C910
L912
R2084
R2082
R2083 R2074
C909 C946
R219
R216
C2053
C281
R910
C920 Q901 R908 C918
L917
L904
L903
L902
R2090
R2089
C353
C901
C2099
R2073
R214
R217 C932
R912
R914
R907
C2094 S337 R909 C902
C933
R901
R238
IC211
JK300 C302 S336 C906 R915
C935 C919 C922 C912
R2085 C934
C289
R331 R2086 C2096
IC318
D106 Q900
C2088 C2098 C2101
D907 C530
C2097 C900 C515 C521 C2250
C505
L905
C2103 D910 C502 C504
R312 R313
L901
C507 C526
D908 L919 C510 C503 C532
R326
C509 C506 C529
S903
S904
C2102 C523
R516
C2095 C508 C531
D909
S6319
S6318
C513
C527
JK301 R2076 S314 S307 C511 C528
C2089
R501 R500 R508
L501
C512
LF
S309 S308 C522 C2251
R2088
R2087
R2075
S6317
C356 C908
R900
R2077 S6320 R505 C519
C363
C364 C2090 PL607 R515
D104
R2091
C2104 C514
L900
R332
L918
L906
2 60
C357 R512 R504
IC2006
C2100
IC2008 L401
C2404
PL900
R2078
C2093
C518
C3009
C2091
R510 L920
C500
R517
D102
C525
C517
L2017 L500 C431
IC1
R518
IC903
R2079 R2080 L921 C2403 C2215
JK302 R333
C501
R2081 R502 C2402
C433
1 59
IC3001
C2092 R506 L922 C2401 C2214
C365 C3008 C2252 C2400 C2213
S623
C601
C923
C3007 IC219 C2253 C2212
R509
C358
R503
C524
C3005
R6039 S613
R2214 C520
R6040 R692
R521
R520
R519
S600 R6035
R6036
C3006
IC107
C516
D226
S622
C470
Q6008
R507
R513
R511
C1001
C3004
R2213
R514
S614
R434
C360
R2209
R2208
C921
IC217
JK304 L400 R430 S620
R604 C471
R433
C451
C449
C456
C448
C446
D2022
C452
C447
R6038
Q6009
C3003 R2306 S621
L2016 C3000 C600
IC224
R2305 C423
PL104
IC3000
R2217
S624
C3002
IC622
R6037 R2218
S323 L317
R607
D2020
R606
R610
R429
R611
C436
S110 R431 C437 S330
C407
C405 R408
C401 R401 S430
C408 R405 S427
S439 C404 R407
S438 C400 R400
C402 R402 S431
C406
C403 R406 S425
R103 R432
C413 R439 R440 R627

R424 C472 C473
R423
R244
D225
C2235 PL103 S112 C435 R2215
C426 R422
S108
30
29
S604
C605
S646
C2087
C2086
C2085
C2084
C2236 S111 C434
Q100 R2216
R102 S107
R404
D2021 C2237 C429 C2211
C3001
Q6011
R6005
R2070 C2238 C2210 S647
Q602
R2069
S113
Q603
X S6314
JK303 R2066 C466 C2209
S640
S641
R403
C427 C2208
C410
R6042
S426
R100
C2083
C425
IC2013
R413
C2207
IC2012
S6315
Q604
R6041
R691
R412 R415
R679 S412 S414
R680
R681
R682
R676 IC221
R101
R6043
S818
S819
R414 C2220 C608 C359
S803
R419 C613 L316
R628
R624 L601
R625
R626
Q605 C2221 R2212
Q2
1 1
C418
S605
C412
S601
S6316 C631 C428 S109 C2254 S440
C422 R697 S324
C462
C450 R228 C463
S441
R6013
R600
C419 C2222 S610
IC2003 R2062
IC220
R233
L609
R2068 S615 R6030
S331
L600
C606
S415
R2098
Q601
R417
C621 C622
C1000
R2063
R2211
C625 R653
C424 S643 C421 C420 R654
1
Q600
2
R2052 R2051 R2050 C628
S642
C2069 C2205 D101 C609 R656
C607
S648
R236
R6007
R629 R639
S437
R436
C457
C460
R427
R6006 R418 C2204 R234 C626
C2072
PL2001 R2071 C443 C2203

R657
R426
R6010
R6011
R601
S606
X4
C440
R2065
00
R2049 R2047 R2046 R2042
C444
C611 R2053
R420
C438
C409
R243
R425
C439
C2206
C612
C630
C2216 C2239 C2223 C2070
R688 C467 C2217 C2240
C415
C2224
R2067
R2064 S413 C2071
L2014
R689 R684
C2068
R640
C411
C2218
R6031
R690 R435 C2241 C2225
S817 R2048 S411 C2219 C2226 R686 R685
PCB KENARI
R632
C627
C2242 S804
C624
S805
R694
C633
S816 R2094 C615S442 C455 C454 C430
S815 R695
C414
R2029 R696 C610 R2303
S814
X
C2227 C2231
IC2002
R2210 R698 C623 C2075

S813 R648 C2228 C2232 C2076
S812 R660 L604 C469
R2045 R655 C2229 C2233
IC215
Q2301
Q401
S811 C2230 C2234 C2077
C2073
S810 R2044 R2304 R687
R2302 C465 C442
L408
C2080
K
R2043 S800
S645
S639
S638
Q6010 S6313
L404
C2058
C2059
R2038
C2063
C2066
R2039
R6014
C2081
C2056
C2057
R2035
C2079
C445
3
C620 Q2300 R661
69
R2300 D915
1R3
X600 C929
C939
R6044
S644
R2040
S9
R2301
L407
L406
E
R250
R251
R2041
S603
S602
L603
C459
C2078
R2097 S807
C432
L2013
C2067
C458
C925
R6017
C468
C2065
S802
C2062
IC2014
S809 S806 C926

S801
C930
C2060 S445
L2012
C938
Q402
L2015 Q2299
L402
C2082
L409
D2023
S912 C604
C603
C927
C2061
L916
C416
Q1
C2064
IC218
L915
C911
C936
D600
S628
S627
R428
S629
L206 R252
S808 PL606
R2096 C BE
L204 C258 C941 L910
R416
C2055
C417
D913
L210 R254 D2102
C2074
R2095 Q400 L911

L2004 C278 D222
C924
L2006 R2025 D2500
C928
A K D911 C286 C2054
R225
L2003 R2024 D2104
PL301
R224 C267
C937
L2005 C269 D2003 R223
Q206 C294 C268
L914
D2105
R274
S635
S633
L2007
L205 D224 R222 D904
L213
PL605 PL308 C298
C297 R202
S325
R221
R273
R220 R237 C275 IC210 R229
C940
C905 C296
S200
C282 R242 L908
L208
C2042
R201
R269
S212 C299 C246 S326
R2001 Q202 C1080 R267
C2045
IC2001
R1067
R205
C2050
IC207
Q2000 R2003
R231
Q204
Q205
R266
L200
D220
C276 IC206 R200
R207
D2004
S905
S911
R1033
R287
R230 C2040
D204
R1091
R1097
L1008
C259
Q1004 R241 C283
R1045
R204
C1087
5 1
C1150
C2044
R270
S634
R227 PL1001
Q203 Q200
C1132 PL604
D202
R904
R240
8
C280
R1069 L2009
00
S220
C245
R268
R239
C2047
C2048
C292
L2
Q1011 R905
C303
PL205
R1046
Q1007
R2002 C272 R235
Z
R2027 R1071
R2026 R1070 IC208
R1096
R226
C1085
S902
C285
R203
C913
R2028
C331
R104
C271 Q1009
D2002
D206
C304
R264
C330
C332
C333
R315
R316
R317
R1092
S652
C1079
C1081
C1086
C1084
R1078
S221
R260
R261
C291 R1068 C2046

Q2002 Q2003
L2000 R286
X300 C273
R2031
R2032
C2004 C1078
D210 C288 C1124 C1136 IC223
C1120
D219
DC1164 C1175
R2005 S201 R2202 R2009
X1
C1114
C2039 L2010
L311
00
C279
D209
C2202
C1158
C1148
C1157
C1138
C1156
S651
D2001 R2008
R271
R285
C1121
C1204
L313 C265
C1203
C1112
C1097
C1117
C287
L314
R2004 C1106 R1094
D214
C260
L1018
C1116
C1174
R206 C1113
Q
C1171
R1108
C1176
R1106
R1089 C1125
20
C274
01 004
C1128
R1098 R2006
D914
D212
Q
C317
R1095
C1154 R1090
2
C1118 C1130
C1133
C1126
R1093 L308
R1111
L1020
R1104
C340
S302
R304
L1021
C343
C341
C1137
C1119
R1128
C1122
C250
C323
C321
C252
R2007
C1144
L201
R322
C2038 C1123 C319

1
C1152
L202
C1140
C2005
C1147
C344
D2000 PL201 C262 C1134
C362 C2007 L2011 R306
D2101 C320
C322
C2006 R232 C1145

C263 C300
S636
R323
C1166
C2008 R1130 C318 C361
D216 L1017
IC316
L203 S901
D217 C1149 C348 R305
L207
PL901
S900 C346
R2030
L209 D215
C305
PL203
C270
S316
C261 R307
IC216
L211
L1026
S303 C347
L1023
L1022
L1024
L212 L315 C349
C1169 C1201
Z
C352 S340 C295 C345
L1002
L214 C306 R300
C334
B
L300
C336
C335
L1025
L312
R321
L1019 Z1000 C1024 IC200

1
S312
C316
C1151
S2011 C1028
R3 S3 S2007
C1057
20 01 C1193 C1194 C264
IC317
S2008
B
R1125 C1192 R1011
S2005
S2006
S2010
C350
R
10
C1005 S1008
C325
R2014
C2019
04
R1008
R288
C324
R249 C1200
C310
C309
C308
C313
C312
C311
C1206
C328
C329
C1025
C301 R1126
C327
R318
C1021
C1029
R319
R1013
C1020
C2023
C1177
C1170
R1105
R1107
R1110
C2009
C1153
C1163
R1109
C284
C326
S311 C337 R2204 L2002

D221 S310 C342 R2010
C277 C2024 C338 C249
R309
R310
R311
S2013
C339 D203
R253 C251 R1124
R325
C2020
C2015 C2016
C2013 C2014
C2011 C2012
D1001
C1185 R2016
C2017
S213
D2103 S1009
S2001
D205
PL1
R1036
R1029
Q1015
R1121
R1122
D223 L2019
C266
R1028
C1035
D2100
R289
C2018
C2010
C254
IC204
R2011
S2002
C1191
X1000
R2012
R2013
R2203
L1003
D207 L1030 PL1002 R1123

L2018 Q1016
R290
C2049 L1027 C1167 S1010
IC2000
S205 C247
C1034
S204 C2022
S2003
L1032
R1037
R1032
D208 R2015 D1000 C1183

PL1003
C293
C1162
D1007
R2019 S2009
C R1022
C1195
L1028
R2200
D218
IC209
R1127
R276 L2001
C2037
C1011 C1182
C2021
R1025
C1037
C1045 R1038
R1031
C1198
R275 C1180 C1202

C2034
C2031
C2030
C2028
S2000
C2026
D1003
C1014 L1029
CQ1003
Z1003
C248 C1197 D211

C1179
C2025
R1112
R1129
C1199
C253
C1042
C1036
R2021
C2033
C2032
C2029
C2027
R2020
R2022
R2023
R2018
R1100
C1168
R1101
R2017 C1184 D213
C2036
R1042
R1103
C1010 R1043 C1048

C1172 C1205 C2200 C1006 R1113
C1173
R1102
C1178
TU1001
C1039
C1165
C1181 C1159
C1043 R1034 R1040
R1050
R1044
R1118
R1041 R1119 Q1014 S1006

C1041 S2012 C1056
C1189
S1005
R1052
Q1013
R1120
R1027 C1187 C1054 R1051 R1039

R
C1055 Q 1005
10 10 R1026
S1003 R1048 IC 205

35 02
Q
C1052 R1049 R1005

R1010 R1114
C1038
X1001 R1009 R1030

C1196
IC201 D1005
C1022
C1030
C1023 C255
C1040 L216
R1023
3
C1047
JK200
C1049
C1031 L218
C2201 C1027
1
Z1001
R2201
2
L219
R1012
C1026
COMPONENT SOLDER
C1015
S1000
C1008
L1001
C1004
S1007
R1024
E
C257
Z1002
C1188 R1115
C1002
R1000
C1013
C1007
R1001
C1003
D1006
(TOP) SIDE (BOTTOM) SIDE
D1004
C1186
C1009
L1000
C1012
R1117
TU1000 R1116 D1002
L1031
No. 0210 MAIN CIRCUIT BOARD

52
THE UPDATED PARTS LIST
FOR THIS MODEL IS
AVAILABLE ON ESTA
17. WALL MOUNT TEMPLATE DIAGRAM (32-INCH MODELS ONLY)
853.90 104.00 400
200
600.00
649.00
245.00
IDTV
MMC
SIDE AV
BUTTON
FUNCTION STAND
No. 0210 WALL MOUNT DETAIL

54
Hitachi, Ltd. Tokyo, Japan
International Sales Division
THE HITACHI ATAGO BUILDING,
No. 15 –12 Nishi Shinbashi, 2 – Chome,
Minato – Ku, Tokyo 105-8430, Japan.
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www.hitachidigitalmedia.com

Hitachi LCD 32LD8700

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No.

ATTENTION: Les données fournies dans le présent

Die in diesem Wartungshandbuch

SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT

It supports the following peripherals:

General description of UV1316:

TUNER AGC VIF-AGC RC VCO DIGITAL VCO CONTROL AFC DETECTOR

(6, 12, 13, 14,

sound intercarrier output FM-PLL

5. VIDEO SWITCH TEA6415

6. AUDIO AMPLIFIER STAGE WITH TPA3004D2

10. SAW FILTERS

11.1.1. General Description

11.3.1. General Description

11.3.2. General Features

11.4.1. General Description

11.5.1. General Description

11.6.1. General Description

PIN Function Table

11.8.3. Pin Connections

11.9.2. General Description

11.10.3. Pin connections

11.13.1. General Description

SOT-223 TO-220 TO-252

Top View Top View

11.14.1. General Description

11.14.3. Pin Description

11.15.1. General Description

11.16.3. Pin connections

11.18.1. General Description

11.18.3. Pin Connections

11.19.1. General Description

11.20.1. General Description

11.21. SDA55XX (SDA5550)

11.21.1. General description

11.22. Sil 9993

11.22.1. General Description

11.23.1. General Description

11.24.1. General Description

11.24.3. Pin Connections

11.25.3. Pin connections

DIP Pin connections CO Pin connections

NC: Not connected

SDA Serial data Address Input/Output

11.26.1. General Description

11.26.3. Pin description

11.27.1. General Description

SYMBOL PIN DESCRIPTION PIN VALUE

11.28.1. General Description

SYMBOL PIN DESCRIPTION

11.29.1. General Description

TERMINAL I/O DESCRIPTION

11.30.1. General Description

11.30.3. Pin Connection

11.31.1. General Description

11.31.2. Pin Connections and Short Descriptions

Pin No. Pin Name Type Connection Short Description

12. SERVICE MENU SETTINGS

12.1. Picture Adjust

12.9. Menu Languages 1 & 2

VPC3230D 8-BIT YUV

No. 0210 BLOCK DIAGRAM

5k6 2 12C_DA MONO_IN 47 N.C C1169