LABORATORY MANUAL COURSE CODE: ECE 204 COURSE TITLE: UNIFIED ELECTRICAL LAB-II

LIST OF PRACTICALS
S.No. 1 Description To design an implement a function generator to generate 1) Square, 2) triangular and 3) sinusoidal waveforms using IC741 and simulate using pSpice To find gain of the transistor in CE, CB and CC configuration on breadboard and simulate using pSpice To Design and implement 1) Mono-stable 2) Bi-stable and 3) Astable multivibrators using IC555 Timer on breadboard. And simulate using pSpice To implement Full Adder using NAND gates and using pSpice Verify superposition theorem and thevenins theorem using experimental set up on bread board and simulate using pSpice MTE To realize a 7-segment code converter on breadboard To realize D/A converters using IC 741 1) R-2R ladder 2) Weighted Ladder, compare the results obtained on breadboard and simulate using pSpice To design and implement an CLIPPER, CLAMPER circuit on breadboard and simulate using pSpice To develop a program to study aliasing in signals using Matlab To study the gain of differential amplifier by varying the value of RE 1) RE= 4.1k ohms 2) RE= 82k ohms on breadboard and and simulate using pSpice To Design and Plot Frequency response of 1) LPF 2) HPF 3) BPF and 4) BRF using IC741 on breadboard and simulate using pSpice To find gain of the JFET on breadboard and simulate using pSpice To design and realize MOD-10 1) Up counter 2) Down counter on breadboard Page No.

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EXPERIMENT NO. 1 - Sine Wave Oscillator Sinusoids are useful waveforms, because they are convenient basis functions for analyzing the response of (linear) systems involving time derivatives and/or integrals of signals. Any sufficiently well-behaved signal can be represented by a linear combination of sinusoids (through Fourier transforms) and derivative and integral operations on any of the basis functions yields another basis function. In fact, sinusoids are the only functions that retain their original shape during processing by a linear system, which makes it easy to characterize the effect of the system by specifying only the amplitude and phase change. In mathematical language, sinusoids, or rather imaginary exponentials are the eigenfunctions of linear systems. Consequently, sine wave generators are useful tools for circuit testing and diagnosis (as you have already seen in the previous labs). In this lab, you will design a variable frequency sine wave generator. Although the approach you use cannot yield a sine wave of sufficient purity (i.e. low harmonic content) for use in a high quality generator, the quality of its waveform is sufficient for many less demanding applications. This is a fairly inexpensive way of producing a versatile waveform generator (sine, triangle and square waves simultaneously) over a broad frequency range. The approach you will use involves the generation of a triangle wave followed by a conversion of the triangle wave to a sine wave using a nonlinear conversion circuit. It is relatively easy to generate a high-quality variable frequency triangle wave using an op amp integrator circuit with a variable input resistor. (Alternatively, it is easy to convert a variable frequency square wave to a triangle wave using an integrator). The triangle wave generator will be made using a combination of an integrator and a Schmitt trigger as shown in the figure below. Although in practice the integrator and Schmitt trigger functions can be integrated into a single fairly simple circuit, the approach outlined in this lab will give you exposure to two opamp applications (integrators and Schmitt triggers separately). A circuit having the block diagram shown on the next page can generate a triangle wave. When the Schmitt trigger output is negative, the integrator output ramps positive. When that output reaches the positive-going threshold of the Schmitt trigger, the Schmitt trigger output goes positive. This causes the integrator output to ramp downward until the Schmitt triggers negative going threshold is reached. This sends the Schmitt trigger output negative, and the cycle repeats. The symmetry of the triangle wave depends on two things. First the negative and positive outputs of the Schmitt trigger must be equal in magnitude to obtain equal slopes for the positive and negative going parts of the triangle wave. Second, the

Positive and negative switching points of the Schmitt trigger, which must be equal magnitude, control the positive and negative peaks of the triangle wave. Although an opamp-based Schmitt trigger will not precisely meet these two conditions; the accuracy will be acceptable for the purpose of this experiment. Your task is to determine how to implement the integrator and Schmitt trigger in such a way as to yield a triangle wave generator having a frequency range of at least 100Hz to 10 kHz. You will be allowed one 10 k potentiometer for adjusting the oscillator frequency. The amplitude of the square wave need only be greater than 5 volts pp, however, the triangle amplitude should be as near a practicable to 5 volts pp. The triangle to sine conversion circuit you will use is an example of a class of nonlinear circuits. It utilizes the nonlinear I-V characteristics of the base-emitter junctions of bipolar transistors. Attached is a copy of the original journal article (W.M.C. Sansen, S. Lui, S. Peters, and Robert G. yer, The Differential Pair as a Triangle-Sine Wave Converter, IEEE J. Solid-State Circuits, Vol. SC-11, June 1976, pp. 418-420) describing this triangle to sine conversion technique. Using a single CA3086 NPN transistor array chip, design and construct a circuit following the technique outlined by Meyer, et al. It is almost certainly easiest to use the collector output option rather than the emitter option that they also mention. The combination of this circuit with your triangle wave generator will be a variable frequency sine wave generator. You probably have to put something between the triangle output and the sine-converter input to reduce the signal amplitude to an appropriate value. The output sinusoid shall be 5 volts pp too and have a zero mean value. The output source impedance shall not exceed 100 ohms. (This does not mean you could load the circuit with 100 ohms! You may meet this requirement by design.) You very likely need another opamp to do this. It is probably best to use it as a differential amplifier, taking the difference in potential between the two collectors of the sine converter. This reduces distortion and saves a capacitor. As a difference amplifier is a little harder to design, I will reserve points on the lab grade specifically for doing this successfully. In demonstrating your circuit to the TA, you must show reasonably distortion-free sine wave generation from 100 Hz to 10 kHz. Distortion must be reduced by proper selection of passive components in the triangle wave oscillator. To establish a quantitative measure of the distortion of the sine wave, use an oscilloscope to capture the signal when your generator frequency is about 1 kHz. Use a sampling rate of at least 100 kHz and try to adjust for as nearly ten cycles of the waveform on screen as practicable. Fill the vertical scale as much as possible without clipping. Use Excel to calculate the FFT and from the peaks in that transform calculate the ratios of the second through fourth harmonics to the fundamental. To meet the requirements of the lab, the amplitudes of the second and third harmonics must be at least 23 DB below the fundamental. Also capture the square and triangle outputs of your circuit at 1 KHz.

In your report, overlay them with the sine wave data all on the same time axis. As in lab 1, the TA will either initial a printout of your waveforms or give you an electronic signature to include on your graph when you demonstrate your triangle and square wave outputs to him. In the section of your report that has the tabulation of measured and designed values, please include at least: 1. Amplitudes of all waveshapes at 100 Hz, 1 kHz, and 10 KHz. 2. Distortion of the sine wave -- FFT printout and the derived ratio of the second and third harmonics to the fundamental amplitude. Make your FFT printout have a DB scale and normalize so that the fundamental is at 0 DB. 3. Waveshapes of all outputs at 1 KHz overlaid on the same time axis. 4. Maximum and minimum frequencies. 5. Quiescent values of the voltages in the sine converter 6. DC or mean value of the sinusoidal output -- i.e. is it really zero mean? Hints: 1. Bypassing the power supplies with small ceramic capacitors on the breadboard will help avoid spurious oscillations. 2. Keep the bias currents in the CA3086 transistors below 1mA for best results. 3. One technique for realizing a variable time-constant integrator is shown below:

Variable Time Constant Integrator

Function Generator Block Diagram: the Schmitt trigger and integrator form a square and triangle generator. The waveshaping circuit uses a differential pair with current source biasing and an emitter resistor. (See attached article.) You should have an opamp buffer in that circuit to minimize distortion and lower the output impedance.

AIM: Design a square wave generator and study its performance using 741 Op-Amp EQUIPMENTS REQUIRED:

COMPONENTS REQUIRED: Resistors, Capacitors, Op-Amp IC 741, Connecting wires and CRO probes. THEORY: Square Wave Generator: A simple op-amp square wave generator is shown in fig. Also called a free running oscillator, the principal of generation of square wave output is to force an opamp to operate in the saturation region. In fig. (a) Fraction _ = R2/ (R1 + R2) of the output is fed back to the (+) input terminal. Thus the reference voltage Vref is _Vo and may take values as + _Vsat or - _Vsat. The output is also fed back to the (-) input terminal after integrating by means of a low-passs RC combination. Whenever input at the (-) input terminal just exceeds Vref, switching takes place resulting in a square wave output. In astable multivibrator, both the states are quasi stable. Consider an instant of time when the output is at +Vsat. The capacitor now starts charging towards +Vsat through resistance R.The voltage at the (+) input terminal is held at + _Vsat by R1 & R2 combination. This condition continues as 7

the charge on C rises, until it has just exceeded + _Vsat, the reference voltage. When the voltage at the (-) input terminal becomes just greater than this reference voltage, the output is driven to Vsat. At this instant, the voltage on the capacitor is + _Vsat. It begins to discharge through R, that is, charge toward Vsat. When the output voltage switches to Vsat, the capacitor charges more & more negatively until its voltage just exceeds _Vsat. The output switches back to +Vsat. The frequency is determined by the time it takes the capacitor to charge from _Vsat to + _Vsat and vice versa. CIRCUIT DIAGRAM:

PROCEDURE: 1. Rig up the circuit as shown in the Fig.on the breadboard. 2. Observe the output on CRO. 3. Calculate the amplitude & frequency of the output. 4. Plot the outputs waveforms on the graph paper. 5.Compare the theoretical frequency with the practical frequency of the output. OBSERVATION TABLE:

CONCLUSION: The theoretical and practical frequency of the outputs is asand the output is plotted on the graph paper. REFERENCE: 1. Op Amps & Linear Integrated circuits by Ramakant Gayakwad, Chapter 7, pp-301305 9

QUESTIONS: Q.1 What is the other name of square wave generator? Q.2.What is the maximum output voltage values? Q.3 What is the operating frequency of square wave generator? Q.4 Under what condition the fo=1/2 _RC?

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Ex. No. 2a: CHARACTERISTICS OF CE CONFIGURATION USING BJT AIM: To plot the transistor characteristics of CE configuration.

THEORY: A BJT is a three terminal two junction semiconductor device in which the conduction is due to both the charge carrier. Hence it is a bipolar device and it amplifier the sine waveform as they are transferred from input to output. BJT is classified into two types NPN or PNP. A NPN transistor consists of two N types in between which a layer of P is sandwiched. The transistor consists of three terminal emitter, collector and base. The emitter layer is the source of the charge carriers and it is heartily doped with a moderate cross sectional area. The collector collects the charge carries and hence moderate doping and large cross sectional area. The base region acts a path for the movement of the charge carriers. In order to reduce the recombination of holes and electrons the base region is lightly doped and is of hollow cross sectional area. Normally the transistor operates with the EB junction forward biased. In transistor, the current is same in both junctions, which indicates that there is a transfer of resistance between the two junctions. One to this fact the transistor is known as transfer resistance of transistor. PROCEDURE: INPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set VCE ,vary VBE in regular interval of steps and note down the corresponding IB reading. Repeat the above procedure for different values of VCE. 3. Plot the graph: VBE Vs IB for a constant VCE.

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OUTPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC reading. Repeat the above procedure for different values of IB. 3. Plot the graph: VCE Vs IC for a constant IB. PIN DIAGRAM:

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RESULT: The transistor characteristics of a Common Emitter (CE) configuration were plotted and uses studied. hie = hfe = hre = hoe =

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Ex.No.2b: CHARACTERISTICS OF CB CONFIGURATION USING BJT AIM: To plot the transistor characteristics of CB configuration.

THEORY: In this configuration the base is made common to both the input and out. The emitter is given the input and the output is taken across the collector. The current gain of this configuration is less than unity. The voltage gain of CB configuration is high. Due to the high voltage gain, the power gain is also high. In CB configuration, Base is common to both input and output. In CB configuration the input characteristics relate IE and VEB for a constant VCB. Initially let VCB = 0 then the input junction is equivalent to a forward biased diode and the characteristics resembles that of a diode. Where VCB = +VI (volts) due to early effect IE increases and so the characteristics shifts to the left. The output characteristics relate IC and VCB for a constant IE. Initially IC increases and then it levels for a value IC = IE. When IE is increased IC also increases. proportionality. Though increase in VCB causes an increase in since is a fraction, it is negligible , and so IC remains a constant for all values of VCB once it levels off.

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PROCEDURE: INPUT CHARACTERISTICS: It is the curve between emitter current IE and emitterbase voltage VBE at constant collector-base voltage VCB. 1. Connect the circuit as per the circuit diagram. 2. Set VCE=5V, vary VBE in steps of 0.1V and note down the corresponding IB. Repeat the above procedure for 10V, 15V. 3. Plot the graph VBE Vs IB for a constant VCE. 4. Find the h parameters. OUTPUT CHARACTERISTICS: It is the curve between collector current IC and collector-base voltage VCB at constant emitter current IE. 1. Connect the circuit as per the circuit diagram. 2. Set IB=20A, vary VCE in steps of 1V and note down the corresponding IC. Repeat the above procedure for 40A, 80A, etc. 3. Plot the graph VCE Vs IC for a constant IB. 4. Find the h parameters

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%age ERROR : from data sheet find values of hic, hrc , hfc, hoc and compare these values with practically obtained values to find %age error RESULT:The transistor characteristics of a Common Base (CB) configuration were plotted and uses studied. 18

Ex.No.2c: CHARACTERISTICS OF CC CONFIGURATION USING BJT AIM: To plot the transistor characteristics of CE configuration.

THEORY: A BJT is a three terminal two junction semiconductor device in which the conduction is due to both the charge carrier. Hence it is a bipolar device and it amplifier the sine waveform as they are transferred from input to output. BJT is classified into two types NPN or PNP. A NPN transistor consists of two N types in between which a layer of P is sandwiched. The transistor consists of three terminal emitter, collector and base. The emitter layer is the source of the charge carriers and it is heartily doped with a moderate cross sectional area. The collector collects the charge carries and hence moderate doping and large cross sectional area. The base region acts a path for the movement of the charge carriers. In order to reduce the recombination of holes and electrons the base region is lightly doped and is of hollow cross sectional area. Normally the transistor operates with the EB junction forward biased. In transistor, the current is same in both junctions, which indicates that there is a transfer of resistance between the two junctions. One to this fact the transistor is known as transfer resistance of transistor. PIN DIAGRAM:

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INPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set VCE, vary VBE in regular interval of steps and note down the corresponding IB reading. Repeat the above procedure for different values of VCE. 3. Plot the graph: VBC Vs IB for a constant VCE. OUTPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC reading. Repeat the above procedure for different values of IB. 3. Plot the graph: VCE Vs IC for a constant IB.

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Percentage ERROR: From data sheet find values of hie, hic , hfc, hoe and compare these values with practically obtained values to find %age error RESULT: The transistor characteristics of a Common Emitter (CC) configuration were plotted.

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Experiment 3a: ASTABLE MULTIVIBRATOR AIM: To study and implement IC 555 as Astable Multivibrator. COMPONENTS REQUIRED: = = 10 K, C= 0.1 and 0.01F, R= 150k, LED red, IC 555

Theory : - In this lab the 555 Timer is examined in detail along with its uses. This timer uses a maze of diodes, transistors, and resistors and for this reason a more simplified diagram of the 555 Timer is used. Below is the typical monostable 555 Timer IC:

This circuit is dependent on RA, RB, and C. Below is the schematic for the circuit we built:

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Circuit Diagram:-

Design: - The following formula was used to find the expected frequency: f = 1/(.693*C*( )) , f=481 Hz The following are actual measurements taken from the lab: f = 526 Hz The result is very similar to the expected value. The 555 Timer has an internal voltage divider comprising of three 5 k resistors. In our case our supply voltage is 12V which results in a upper voltage threshold of 8V and a lower threshold of 4V. The measurements I obtained from the lab were very similar with a lower threshold of 3.8 V and a higher threshold of 8.1V. The next part of this section included changing both 10 k resistors to variable 1 M potentiometers. We adjusted the frequency to range from 2 to 5 Hz and observed the LED slowly flashing on and off. We varied the value of the potentiometers to find the smallest 24

and the largest frequency value. We obtained the following results: Largest f = 60.1 kHz with RA = 100 and RB = 70 Smallest f = 4.8 Hz with RA = 1 M and RB = 1 M Next we changed VC to +5 V and the frequency doesnt change as the voltage changes, because the threshold voltages change proportionally to the supple voltage, therefore the capacitor has to charge up less. Procedure:1. Make the circuit diagram as shown in above figure on bread board. 2. Give the power supply from dc battery source and see the output. 3. Red colored LED will start glow alternatively depending upon the time constant RC. 4. Observe the output on CRO as well. 5. Now change the time constant by changing the value of RA, RB and C. 6. Measure change in frequency in the output waveform (as well in LED). Observation Table with errors in measurement S.no. Measured Time period Tm+2% Tm-2% Average Tmavg= (Tmmax+Tm min)/2

1. 2. 3. 4. 5.

Calculations using tolerance in component values: f = 1/(.693*C*( )) RA 10%, RB 10%, C 5% Find min and max values of using new values of components Find average 1/ Percentage error: ((TM -Tavg)/Tavg) x 100

, and

Scope of Result : At the output square waveforms will be generated and observed.

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Exp 3b: Monostable Multivibrator AIM: To study and implement IC 555 as Monostable Multivibrator. Components Required: RA=RB= 10 K, C= 0.1 and 0.01F, R= 150k, LED red, IC 555 THEORY: In this lab the 555 Timer is examined in detail along with its uses. This timer uses a maze of diodes, transistors, and resistors and for this reason a more simplified diagram of the 555 Timer is used. Below is the typical monostable 555 Timer IC:

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Internal diagram of IC 555

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CIRCUIT DIAGRAMS: The schematic below represents a mono-stable multi-vibrator:

When the circuit was turned on, the LED was initially off. It was low because the trigger voltage was high due to the pull up resistor, and the voltage across the capacitor at pin 6/7 was equal to zero. After pin 2, the trigger voltage, was grounded the LED turned on and the output went high. This is due to the fact that the mono stable MV was set off. By using an LED at the output of the Timer, we are able to see the output pulse. With the schematic from the lab manual, it is impossible to measure the duration of the pulse by manually triggering the 555 Timer IC. Using a pulse generator with an oscilloscope would be a preferred method. 28

DESIGN: Time delay can be calculated using the following equation: t= 1.1RC 6 t = 1.1(10x103 )(0.68x10 ) = .0748sec Manually finding the time would be much easier if a larger resistor was used. We tested the operation of the RESET by triggering the input first and then grounding pin 4. When the Reset is grounded the output goes immediately to zero, in other words, the LED turns off before the completion of the timing cycle and the flip flop is reset. PROCEDURE: 1. Make the circuit diagram as shown in above figure on bread board. 2. Give the power supply from dc batter source and see the output. 3. Red color LED will start glow alternatively depending upon the time constant RC. 4. Observe the output on CRO as well. 5. Now change the time constant by changing the value of RA, RB and C. 6. Measure change in frequency in the output waveform (in LED as well). Observation Table with measurement ERRORS Sr no 1 2 3 4 5 6 R C Measured Tm+2% Tm-2% time of pulse Tm Average Tm avg= ( Tm Max+Tm min)/2

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Value of Tm ranges from

Calculations using tolerance in component values: Calculated pulse duration t = 1.1RC R 10%,, C 5% Find min and max values of t using new values of R and C Find average Tavg = (t min+t max)/2 Percentage error: = ( (T M -Tavg )/Tavg ) * 100% Result :

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Experiment4: Half/Full adder. Aim: Realization of Half/Full adder and Half/Full Subtractors using logic gates. Apparatus Required: - IC 7486, IC 7432, IC 7408, IC 7400, etc. Procedure: 1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Switch on VCC and apply various combinations of input according to the truth table. 4. Note down the output readings for half/full adder and half/full subtractor sum/difference and the carry/borrow bit for different combinations of inputs. a. Half Adder Truth Table

Half Adder using NAND gates only:-

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Full Adder using basic gates:-

Full Adder using NAND gates only:-

Full Adder Truth Table:

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EXERCISE:
1. What is the need of arithmetic circuits?
Ans :

2. Is it possible to construct the half adder using only NAND gate? Why?
Ans :

3. Is it possible to construct the full adder using only NOR gate?

Ans : 4. What is the difference between half adder and full adder? Ans :

5. What are combinational circuits?

Ans :

6.What are sequential circuit?

Ans :

7. Give difference between sequential circuits and combinational circuits?

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Experiment 5: AIM: VERIFICATION OF NETWORK THEOREMS OBJECTIVE: Verification of i) Thevenin Theorem. ii) Superposition Theorem. A) THEVENINS THEOREM CIRCUIT DIAGRAM:

Fig-1. CIRCUIT DIAGRAM FOR VERIFICATION OF THEVENINS THEOREM PROCEDURE: 1. Keep all the rheostats close to their maximum resistance values. 2. Close the switch S to position aa and S to cc. Observe the load (26 ohm
1 2

rheostat) current (I ) and terminal voltage (V ) readings. Then the value of load
L L

resistance R =V /I .
L L L

3. Disconnect the load by opening the switch S and read the open circuit voltage (or
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Thevenin equivalent voltage) V .

TH

4. Next, to compute the Thevenin equivalent resistance (R ) of the network as seen

TH

from the load terminals: i) Replace the 220V source by a short by closing S1 to bb. ii) Apply 110V at the output terminals by closingS2 to dd. Read the Voltmeter (V) and ammeter (I) and get R = V/I. 5. Now compute the load current applying Thevenins theorem as I =V / (R +R ).
L TH TH L TH

6. Compare the above computed load current with its observed value in step (2) and verify the Theorem. 7. Adjust all the rheostats to new settings and repeat from step (2) to step (6) for at least six sets of readings without exceeding rated current in any element. 34

DISCUSSION: (i) Why are you applying 110 V instead of 220 V while finding R ?
TH

(ii) Can you suggest an alternative procedure for the determination of R ?

TH

(iii) Is there any restriction for choice of circuit elements? (iv) What type of ammeter and voltmeter (MC or MI) will you use and why? B) SUPERPOSITION THEOREM CIRCUIT DIAGRAM:

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PROCEDURE: i) Connect the circuit as shown in the diagram, keeping the switches open and resistances at their maximum positions. ii) Set S to position aa and S to position cc respectively which means both the
1 2

sources are energized. Note down the currents I , I and I from the ammeter. A ,
1 2 3 1

A and A . iii) Set S on position aa and S on position dd respectively, i.e. only 220 V source is energized and the terminals of S are shorted. Note down the current I , I and I
2 1 2 1 2 1 2 3 1 2 2 3

iv) Set S to position bb and S to position cc respectively and note I , I and I . [Please note the polarity of the currents] v) Compare I , I and I with (I +I ), (I +I ) and (I +I ) taking care of the signs properly
1 2 3 1 1 2 2 3 3

3.

to verify the theorem. vi) Repeat this from step (ii) to (v) for three different sets of resistance value of the three rheostats. vii) Tabulate the results as shown. Table II Superposition Theorem

DISCUSSION: i) What type of ammeters (MI or MC) will you choose? ii) While considering the effect of a single source, the other source is short circuited why? How far is it justified? iii) Why are you noting the direction of the deflection of the meter? iv) If the rheostats are replaced by three incandescent lamps, can you verify the theorem? 36

Experiment No: 6 AIM : Seven segment LED display APPARATUS REQUIRED :

Seven-Segment LEDs The seven-segment LED display has four individual digits, each with a decimal point. Each of the seven segments (and the decimal point) in a given digit contains an individual LED. When a suitable voltage is applied to a given segment LED, current flows through and illuminates that segment LED. By choosing which segments to illuminate, any of the nine digits can be shown.

Pin connections:

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1. A, B, C, D are the binary inputs. 2. a, b, c, d, e, f, g, h are the driver signals to the display elements. 3. LT is the lamp test control, turns all segment On, active Low 4. BL blanks all segments when activated, active LOW 5. LE is the latch enable control. Truth table The function of a BCD to 7-segment decoder is to convert the logic states at the outputs of a BCD counter such as the 4510 into a form which will drive a 7-segment display. The display shows the decimal numbers 0-9 and is easily understood. The individual segments making up a 7-segment display are identified by letters as follows:

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There are two important types of 7-segment LED display. In a common cathode display, the cathodes of all the LEDs are joined together and the individual segments are illuminated by HIGH voltages.

In a common anode display, the anodes of all the LEDs are joined together and the individual segments are illuminated by connecting to a LOW voltage.

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When the 4511 is set up correctly, the outputs follow this truth table:

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Experiment 7: 8-bit Digital-to-Analog Converter Overview: This article aims to introduce to beginners and intermediate readers a simple solution to build a digital to analog converter, based on the famous r/2r resistors network. This article also discuss a problem encountered by many beginners while trying to build their own DAC, and proposes some very simple solutions to that problem.

Through this article, I am going to explain how to build an 8-bit digital to analog converter with parallel input. If you don't know what this means, well its simply a circuit that will take as input a digital 8-bit number from 0 (00000000) to 255 (11111111), and output the relative value on a scale from 0 to 5v. The maths that describe this process is very simple, an 8 bit converter will divide the 5 volts into 255 steps, each step having a value of: 5/255 = 0.019 V Then the output voltage for the converter should be equal to the binary input multiplied by the step value, e.g. for an input of 129 (1000 0001 in binary) the output voltage should be: 129 X 0.019 = 2.451V Here is a simplified functional diagram of an 8-bit DAC. Some vocabulary DAC: Digital to Analog converter D0, D1, D..: Data lines Analog: Continuous electrical signals Digital: Method of representing information using "1" and "0" (usually 5v and 0V) LSB: Less significant bit. MSB: Most significant bit.

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R/2R LADDER NETWORK: The digital data entering thought the 8 lines (D0 to D7) are going to be converted to an equivalent analog voltage (V out) by the mean of the R/2R resistor network. Actually a lot of commercial Digital to Analog converter ICs are based on this same principle. The R/2R network is build by a set of resistors of 2 values, with one of them double the other (example 10K and 20K), in on of my circuits I used 1M ohm and 470K Follow the colors on the schematic and on the ohm resistors, which is description text respectively, it can help! quite near to the R/2R ratio, and this small difference didn't cause any detectable errors in most applications. However, if you want to build a very precise DAC, be precise when choosing the values of the resistors that will exactly match the R/2R ratio. Note that you can build a DAC with any number of bits you want, simply by enlarging the resistor network, by adding more R/2R branches (like the one shaded in green), BUT you must keep the 2R resistance connected to ground (shaded in light red) Going through the mathematical proof for the operation of this converter can be a pain for some of us, and I am only intending to keep things simple. Now, in order to use this Resistor Network (also called R/2R Ladder) for real applications, you will have to build a very simple voltage buffer circuit, which will be explained in the next section. CIRCUIT DIAGRAM:

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Follow the colors on the schematic and on the description text respectively, it can help! All the components are labeled on the circuit, so i'll start directly to explain how it works. to simplify this task, i'll split the circuit into 2 main stages: the Digital to analog converter and the Voltage buffer stage. Stage 1: the Digital to analog converter (The R/2R network) This part have been explained in detail in the previous section, its purpose is to create the voltage V1 which is equivalent to the weight of the binary number on the lines (D0 to D7). Now that this is a resistor network, if we apply any load on the output of the first stage, this load will be considered as an additional resistor in the network, and thus will disturb the network which will no longer provide the correct & desired output voltage. Therefore, to overcome this problem, we need a voltage buffer, here is where the next stage comes... Stage 2: the voltage buffer This stage will isolate the point V1 from the final output V2, while always keeping the voltage V2 at the exact same value of V1. This is what we call a voltage buffer. for the voltage buffer we use an opamp with the output connected to the inverting input (this special configuration of the Op Amp is also called Voltage Follower). The most important things to note are: 1 No current (almost 0A) will flow from the point V1 into the opamp, so we wont be disturbing the resistor network configuration 2 V2 will always equal V1 (theoretically, see the rest of this document) 3 The current going out from the point V2 to any other stage is sourced from from the power supply of the OpAmp.

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A quick look on those 2 graphs can be sufficient to understand the problem: the output of the op-amp is not linear on the full 0-to-Vcc scale. actually an OpAmp, depending on its type, will deliver a maximum voltage of (Vcc - 0.5V), where Vcc is the supply voltage of the OpAmp. So, in our application, the OpAmp will only deliver 4.5V even if theoretically it should deliver 5V. You may think this caused by the resistor network, but it's not! this is a limitation in the op-amp itself. Lets get a little deeper into the problem, the actual output curve in red should be linear, but actually it begins loosing its linearity beginning from 3.9 volt. (Again this depends on the type of OpAmp, those results a based on my own tests on a LM350 OpAmp) The red 'Error zone' is where the output of the DAC no longer math the relative binary input. This is the error we will be trying to overcome in the next part, through 2 very simple solutions.

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Solution 1 :

The first solutions - shown in the red shading - is to increase the supply voltage of the Op-Amp, as shown in the schematic. this will totally solve the problem, and, whether you are supplying 6.5 volts or more, you will get neat linear output from 0V to 5V. Solution 2 :

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Experiment 8: NON LINEAR WAVE SHAPPING-CLIPPERS Aim: To obtain the output and transfer characteristics of various diode clipper circuits. Apparatus required: Name of the Component/Equipment Resistors Diode CRO Function generator DC Regulated power supply Theory: The basic action of a clipper circuit is to remove certain portions of the waveform, above or below certain levels as per the requirements. Thus the circuits which are used to clip off unwanted portion of the waveform, without distorting the remaining part of the waveform are called clipper circuits or Clippers. The half wave rectifier is the best and simplest type of clipper circuit which clips off the positive/negative portion of the input signal. The clipper circuits are also called limiters or slicers. Procedure: 1.Connect the circuit as per circuit diagram shown in Fig.1 Obtain a sine wave of constant amplitude 8 V p-p from function generator and apply as input to the circuit. 2.Observe the output waveform and note down the amplitude at which clipping occurs. 3.Draw the observed output waveforms. 4. To obtain the transfer characteristics apply dc voltage at input terminals and vary the voltage insteps of 1V up to the voltage level more than the reference voltage and note down the corresponding voltages at the output. 5. Plot the transfer characteristics between output and input voltages. 6. Repeat the steps 1 to 5 for all other circuits. 47 Specifications Quantity

1K IN4007 20MHZ 1MHZ 0-30V, 1A

1 1 1 1 1

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EXPERIMENT NO 9: Aim: To perform sampling and explain the concept of aliasing using MATLAB. ALGORITHM STEPS:

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DIFFERENTIAL AMPLIFIERS A differential amplifier has two possible inputs and two possible outputs. This arrangement means that the differential amplifier can be used in a variety of ways. Before examining the three basic configurations that are possible with a differential amplifier, you need to be familiar with the basic circuitry of a differential amplifier. BASIC DIFFERENTIAL AMPLIFIER CIRCUIT Before you are shown the operation of a differential amplifier, you will be shown how a simpler circuit works. This simpler circuit, known as the DIFFERENCE AMPLIFIER, has one thing in common with the differential amplifier: It operates on the difference between two inputs. However, the difference amplifier has only one output while the differential amplifier can have two outputs. By now, you should be familiar with some amplifier circuits, which should give you an idea of what a difference amplifier is like. In NEETS, Module 7, you were shown the basic configurations for transistor amplifiers. Figure 3-1 shows two of these configurations: the common emitter and the common base. In view (A) of figure 3-1 a common-emitter amplifier is shown. The output signal is an amplified version of the input signal and is 180 degrees out of phase with the input signal. View (B) is a common-base amplifier. In this circuit the output signal is an amplified version of the input signal and is in phase with the input signal. In both of these circuits, the output signal is controlled by the base-to-emitter bias. As this bias changes (because of the input signal) the current through the transistor changes. This causes the output signal developed across the collector load (R2) to change. None of this information is new it is just a review of what you have already been shown regarding transistor amplifiers.

NOTE: Bias arrangements for the following explanations will be termed base-to-emitter. In other publications you will see the term emitter-to-base used to describe the same bias arrangement. THE TWO-INPUT, SINGLE-OUTPUT, DIFFERENCE AMPLIFIER If you combine the common-base and common-emitter configurations into a single transistor amplifier, you will have a circuit like the one shown in figure 3-2. This circuit is the two-input, single-output, difference amplifier.

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When the input signal developed by R1 goes positive, the current through Q1 increases. This increased current causes a positive-going signal at the top of R3. This signal is felt on the emitter of Q2.Since the base of Q2 is grounded, the current through Q2 decreases with a positive-going signal on the emitter. This decreased current causes less voltage drop across R4. Therefore, the voltage at the bottom ofR4 increases and a positive-going signal is felt at the output. When the input signal developed by R1 goes negative, the current through Q1 decreases. This decreased current causes a negativegoing signal at the top of R3. This signal is felt on the emitter of Q2.When the emitter of Q2 goes negative, the current through Q2 increases. This increased current causes more of a voltage drop across R4. Therefore, the voltage at the bottom of R4 decreases and a negative-going signal is felt at the output. This single-input, single-output, differential amplifier is very similar to a single-transistor amplifier as far as input and output signals are concerned. This use of a differential amplifier does provide amplification of a.c. or D.C. signals but does not take full advantage of the characteristics of a differential amplifier. SINGLE-INPUT, DIFFERENTIAL-OUTPUT, DIFFERENTIAL AMPLIFIER In chapter one of this module you were shown several phase splitters. You should remember that a phase splitter provides two outputs from a single input. These two outputs are 180 degrees out of phase with each other. The single-input, differential64

output, differential amplifier will do the same thing. Figure 3-8 shows a differential amplifier with one input (the base of Q1) and two outputs (the collectors of Q1 and Q2). One output is in phase with the input signal, and the other output is 180 degrees out of phase with the input signal. The outputs are differential outputs.

This circuits operation is the same as for the single-input, single-output differential amplifier just described. However, another output is obtained from the bottom of R2. As the input signal goes positive, thus causing increased current through Q1, R2 has a greater voltage drop. The output signal at the bottom of R2 therefore is negative going. A negative-going input signal will decrease current and reverse the polarities of both output signals. Now you see how a differential amplifier can produce two amplified, differential output signals from a single-input signal. One further point of interest about this configuration is that if a combined output signal is taken between outputs number one and two, this single output will be twice the amplitude of the individual outputs. In other words, you can double the gain of the differential amplifier (single output) by taking the output signal between the two output terminals. This single-output signal will be in phase with the input signal. This is shown by the phantom signal above R5 (the phantom resistor connected between outputs number one and two would be used to develop this signal). DIFFERENTIAL-INPUT, DIFFERENTIAL-OUTPUT, DIFFERENTIAL AMPLIFIER When a differential amplifier is connected with a differential input and a differential output, the full potential of the circuit is used. Figure 3-9 shows a differential amplifier with this type of configuration (differential-input, differential-output).

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Normally, this configuration uses two input signals that are 180 degrees out of phase. This causes the difference (differential) signal to be twice as large as either input alone. (This is just like the two-input, single-output difference amplifier with input signals that are 180 degrees out of phase.)Output number one is a signal that is in phase with input number two, and output number two is a signal that is in phase with input number one. The amplitude of each output signal is the input signal multiplied by the gain of the amplifier. With 180-degree-out-of-phase input signals, each output signal is greater in amplitude than either input signal by a factor of the gain of the amplifier. When an output signal is taken between the two output terminals of the amplifier (as shown by the phantom connections, resistor, and signal), the combined output signal is twice as great in amplitude as either signal at output number one or output number two. (This is because output number one and output number two are 180 degrees out of phase with each other.) When the input signals are 180 degrees out of phase, the amplitude of the combined output signal is equal to the amplitude of one input signal multiplied by two times the gain of the amplifier. When the input signals are not 180 degrees out of phase, the combined output signal taken across output one and output two is similar to the output that you were shown for the two-input, single-output, difference amplifier. The differential amplifier can have two outputs (180 degrees out of phase with each other), or the outputs can be combined as shown in figure 3-9.

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EXPERIMENT NO 11 Aim: To plot frequency response of LPF, HPF, and BPF in MATLAB. ALGORITHM STEPS:

Low pass filter Program code: format long rp=input('enter the passband ripple'); rs=input('enter the stop band ripple'); wp=input('enter the passband frequency'); ws=input('enter the stopband frequency'); fs=input('enter the sampling frequency'); w1=2*wp/fs;w2=2*ws/fs; [n,wn]=buttord(w1,w2,rp,rs,'s'); [z,p,k]=butter(n,wn); [b,a]=zp2tf(z,p,k); [b,a]=butter(n,wn,'s'); 68

w=0:.01:pi; [h,om]=freqs(b,a,w); m=20*log10(abs(h)); plot(om/pi,m); ylabel('gain in dB-->'); xlabel('(a)Normalised frequency-->');

Result: enter the pass band ripple 0.15 enter the stop band ripple 60 enter the pass band frequency 1500 enter the stop band frequency 3000 enter the sampling frequency 7000

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Ex.No.12 CHARACTERISTICS OF JUNCTION FIELD EFFECT TRANSISTOR AIM: To Plot the characteristics of given FET & determine rd, gm, IDSS,VP. ,

THEORY: FET is a voltage operated device. It has got 3 terminals. They are Source, Drain & Gate. When the gate is biased negative with respect to the source, the pn junctions are reverse biased & depletion regions are formed. The channel is more lightly doped than the p type gate, so the depletion regions penetrate deeply in to the channel. The result is that the channel is narrowed, its resistance is increased, & ID is reduced. When the negative bias voltage is further increased, the depletion regions meet at the center & ID is cutoff completely. PROCEDURE: DRAIN CHARACTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set the gate voltage VGS = 0V. 3. Vary VDS in steps of 1 V & note down the corresponding ID. 4. Repeat the same procedure for VGS = -1V. 5. Plot the graph VDS Vs ID for constant VGS. OBSERVATIONS 1. d.c (static) drain resistance, rD = VDS/ID. 2. a.c (dynamic) drain resistance, rd = VDS/ ID. 3. Open source impedance, YOS = 1/ rd.

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TRANSFER CHARACTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set the drain voltage VDS = 5 V. 3. Vary the gate voltage VGS in steps of 1V & note down the corresponding ID. 4. Repeat the same procedure for VDS = 10V. 5. Plot the graph VGS Vs ID for constant VDS. FET PARAMETER CALCULATION:

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Percentage ERROR : from data sheet find values of gmo and IDSS to get values of Rd gm IDSS VP using formulas and compare these values with practically obtained values to find Percentage error

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Experiment 13: 4-Bit Synchronous Binary Counter AIM: To verify the functionality of Synchronous/Asynchronous Up/Down decade counter

Figure: Four-bit synchronous binary counter, timing diagram Synchronous Decade Counters: Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9 and then recycles to 0 again. This is done by forcing the 1010 state back to the0000 state. This so called truncated sequence can be constructed by the following circuit.

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From the sequence in the Figure 3.5b, we notice that: Q0 toggles on each clock pulse. Q1 changes on the next clock pulse each time Q0=1 and Q3=0. Q2 changes on the next clock pulse each time Q0=Q1=1. Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1(count 7), or

then Q0=1 and Q3=1 (count 9). Flip-flop 2 (Q2) changes on the next clock pulse each time both Q0=1 and Q1=1. Thus we must have J 2 = K 2 = Q 0 Q 1 F 80

Flip-flop 3 (Q3) changes to the opposite state on the next clock pulse each time Q0=1, Q1=1, and Q2=1 (state 7), or when Q0=1 and Q3=1 (state 9). Thus we must have J3 =K3 =Q0 Q1 Q2 +Q0 Q3 These characteristics are implemented with the AND/OR logic connected as shown in the logic diagram (Figure 3.5b). Up-Down Synchronous Counters A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown in Figure 3.6. Similar to an asynchronous up-down counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence.

An examination of the sequence table shows: for both the UP and DOWN sequences, Q0 toggles on each clock pulse. for the UP sequence, Q1 changes state on the next clock pulse when Q0=1. for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0. 81

 for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1. for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0. These characteristics are implemented with the AND, OR & NOT logic connected as shown in the Figure 3.6 Example: 4-bit synchronous up-down counter

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Asynchronous Decade Counters The binary counters previously introduced have two to the power n states. But counters with states less than this number are also possible. They are designed to have the number of states in their sequences, which are called truncated sequences. These sequences are achieved by forcing the counter to recycle before going through all of its normal states. A common modulus for counters with truncated sequences is ten. A counter with ten states in its sequence is called a decade counter. The circuit below is an implementation of a decade counter. Figure 1.6: Asynchronous decade counter, timing diagram.

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Figure 1.6: Asynchronous decade counter, timing diagram Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that only Q1 and Q3 are used to decode the count of ten. This is called partial decoding, as none of the other states (zero to nine) have both Q1 and Q3 HIGH at the same time.

The sequence of the decade counter is shown in the table below:

Recycles 1 1 0 0 (normal next state) Glitch: Notice that there is a glitch on the Q1 waveform. The reason for this glitch is that Q1 must first go HIGH before the count of ten can be decoded. Not until several nanoseconds after the counter goes to the count of ten does the output of the decoding gate go LOW (both inputs are HIGH). Therefore, the counter is in the 1010 state for a short time before it is reset to00 00, thus producing the glitch on Q1 and the resulting glitch on the CLR line that resets the counter.

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