PIC18V2

202 PRC
PIC18 Peripheral Configuration and MPLAB-C18 Programming Techniques
Objectives
When you finish this class, you will understand PIC18:
Architecture Interrupts Interrupt Handlers Basic Peripherals Peripheral Configuration Programming in C using MPLAB C18
2008 Microchip Technology Incorporated. All Rights Reserved.
MCU 2121
Slide 2
Agenda
Architecture Overview
Programmers Model
Program Memory Stack Data Memory
Instruction Set Overview
PIC18 Interrupts
MCU 2121
Slide 3
Agenda (continued)
Development Tools
MPLAB IDE, ICD2, PICDEM2 Plus MPLAB C18 C Language Extensions
Program Memory Variables SFR Access Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support
MCU 2121
Slide 4
Agenda (continued)
Peripherals and Hands-On Exercises
I/O Ports & External Interrupts Analog: Comparators, VREF, and ADC Timers CCP (Capture, Compare & PWM)
MCU 2121
Slide 5
Agenda (continued)
MSSP (I2C, SPI and Microwire) USART
Oscillators and Power Saving Modes Special features

PLVD, PBOR, ICSP, WDT, Resets
MCU 2121
Slide 6
PIC18 Architecture
Overview
Harvard Architecture
8-bit microcontroller 16-bit Instruction width Data Transfer Mechanism between PM and DM
8 bit window
Program Memory (Up to 2MB)
PIC18
Data Memory
16
RISC CPU
(Up to 4KB)
MCU 2121
Slide 8
Program Memory Organization

21-Bit Program Counter
2MB Address Space
PC<0> always = 0
16-bit Program Memory is Byte Addressable
Reset Vector @ 0x00 Interrupt Vectors

High Priority @ 0x08 Low Priority @ 0x18
MCU 2121
Slide 9
Return Address Stack

H/W Stack Memory 31 Levels
Used by interrupts, CALL, RCALL, RETURN, RETLW and RETFIE instructions
20 0
Top of Stack Registers:

4 0 20 0
Stack Pointer:
RESET State: No RAM at level 0
Stack grows up
No rollover back to level 0!

2008 Microchip Technology Incorporated. All Rights Reserved. MCU 2121 Slide 10
STKPTR Register
R/C-0 bit 7 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
bit 7
STKFUL: Stack Full Flag Bit 1 = Stack full or overflow occurred 0 = Reset or cleared by user software STKUNF: Stack Underflow Flag Bit 1 = Stack underflow occurred 0 = Reset or cleared by user software SP4:SP0: Stack Pointer Bits
MCU 2121 Slide 11
bit 6
bit 4-0
Programmers Model
MCU 2121
Slide 12
Table Pointer
Program Memory Data Access (R/W)
Program memory (16 bits) TBLPTR 21-bit 21Address TABLAT Data 055h TBLPTRU TBLPTRH TBLPTRL TABLAT Register file (8 bits)
High byte
Low byte
TBLPTR registers are used to address program memory TBLRD instruction is used to read a byte
2 cycles not incl. TBLPTR set-up Data is latched in TABLAT register
TBLWT instruction is used to load write buffer

EECON1 register controls actual write cycle Erase block size 32 or 64 bytes (see data sheet) 6 ms to update one row of 64 bytes
See section 6.5 of the datasheet for an example of the code sequence
Table Pointer
Assembly Operations
TBLRD/TBLWT *
no change to table pointer
TBLRD/TBLWT *+
auto post-increment of table pointer
TBLRD/TBLWT *auto post-decrement of table pointer
TBLRD/TBLWT +*
auto pre-increment of table pointer
MCU 2121
Slide 14
Data Memory Organization

000h 07Fh
Access RAM Access RAM Bank 0 GPR Bank 0 GPR Bank 1 Bank 1 GPR GPR
Data Memory up to 4k bytes Divided into 256 byte banks Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected BSR determines which bank is currently selected
PIC18F2520/4520 Register File Map
080h 0FFh 100h
1FFh 200h
Bank 2 Bank 2 GPR GPR

2FFh
Access Bank Access RAM Access RAM

00h 7Fh 80h FFh
D00h
Access SFR Access SFR Bank 13 Bank 13 GPR GPR 256 Bytes
DFFh E00h
Bank 14 Bank 14 GPR GPR

EFFh F00h F7Fh F80h FFFh
2008 Microchip Technology Incorporated. All Rights Reserved. MCU 2121
Bank 15 GPR Bank 15 GPR Access SFR Access SFR

Slide 15
PIC18 Instruction Set

Overview, Extended Mode

Data Move Instructions
Data memory to data memory Data memory to program memory (vice versa) Literal
Arithmetic, Logic, Shift Instructions Single Cycle 8 x 8 Multiply (100ns) Powerful Bit Manipulation
Single cycle bit set, clear or toggle Operate directly on all registers including I/O
Branching / Conditional Branching
MCU 2121
Slide 17

77 Standard Instructions
73 are single word 4 two-word MOVFF, MOVLF, CALL, GOTO
Most Instructions Are Single Cycle

4 two word instructions are two cycle 10 branches, 10 skip instructions are 1 or 2 cycle 8 table operation instructions are two cycle 3 returns are 2 cycle
Table Read/Write 8 Extended Instructions
MCU 2121
Slide 18
PIC18F: Extended Mode

Enable/Disable by XINST configuration bit Indexed Literal Offset Addressing mode and
Instruction ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK Zs, fd Zs, Zd k f, k k f, k k Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return
MCU 2121 Slide 19
Description
Extended Mode Advantage

C Compiler Optimized
Software Stack Pointer manipulation Dynamic allocation and de-allocation of software stack Manipulation of variables located in a software stack Direct Function pointer invocation
Result:
Reduced code size & execution time of Cbased programs
MCU 2121
Slide 20
MPLAB C18 C Language Extensions
MPLAB C18 Compiler

PIC18 only Targets ANSI:1989 standard Standard C functions Peripheral library support $495US One-time cost. Student Version ($free):
http://www.microchip.com/mplabc After 60 days:
Optimizations disabled Extended mode disabled
MCU 2121
Slide 22
C18 C Language Extensions

MCU 2121
Slide 23
Storage Qualifiers
rom near Program memory address < 64K ram In access bank
far
Anywhere in program Anywhere in memory data memory
NOTE: C18 default is far ram

rom Qualifier rom object stored in program memory Compiler inserts TBLRD and TBLWT
instructions to access Can be used on any data type Can be a pointer
16-bits for near qualifier 24-bits for far qualifier
MCU 2121
Slide 25
Pointer Example
struct personal { char age; char weight; }; variable in data memory struct personal Jane = { 84, 110 }; variable in program memory rom struct personal Bob = { 24, 180 };
rom pointer to data memory struct personal *rom person1 = & Jane; ram pointer to data in program memory rom struct personal *person2 = & Bob; rom pointer to data in program memory rom struct personal *rom person3 = & Bob;
String Constants
String literals (e.g., Hello World) are of type: rom const char []; Multiple versions of standard C string libraries are provided to help accommodate this: strcpypgm2ram( myvar, Wait... ); strlenpgm( Volume Control );
MCU 2121
Slide 27

MCU 2121
Slide 28
Inline Assembly Insert assembly instructions into C Typical uses:

Specialized instructions (e.g. CLRWDT) Specific sequence of instructions
Hand optimization Increase program control
MCU 2121
Slide 29
Inline Assembly
Syntax:
Specify all operands Directives are not supported C style comments Labels require a colon Use C-style literals (0x12 or 18, not H12) Note: optimizations are disabled in functions with inline assembly.
void add5 (void) { static char foo=0; _asm // foo += 5 movlb foo movlw 0x5 addwf foo,1,1 _endasm }
MCU 2121
Slide 30

MCU 2121
Slide 31
Mixing C and Assembly

Requires sharing of symbols
C Export Import (nothing) external declaration Assembly GLOBAL EXTERN
Described in the MPLAB C Compiler for PIC18 Users Guide
MCU 2121
Slide 32
Example of Mixing C / Asm

// import function void infinite_asm( void ); // import data extern char asm_count; char c_count; void infinite_c( void ) { asm_count++; infinite_asm(); } ; import function & data EXTERN infinite_c, c_count udata asm_count res 1 code infinite_asm: movlb c_count incf c_count goto infinite_c ; export function & data GLOBAL infinite_asm, asm_count
C file
Assembly file
Slide 33

MCU 2121
Slide 34
MPLAB C Compiler for PIC 18

Default Sections Un-initialized Data (.udata)
int x;
Initialized Data (.idata)

int y = 5;
Data in program Memory (.romdata)

rom int z = 12;
Executable content (.code)

void foo (void) {}
Specifying Sections Add section name and absolute address of a section

#pragma type [attribute-list] [section name[=address]]
Example: Create an uninitialized section mydata at location 0x120

#pragma udata mydata = 0x120 near long counter;
Section Attributes
access
Locate section in access RAM no banking required variables must be declared with near qualifier
overlay
Permit other sections to occupy same address May be combined with access Each section must reside in separate .c file All must have same name and address

MCU 2121
Slide 38
Configuration Settings Support

Processor specific configuration
#pragma config setting-list
Ex. watchdog timer, brown out reset, oscillator settings, PLVD, etc Setting list in: C:\MCC18\doc\hlpPIC18ConfigSet.chm
MCU 2121
Slide 39
PIC18 Interrupts
Interrupt Overview
Multiple Internal and External Sources
Global Enable Bit Individual Enable, Flag and Priority Bits Two Modes of Operation
Legacy: RCON.IPEN = 0 (Default) Priority: RCON.IPEN = 1
Most Interrupts Wake PIC from Sleep Fast Context Save/Restore Latency of 3-4 Instruction Cycles
MCU 2121
Slide 41
Interrupt Logic
Legacy Mode
TMR0IF TMR0IE
Other Core Interrupts Core Interrupts
Wakeup to CPU
Peripheral Interrupts
TMR1IF TMR1IE
Interrupt to CPU Vector to 0x0008
Other Peripheral Interrupts
GIE
PEIE
MCU 2121
Slide 42
Interrupt Logic
Priority Mode
IP IE IF INT0IF INT0IE GIEH Vector to 0x0008 High Priority Interrupt to CPU Wakeup to CPU Low Priority Interrupt to CPU Vector to 0x0018 GIEL
IP IE IF
MCU 2121
Slide 43
Interrupt Overview
Interrupt Sources
3 or 4 External Interrupts (INT0-INT3)
Edge Triggered Rising or Falling selected in INTCON2 register
PORTB Interrupt on Change (RB4-RB7) Timer Rollover/Overflow Events Comparator Output Change A/D Conversion Complete Communication Channel Events Other Peripheral Events
MCU 2121
Slide 44
Enabling Interrupts
(slide 1 of 7)
Set Interrupt Priority Enable

Legacy or priority mode interrupt operation
RCON Register
IPEN
SBOREN
---
RI
TO
PD
POR
BOR
IPEN: Interrupt Priority Enable 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupt (PIC16 compatibility mode)
MCU 2121
Slide 45
Enabling Interrupts
(slide 2 of 7) Set Peripheral Interrupt Priority
1 = High Priority, 0 = Low Priority
IPR1 Register
PSPIP
PSPIP: ADIP: RCIP: TXIP:
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
Parallel Slave Interrupt Priority A/D Converter Interrupt Priority EUSART Rcv Interrupt Priority EUSART Tx Interrupt Priority
SSPIP: CCPIP: TMR2IP: TMR1IP:
MSSP Interrupt Priority CCP1 Interrupt Priority Timer2 Interrupt Priority Timer1 Interrupt Priority
IPR2 Register
OSCIP
OSCIP: CMIP: ---EEIP:
CMIP
---
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
Oscillator Fail Interrupt Priority Comparator Interrupt Priority Unimplemented Bit Data EEPROM/Flash Write Operation Interrupt Priority
BCLIP: HLVDIP: TMR3IP: CCP2IP:
Bus Collision Interrupt Priority High/Low Voltage Detect Interrupt Priority Timer3 Interrupt Priority CCP2 Interrupt Priority
MCU 2121
Slide 46
Enabling Interrupts
(slide 3 of 7)
Set Peripheral Interrupt Enables

1 = Enabled, 0 = Disabled
PIE1 Register
PSPIE
PSPIE: ADIE: RCIE: TXIE:
ADIE
RCIE
TXIE
SSPIE
SSPIE: CCPIE: TMR2IE: TMR1IE:
CCPIE
TMR2IE
TMR1IE
Parallel Slave Interrupt Enable A/D Converter Interrupt Enable EUSART Rcv Interrupt Enable EUSART Tx Interrupt Enable
MSSP Interrupt Enable CCP1 Interrupt Enable Timer2 Interrupt Enable Timer1 Interrupt Enable
PIE2 Register
OSCIE
OSCIE: CMIE: ---EEIE:
CMIE
---
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
Oscillator Fail Interrupt Enable Comparator Interrupt Enable Unimplemented Bit Data EEPROM/Flash Write Operation Interrupt Enable
BCLIE: HLVDIE: TMR3IE: CCP2IE:
Bus Collision Interrupt Enable High/Low Voltage Detect Interrupt Enable Timer3 Interrupt Enable CCP2 Interrupt Enable
MCU 2121
Slide 47
Enabling Interrupts
(slide 4 of 7)
Set Core Interrupt Priority

1 = High Priority, 0 = Low Priority
INTCON2 Register
RBPU
INTEDG0 INTEDG1 INTEDG2
---
TMR0IP
---
RBIP
TMR0IP: TMR0 Overflow Interrupt Priority RBIP: RB Port Change Interrupt Priority
INTCON3 Register
INT2IP
INT2IP: INT1IP:
INT1IP
---
INT2IE
INT1IE
---
INT2IF
INT1IF
INT2 External Interrupt Priority INT1 External Interrupt Priority
NOTE: INT0 does not have an IP bit it is always a high priority interrupt
MCU 2121
Slide 48
Enabling Interrupts
(slide 5 of 7)
Set Core Interrupt Enables

1 = Enabled, 0 = Disabled
INTCON Register
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
TMR0IE: TMR0 Overflow Interrupt Enable INT0IE: INT0 External Interrupt Enable RBIE: RB Port Change Interrupt Enable INTCON3 Register
INT2IP
INT1IP
--INT2IE: INT1IE:
INT2IE
INT1IE
---
INT2IF
INT1IF
INT2 External Interrupt Enable INT1 External Interrupt Enable
MCU 2121
Slide 49
Enabling Interrupts
(slide 6 of 7)
Enable Peripheral Interrupts

INTCON Register
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PEIE/GIEL: Peripheral Interrupt Enable When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts
MCU 2121
Slide 50
Enabling Interrupts
(slide 7 of 7)
Enable Global Interrupts

INTCON Register
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
GIE/GIEL: Peripheral Interrupt Enable When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts
MCU 2121
Slide 51

Program Memory Variables Inline Assembly Mixing C and Assembly Defining Sections Configuration Settings Support Interrupt Support
MCU 2121
Slide 52
Interrupt Support
Programmer responsibility:
Provide code for interrupt vector Provide Interrupt Service Routine (ISR)
Compiler saves:
WREG, BSR, STATUS registers (v3.xx and above)
Programmer saves:
Any additional information
MCU 2121
Slide 53
Creating an ISR Vector

Create a function at the (high) ISR vector address:
void high_isr (void); #pragma code high_vector_scn=0x0008 void high_vector (void) { _asm goto high_isr _endasm } #pragma code
MCU 2121
Slide 54
Declaring Interrupt Service Routines

Defining a low priority ISR
void isr_low (void); #pragma interruptlow isr_low void isr_low (void) { // Code for low priority ISR }
MCU 2121
Slide 55
Declaring Interrupt Service Routines

Defining a high priority ISR
void isr_high (void); #pragma interrupt isr_high void isr_high (void) { // Code for high priority ISR }
MCU 2121
Slide 56
Preserving Compiler Resources Prior to C18 v3.00 users were required to preserve compiler resources
#pragma interrupt isr \ save=section(.tmpdata), PROD void isr (void) { int result; result = poll_device(); ... }
MCU 2121
Slide 57
Preserving Resources v3.xx automatically saves and restores context May save variables and sections:
#pragma interrupt \save= myint, section(mydata) isr void isr (void) { int result; result = poll_device(); ... }
MCU 2121
Slide 58
PIC18 Peripherals
PIC18 Common Peripherals

Digital I/O Ports Analog Comparator Analog to Digital Converter Timers (0,1,2,3) Capture, Compare, PWM (CCP) Addressable USART (AUSART) Master Synchronous Serial Port (MSSP) Parallel Slave Port (PSP)
MCU 2121
Slide 60
Digital I/O Ports
Digital I/O Ports

Up to 70 bi-directional I/O pins
Some multiplexed with peripheral functions
High drive capability

25mA source/sink capability
Direct, single cycle bit manipulation 4kV ESD protection diodes

Based on human body model
After reset:
Digital I/O default to Input (Hi-Z) Analog capable pins default to analog
MCU 2121
Slide 62
Configuring Analog Pins for Digital

Method depends on specific device
Could be in ADCON1 register
ADC Control Register 1 (ADCON1)
Port Configuration Bits
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
Could be in ANSEL registers

1 = Analog; 0 = Digital ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 ANS13 ANS12 ANS11 ANS10 ANS9 ANS8
Some devices allow Port B configuration in configuration registers
MCU 2121
Slide 63
I/O Port Direction Control
Bit n in TRISx controls the data direction of Bit n in PORTx 1 = Input, 0 = Output
Digital I/O Ports

MOVF MOVF MOVWF MOVWF PORTX,w LATX,w PORTX LATX Reads PORTX Pins (Physical state of pin) Reads PORTX Output Latch Register Writes to PORTX / LATX Writes to PORTX / LATX
8-bit Data Bus
Write PORTX Write LATX LATX

(PORTX Latches)
Read LATX
Read PORTX
PORTX
I/O Pins
Why do we have LAT Reg?

At Low Frequency or Low Capacitive Loading
BSET PORTA,PIN0 BSET PORTA,PIN1
Q4 Voltage VIL V on PORTA,PIN0
Q1
Q2
Q3
Qclks Port A Read in RMW Operation
At High Frequency or High Capacitive Loading

BSET PORTA,PIN0 BSET PORTA,PIN1
Q4 Q1 Q2 Q3 Q4 Voltage VIL V on PORTA,PIN0 Port A Read in RMW Operation

Qclks
Port B Options
Configuring PORTB Interrupt on Change
RB7:RB4 have interrupt on change option

Pins must be set as INPUT to be included
INTCON Register
R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit 1 = Enables all unmasked (IPEN=0) / high priority (IPEN=1) interrupts 0 = Disables all interrupts RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the pins RB7:RB4 changed state (must be cleared in software) 0 = None of the RB7:RB4 pins changed state
MCU 2121 Slide 67
bit 3
bit 0
PORTB Options
All PORTB pins have weak internal pull up.
One bit controls all pins
INTCON2 Register
R/W-1 bit 7 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit

1 = All PORTB Pull-ups are disabled 0 = PORTB Pull-ups are enabled by individual port latch values
bit 0
RBIP: RB Port Change Interrupt Priority bit

1 = High Priority 0 = Low Priority
MCU 2121
Slide 68
Development Tools
MPLAB IDE, ICD2, PICDEM2 Plus
MPLAB IDE
MPLAB Integrated Development Environment Integrates Microchip and 3rd Party Tools
Code Editor Assembler and Compilers Linker and Librarian Simulator, Debuggers and Emulators Programmers
MCU 2121
Slide 70
MPLAB-ICD 2 and PICDEM 2 Plus
USB
ICSP over RJ11
All labs will use the ICD 2 and PICDEM 2 Plus

ICD2 In-circuit programmer and debugger PICDEM 2 Plus demo board for most PIC16/18 devices
PICDEM 2 Plus Demo Board
MCU 2121
Slide 72
Analog:
Comparators
Analog Comparator Module

V REF
Two comparators Operates in sleep mode Generates interrupt / wakeup on output change Comparator output pins available Eight programmable modes
Analog Comparator
Key Registers
CMCON Register
R-0 bit 7 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 bit 0
C2OUT: Comparator 2 Output C1OUT: Comparator 1 Output C2INV: Comparator 2 Inversion
C1INV: Comparator 1 Inversion CIS: Comparator Input Switch CM2:CM0: Comparator Mode
CVRCON Register
R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
CVRSS: Comparator Vref Source CVREN: Comparator Vref Enable Selection CVROE: Comparator Vref Output Enable CVRR: Comparator Vref Range Selection CVR3:CVR0: Comparator Vref Value Selection
MCU 2121
Slide 75

Modes of Operation
CMCON Register
R-0 bit 7 R-0 R/W-0
Comparators Reset
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 bit 0
C1OUT C1OUT
RA0/AN0 VINVIN+
Off (Read as 0)
CM2 = 0 RA3/AN3 CM2 = 0 CM1 = 0 CM1 = 0 CM0 = 0 RA1/AN1 CM0 = 0

RA2/AN2
C1 + C2 +
State Change
C1INV = 0 C1INV = 0 C2INV = 0 C2INV = 0

State Change
VINVIN+
CMIF Interrupt Flag
C2OUT C2OUT CIS = X CIS = X

Off (Read as 0)
Slide 76

Configuraton
CMCON Register
Two Independent Comparators

C1OUT C1OUT
RA0/AN0 VINVIN+

RA2/AN2
C1 + C2 +
State Change

State Change
VINVIN+
CMIF Interrupt Flag


Configuraton
CMCON Register
Two Common Reference Comparators

C1OUT C1OUT
RA0/AN0 VINVIN+

RA2/AN2
C1 + C2 +
State Change

State Change
VINVIN+
CMIF Interrupt Flag


Configuraton
CMCON Register
One Independent Comparator with Output

C1OUT C1OUT
RA0/AN0 VINVIN+

RA2/AN2
C1 + C2 +
RA4/C1OUT
State Change

State Change
VINVIN+
CMIF Interrupt Flag


Configuraton
CMCON Register
Two Independent Comparators with Outputs

C1OUT C1OUT
RA0/AN0 VINVIN+

RA2/AN2
C1 + C2 +
RA4/C1OUT
State Change

State Change
VINVIN+
CMIF Interrupt Flag
RA5/C2OUT


Configuraton
CMCON Register
Two Common Reference Comparators with Outputs

C1OUT C1OUT
RA0/AN0 VINVIN+

RA2/AN2
C1 + C2 +
RA4/C1OUT
State Change

State Change
VINVIN+
CMIF Interrupt Flag
RA5/C2OUT


Configuraton
CMCON Register
Four Inputs Multiplexed to Two Comparators

C1OUT C1OUT
RA0/AN0 RA3/AN3 VIN+ VIN-
CM2 = 1 CM2 = 1 CM1 = 1 CM1 = 1

RA1/AN1 VINVIN+
C1 + C2 +
From VREF Module
State Change

State Change
CMIF Interrupt Flag
CM0 = 0 CM0 = 0
RA2/AN2
C2OUT C2OUT
CIS = 0 CIS = 0

Configuraton
CMCON Register
Comparators Off
C1OUT C1OUT
RA0/AN0 VINVIN+
Off (Read as 0)

RA2/AN2
C1 + C2 +
State Change

State Change
VINVIN+
CMIF Interrupt Flag

Off (Read as 0)
Slide 83
Analog:
Comparator Vref
Comparator Voltage Reference

16 Tap Resistor Ladder Network 24 or 32 Step Sizes Internal or External Voltage Source for Reference Generation VREF output can be directed to I/O pin Can be used as 4-bit D/A Converter
MCU 2121
Slide 85
Comparator Voltage Reference

Configuration
CVRCON Register
R/W-0 bit 7 CVRSRC VREF+ VDD 8R VREF Enable R Value Select R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
When CVRR = 1: When CVRR = 1:

CVREF = ((CVR3:CVR0)/24)(CVRSRC)) CVREF = ((CVR3:CVR0)/24)(CVRSRC
CVR3:0 CVR3:0
When CVRR = 0: When CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32)(CVRSRC)) CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32)(CVRSRC
CVREN CVREN
16 Steps Source Select
R R
16:1 Mux
CVREF
CVRSS = 0 CVRSS = 0
Range Select
R R 8R
RA2/AN2/CVREF
CVRR CVRR
VREF-
Output Enable
CVOE CVOE
Analog:
10-bit A/D Converter Module
10-bit A/D Converter

Channel Select
CHS3:CHS0 CHS3:CHS0
AN12 AN12 AN10 AN9 AN8 AN7* AN6* AN5* AN4
In ADCON0 Register
13:1 Analog Mux
VAIN
10-bit A/D Result Registers
ADC
VREF+ VREF-
ADRESH
ADRESL
VREF+ / AN3 VREF- / AN2

AN1 AN0
VDD
x0 x1 1x 0x
VSS VREF Select VCFG1:VCFG0 In ADCON1 Register VCFG1:VCFG0

*AN5-AN7 not available on 28-pin devices
Input Signal Acquisition Time

Acquisition Time Conversion Time
time VC
ADRES VIN
10
time
SOURCE
ADC
CHOLD VSS
+ VC -
Acquisition Time is determined RS < 10k by Acquisition Time allows Pin Capacitance and time to Hold Capacitor Source impedance fully charge to VIN V (recommend <10k)
MCU 2121
Slide 89
Conversion Time
Acquisition Time Conversion Time Acquisition Time
time VC
ADRES VIN
ADC Result
10
time ADC Conversion Clock cycles (TAD)
ADC
CHOLD VSS
time
+ VC -
Slide 90

Conversion Process
Step 1: Initialize the A/D module:
Configure analog pins, reference voltages, and digital/analog I/O pins Select the A/D input channel Select the A/D acquisition time Select the A/D conversion clock source Enable the A/D module (set ADON bit)
Step 2: Configure the A/D Interrupt (optional)

Clear the ADIF bit Set the ADIE bit Set the GIE bit
Step 3: Wait for the desired acquisition time (T ACQ)

Only required if ACQT2:0 = 000
MCU 2121
Slide 91

Conversion Process
Step 4: Set GO/DONE bit to start the conversion Step 5: Wait for the A/D conversion to complete
Wait for GO/DONE bit to be cleared OR Wait for A/D interrupt
Step 6: Read A/D result registers Step 7: Clear the ADIF flag Wait at least 2 T AD before next acquisition
MCU 2121
Slide 92

Configuration
ADCON0 Register
U-0 bit 7 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
bit 5-2
CHS3:CHS0 Analog Channel Select Bits

0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = Channel 0 (AN0) Channel 1 (AN1) Channel 2 (AN2) Channel 3 (AN3) Channel 4 (AN4) Channel 5 (AN5) Channel 6 (AN6) Channel 7 (AN7) Channel 8 (AN8) Channel 9 (AN9) Channel 10 (AN10) Channel 11 (AN11) Channel 12 (AN12)
bit 1
GO/DONE: A/D Conversion Status bit

1 = A/D Conversion in progress 0 = A/D Idle
bit 0
ADON: A/D On bit

1 = A/D Converter module is enabled 0 = A/D Converter module is disabled
MCU 2121
Slide 93

Configuration
ADCON1 Register
U-0 bit 7 U-0 R/W-0 R/W-0 R/W-0* R/W* R/W* R/W* bit 0
bit 5
VCFG1: Voltage Reference (VREF-) Configuration bit 1 = VREF- (AN2)

0 = VSS
bit 4
VCFG0: Voltage Reference (VREF+) Configuration bit

1 = VREF+ (AN3) 0 = VDD
MCU 2121
Slide 94

Configuration
ADCON1 Register
bit 3-0 PCFG3:PCFG0 A/D Port Configuration Control bits
A = Analog Input D = Digital I/O
MCU 2121
Slide 95

Configuration
ADCON2 Register
NOTE: This parameter determines the value of TAD: the conversion time per bit. bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Selection bits
111 = FRC (Clock derived from A/D RC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (Clock derived from A/D RC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2

Configuration
Choosing the A/D Clock Source

Choose T AD such that it is as short as possible without going less than the minimum T AD allowed.
A/D Clock Source (TAD) A/D Clock Source (TAD) Operation Operation 2 TOSC 2 TOSC 4 TOSC 4 TOSC 8 TOSC 8 TOSC 16 TOSC 16 TOSC 32 TOSC 32 TOSC 64 TOSC 64 TOSC RC RC ADCS2:ADCS0 ADCS2:ADCS0 000 000 100 100 001 001 101 101 010 010 110 110 x11 x11 Maximum Device Frequency Maximum Device Frequency PIC18F4520 PIC18F4520 2.86 MHz 2.86 MHz 5.71 MHz 5.71 MHz 11.43 MHz 11.43 MHz 22.86 MHz 22.86 MHz 40.0 MHz 40.0 MHz 40.0 MHz 40.0 MHz * *
At FOSC = 4 MHz: TOSC = 1/FOSC = .25 s TAD = 4T OSC = 1 s
* The Internal RC has a typical TAD time of 1.2s
Minimum T AD = 0.7s
See data sheet for official specification.

MCU 2121 Slide 97

Configuration
Calculating Acquisition Time
TACQ = TAMP + TC + TCOFF

TAMP = Amplifier Settling Time = Tamp internal + Tamp external TC = Charging Time = -(CHOLD)(RIC + RSS + RS)ln(1/2047)s TCOFF = Temperature Coefficient = (Temp 25C)(0.02s/C) for Temp > 25C = 0 for Temp < 25C

Configuration
Calculating amplifier settling time
TAMP = TAMP INT+ TAMP EXT

TAMP INT : Internal amplifier settling time. Check datasheet for specific part. For the PIC18F4520, TAMP INT is 2 s. TAMP EXT: External amplifier (circuitry) settling time. This becomes important when external components are used to pre-condition the signal. Since the external circuitry on the PICDEM2 Plus is a mechanical POT, this number is 0 s.
TAMP = 2 s

Configuration
Calculating Charging Time

TC = -(CHOLD)(RIC + RSS + RS)ln(1/2047)s
CHOLD RIC RSS RS = Holding Capacitor Value = 25pF = Interconnect Resistance = 1k = Sampling Switch Impedance = 2k = Source Impedance = 2.5k MAX
Assuming a maximum source impedance of 2.5k, we have: TC = 1.05s


Configuration
Calculating Temperature Coefficient
TCOFF = (Temp 25C)(0.02s/C)

Temp = Operating Temperature Valid for Temp > 25C. TCOFF = 0 for Temp < 25C Using the maximum operating temperature of 85C for an Industrial grade part, we have: TCOFF = 1.2s

Configuration
Calculating Acquisition Time
TACQ = TAMP + TC + TCOFF

For Rs = 2.5k Temp = 85 C TAMP = 2 s
TACQ = 2 + 1 + 1.2 = 4.2 s


Configuration
ADCON2 Register
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Selection bits

111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD
Given: TACQ = 4.2 s TAD = 800 ns Then: ACQT2:0 = 011 = 4.8 s
MCU 2121
Slide 103

Configuration
ADCON2 Register
R/W-0 bit 7 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
bit 7
ADFM: A/D Result Format Selection bit 1 = Right Justified ADRESH

b9 b9 b8 b8
ADRESL
b7 b6 b7 b6 b5 b5 b4 b3 b4 b3 b2 b2 b1 b1 b0 b0
0 = Left Justified ADRESH

b9 b9 b8 b8 b7 b6 b7 b6 b5 b5 b4 b3 b4 b3 b2 b2
ADRESL
b1 b0 b1 b0
MCU 2121
Slide 104
Timers
Timer 0, Timer 1 and Timer 3 Modules
Timer Comparison
TIMER 0 SIZE OF REGISTER 8-bits or 16-bits Fosc/4 TIMERS 1 & 3 16-bits TIMERS 2 & 4 8-bits
CLOCK SOURCE (Internal) CLOCK SOURCE (External ) CLOCK SCALING AVAILABLE (Resolution) INTERRUPT EVENT
Fosc/4
Fosc/4
T0CKI pin
T13CKI pin or Timer 1 oscillator (T1OSC)
None
Prescaler 8-bits (1:21:256)
Prescaler 2-bits (1:1, 1:2, 1:4, 1:8)
Prescaler (1:1,1:4,1:16) Postscaler (1:11:16)
On overflow FFh00h NO
On overflow FFFFh0000h YES
TMR REG matches PR2
CAN WAKE PIC FROM SLEEP?
NO
MCU 2121
Slide 106
Timer 0
PIC16 Compatibility Mode
8-bit Timer/Counter 8-bit Programmable Prescaler Internal or External Clock Source Interrupt on Overflow from FF to 00
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1
TMR0L
Programmable Prescaler
T0SE T0SE
T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0 PSA PSA 8-bit Data Bus
MCU 2121
Slide 107
Timer 0
16-bit Mode
16-bit Timer / Counter 16-bit Read / Write Mode Interrupt on overflow from FFFF to 0000 Same basic features as compatibility mode
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
T0CS T0CS T0PS2:T0PS0 T0PS2:T0PS0 PSA PSA
TMR0H
8-bit Data Bus

Timer 0 Operation
TMR0IF TMR0IF FOSC/4 T0CKI
0 0 1
Clock Sync
1
TMR0L
T0SE T0SE
DATA BUS
T0CON Register
TMR0ON T08BIT T0CS T0SE PSA T0PS2:0
T08BIT 1 = 8 BIT 0 = 16 BIT

Timer 0 Operation
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
TMR0H
DATA BUS
T0CON Register
T08BIT 1 = 8 BIT 0 = 16 BIT

Timer 0 Operation
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
TMR0H
DATA BUS
T0CON Register
TMR0 Clock Source Select 1 = TOCK1, 0 = Fosc/4
MCU 2121
Slide 111
Timer 0 Operation
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
TMR0H
DATA BUS
T0CON Register
Source Edge Select 1 = increment TMR0 on rising edge 0 = increment TMR0 on falling edge
MCU 2121
Slide 112
Timer 0 Operation
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
TMR0H
DATA BUS
T0CON Register
Prescaler Assignment 1= prescaler NOT assigned 0= prescaler IS assigned

Timer 0 Operation
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
TMR0H
DATA BUS
T0CON Register
PS2 0 0 0
PS1 0 0 1 1 0 0 1 1
PS0 0 1 0 1 0 1 0 1
TMR0 RATE 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Slide 114
Prescaler Rate Select Bits
0 1 1 1 1
MCU 2121
Timer 0 Operation
FOSC/4 T0CKI
0 0 1
TMR0IF TMR0IF
Clock Sync
1 READ TMR0L
High Byte
TMR0L
WRITE TMR0L
T0SE T0SE
TMR0H
DATA BUS
T0CON Register
TMR0ON 1 = ON 0 = STOPPED
Timer 1 and Timer 3

16-bit Timer / Counter Timer, Synchronous Counter or Asynchronous Counter Can operate from separate external crystal Two readable and writeable 8-bit registers 1, 2, 4, or 8 Prescaler Interrupt on overflow from FFFFh to 0000h
MCU 2121
Slide 116
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
T1OSO/ T13CKI T1OSI FOSC/4 T1OSCEN T1OSCEN
Prescaler 1, 2, 4, 8
0
Sync Detect Sleep Input
T1SYNC T1SYNC TMR1ON TMR1ON
TMR1CS TMR1CS T1CKPS1: T1CKPS0 T1CKPS1: T1CKPS0
TMR1IF TMR1IF
Clear Timer 1 (CCP Special Event Trigger)
READ TMR1L
High Byte
TMR1L
WRITE TMR1L
TMR1H
8-bit Data Bus RD16

Bit 7
T1RUN
TCKPS1:0
T1OSCEN
T1SYNC
TMR1CS TMR1ON
Bit 0
T1CON Register
MCU 2121
Slide 117
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
16-bit Read/Write Mode Enable 1 = Read/Write of Timer in one operation 0 = Read/Write of Timer in two 8-bit operations
TMR1IF TMR1IF
TMR1H Clear Timer 1 (CCP Special Event Trigger) TMR1L
8-bit Data Bus
T1CON Register
RD16
Bit 7
T1RUN
TCKPS1:0
T1OSCEN
T1SYNC
TMR1CS TMR1ON
Bit 0
Slide 118
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
16-bit Read/Write Mode Enable 1 = Read/Write of Timer in one operation 0 = Read/Write of Timer in two 8-bit operations
Clear Timer 1 (CCP Special Event Trigger) High Byte

READ TMR1L
TMR1IF TMR1IF
TMR1L
WRITE TMR1L
TMR1H
T1CON Register
RD16
Bit 7
8-bit Data Bus T1OSCEN T1SYNC TMR1CS TMR1ON

Bit 0
Slide 119
T1RUN
TCKPS1:0
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
TMR1IF TMR1IF
READ TMR1L
TMR1L
WRITE TMR1L
Timer1 Oscillator Enable 1 = T1OSC Enabled 0 = T1OSC off
TMR1H
T1CON Register
RD16
Bit 7

Bit 0
Slide 120
T1RUN
TCKPS1:0
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
TMR1IF TMR1IF
READ TMR1L
TMR1L
WRITE TMR1L
Timer1 Clock Source 1= External Clock 0 = Fosc/4
TMR1H
T1CON Register
RD16
Bit 7

Bit 0
Slide 121
T1RUN
TCKPS1:0
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
TMR1IF TMR1IF
Timer1 Prescale Select 11 = 1:8 10 = 1:4 01 = 1:2 00 = 1:1

READ TMR1L
High Byte
TMR1L
WRITE TMR1L
TMR1H
T1CON Register
RD16
Bit 7

Bit 0
Slide 122
T1RUN
TCKPS1:0
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
TMR1IF TMR1IF
READ TMR1L
TMR1L
WRITE TMR1L
Timer1 System Clock Status Read Only Bit 1 = Device clock derived from Timer1 OSC 0 = Device clock derived from another source
TMR1H
T1CON Register
RD16
Bit 7

Bit 0
Slide 123
T1RUN
TCKPS1:0
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
TMR1IF TMR1IF
Timer1 External Clock Synchronization Bit only used when TMR1CS = 1 1 = Synchronize external clock input 0 = Do not synchronize

READ TMR1L
High Byte
TMR1L
WRITE TMR1L
TMR1H
T1CON Register
RD16
Bit 7

Bit 0
Slide 124
T1RUN
TCKPS1:0
Timer 1 and Timer 3

Timer 1 Oscillator
1 1
0
TMR1IF TMR1IF
Timer On 1 = Enables Timer 0 = Stops Timer

READ TMR1L
High Byte
TMR1L
WRITE TMR1L
TMR1H
T1CON Register
RD16
Bit 7

Bit 0
T1RUN
TCKPS1:0
MCU 2121
Slide 125
CCP Module
PWM Mode
Timer 2
8-bit Timer with prescaler and postscaler Used as PWM time base TMR2 is readable & writable TMR2 resets on match with PR2 Match with PR2 generates interrupt Used as baud clock for MSSP (SPI)
MCU 2121
Slide 127
Timer 2
T2CON Register
R/W-0 -bit 7 R/W-0 T2OUTPS3 T2OUTPS3 R/W-0 T2OUTPS2 T2OUTPS2 R/W-0 T2OUTPS1 T2OUTPS1 R/W-0 T2OUTPS0 T2OUTPS0 R/W-0 TMR2ON TMR2ON R/W-0 T2CKPS1 T2CKPS1 R/W-0 T2CKPS0 T2CKPS0 bit 0
00 = 1:1 01 = 1:4 1x = 1:16

TMR2 Prescale Value Selection Bits T2CKPS1:T2CKPS0 T2CKPS1:T2CKPS0
TMR2 Postscale Value Selection Bits T2OUTPS3:T2OUTPS0 T2OUTPS3:T2OUTPS0

1:1 to 1:16 Postscaler
0000 = 1:1 0001 = 1:2 1111 = 1:16

TMR2IF TMR2IF
Timer 2 Output (To PWM or MSSP) PR2
Reset
TMR2/PR2 Match
FOSC/4
1:1, 1:4, 1:16 Prescaler
TMR2
Comparator
8-bit Data Bus
MCU 2121
Slide 128
CCP and ECCP Modules

Standard CCP Module (CCP2):
Input Capture Output Compare Standard, Single Output PWM
Enhanced CCP Module (CCP1):

Complementary Outputs Deadband control
MCU 2121
Slide 129
CCP2
PWM Mode
CCPxCON<5:4> Master CCPR2L 5 4
High Time (Duty Cycle) Duty Cycle

TMR2 = CCPRxH:2 LSb
Slave
CCPR2H CCPx Output Comparator VDD VSS
R S
TB0 TB1 TMR2 * * Corresponding TRIS Bit TMR2 = PR2 TMR2 = PR2
Period
Comparator
Clear Timer, CCPx pin and latch D.C.
PR2
Period
MCU 2121
Slide 130
Configuring CCPx for PWM

1. 2.
Set PWM Period by writing to PR2 register Set PWM Duty Cycle by writing to CCPRxL and CCPxCON<5:4> bits Make the CCPx pin an output by clearing the appropriate TRIS bit Set the TMR2 prescale value, then enable TMR2 by writing to T2CON Configure the CCPx module for PWM mode
3.
4.
5.
MCU 2121
Slide 131
PWM Configuration: Step 1

Calculating the Period Value
TPWM = (PR2 + 1) 4 TOSC TMR2PRE

TPWM = Desired PWM Signal Period = 1 / fPWM PR2 = TMR2s Period Register TOSC = System Oscillator Period = 1 / fOSC TMR2PRE = TMR2 Prescale Value (1, 4, or 16)
MCU 2121
Slide 132

Calculating the Period Value
Rearranging the equation we get:
PR2 =
fOSC 4 fPWM TMR2PRE
-1
Choose TMR2PRE to ensure that PR2 is in the range of 0 to 255 for the desired PWM frequency.
TMR2PRE may be 1, 4, or 16.


Calculating the Duty Cycle Value
DCPWM = (CCPRxL:CCPxCON<5:4>) TOSC TMR2PRE

DCPWM = Desired PWM Duty Cycle (time, not %) CCPR2L = Upper 8-bits of Duty Cycle Value CCP2CON<5:4> = Low 2-bits of Duty Cycle Value TOSC = System Oscillator Period TMR2PRE = TMR2 Prescale Value (1, 4, or 16)
MCU 2121
Slide 134

Calcluating the Duty Cycle Value
Rearranging the equation we get:

%DCPWM fOSC CCPR2L:CCP2CON<5:4> = 100 TMR2PRE fPWM
Choose TMR2PRE to ensure that CCPR2L:CCP2CON<5:4> is in the range of 0 to 1023 for the desired PWM duty cycle.
TMR2PRE may be 1, 4, or 16.
MCU 2121
Slide 135

Calculating the Duty Cycle Value
10-bit Duty Cycle value is stored across two registers:

CCPRxL Register
R/W-0 DC2B9 DC2B9 bit 7 R/W-0 DCxB8 DCxB8 R/W-0 DCxB7 DCxB7 R/W-0 DCxB6 DCxB6 R/W-0 DCxB5 DCxB5 R/W-0 DCxB4 DCxB4 R/W-0 DCxB3 DCxB3 R/W-0 DCxB2 DCxB2 bit 0
8 Most Significant Bits 8 Most Significant Bits
CCPxCON Register
R/W-0 -bit 7 R/W-0 -R/W-0 DCxB1 DCxB1 R/W-0 DCxB0 DCxB0 R/W-0 CCPxM3 CCPxM3 R/W-0 CCPxM2 CCPxM2 R/W-0 CCPxM1 CCPxM1 R/W-0 CCPxM0 CCPxM0 bit 0
2 Least Significant Bits 2 Least Significant Bits
MCU 2121
Slide 136
PWM Configuration: Step 3 Configure

the CCP2 Pin as an Output
Select CCP2 pin Clear corresponding TRIS bit

(1)
RB3/AN9/CCP2(1)
Optional CCP2 on RB3: If CONFIG3H<CCP2MX> = 0 #pragma config CCP2MUX = OFF
TRISB<3> = 0 TRISB<3> = 0
RC1/T1OSI/CCP2(1)
Default CCP2 on RC1: If CONFIG3H<CCP2MX> = 1 #pragma config CCP2MUX = ON
(1)
TRISC<2> = 0 TRISC<2> = 0

Set TMR2 Prescale Value and Enable TMR2
T2CON Register
R/W-0 -bit 7 R/W-0 T2OUTPS3 T2OUTPS3 R/W-0 T2OUTPS2 T2OUTPS2 R/W-0 T2OUTPS1 T2OUTPS1 R/W-0 T2OUTPS0 T2OUTPS0 R/W-0 TMR2ON TMR2ON R/W-0 T2CKPS1 T2CKPS1 R/W-0 T2CKPS0 T2CKPS0 bit 0
bit 2
TMR2ON: Timer2 On bit

1 = Timer2 is On 0 = Timer 2 is Off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
T2CKPS1:T2CKPS0 T2CKPS1:T2CKPS0 values determined when values determined when calculating PWM period calculating PWM period and duty cycle and duty cycle
MCU 2121
Slide 138

Configure CCP for PWM Mode
CCP2CON Register
R/W-0 -bit 7 R/W-0 -R/W-0 DC2B1 DC2B1 R/W-0 DC2B0 DC2B0 R/W-0 CCP2M3 CCP2M3 R/W-0 CCP2M2 CCP2M2 R/W-0 CCP2M1 CCP2M1 R/W-0 CCP2M0 CCP2M0 bit 0
bit 5-4 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0 for CCP2
These bits are the two LSbs of the 10-bit PWM duty cycle. The 8 MSbs (DCx9:DCx2) of the duty cycle are found in CCPR2L.
DC2B1:DC2B0 values determined when calculating PWM duty cycle DC2B1:DC2B0 values determined when calculating PWM duty cycle
bit 3-0 CCP2M3:CCP2M0: CCP Module 2 Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCP2IF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 11xx = PWM mode
CCP Module
Capture Mode
CCP Module
Capture Mode Applications
Event arrival time recording Period measurement Pulse-width measurement Interrupt generation Event counting Time reference* Duty cycle measurement*
* Requires a second CCP module operating in compare mode
MCU 2121
Slide 141
CCP Module Timer Resources

CCP Mode Capture Compare PWM
RD16
Bit 7
Timer Resource Timer1 or Timer3* Timer1 or Timer3* Timer2

T3CCP1 T1SYNC TMR1CS TMR1ON
Bit 0
T3CCP2
TCKPS1:0
T3CON Register
*T3CCP2:1 Timer3 and Timer1 to CCP Enable 1x = Timer3 is clock source for CCP modules 01 = Timer3 is clock source for CCP2 Timer1 is clock source for CCP1 00 = Timer1 is clock source for CCP modules
CCP Module
Input Capture Mode
CCPxCON Register: CCPx Mode Select Bits 0100: Capture every falling edge 0110: Capture every 4th rising edge 0101: Capture every rising edge 0111: Capture every 16th rising edge T3CON Register Timer Mode Select bits CCPxM3:0 CCPxM3:0 T3CCP2:1 T3CCP2:1 TMR3H TMR 3 Enable 1:1, 1:4, 1:16 Prescaler CCPRxH TMR 1 Enable TMR1H CCPx Pin
TMR3L
Edge detect
CCPRxL
TMR1L
Set CCPxIF
MCU 2121 Slide 143
CCP Module
Compare Mode Applications
Generate
Single pulse Train of pulses Periodic waveform
Start ADC conversion Time reference* Duty cycle measurement*
* Requires a second CCP module operating in compare mode
MCU 2121
Slide 144
CCP Module
Output Compare Mode
Set CCPIF Special Event Trigger CCPR1H CCPR1L CCPx output pin
Comparator
O/P Logic
S Q R
CCPxM3:0 CCPxM3:0
TRIS output Enable
TMR1 T3CCP2:1 T3CCP2:1 T3CON Register Timer Mode Select bits
TMR3 CCPxCON Register: CCPx Mode Select Bits 0010: Toggle CCPx pin on match (CCPxIF bit set) 1000: CCPx pin high on match (CCPxIF bit set) 1001: CCPx pin low on match (CCPxIF bit set) 1010: Generate s/w interrupt on match (CCPx pin not affected) 1011: Trigger special event on match (CCPIF bit set)
MCU 2121
Slide 145
MSSP
(Master Synchronous Serial Port) (Master Synchronous Serial Port)
(I2C, SPI and Microwire)
Master Synchronous Serial Port

SPITM Mode
Programmable baud rate Maximum baud rates (@ 40MHz)
Master: 10 Mbps Slave: 2.5 Mbps Single Byte Tx
I2CTM Mode
Standard (100 kHz), Fast (400 kHz)
Microchip 1 MHz proprietary protocol
Master / multi - master 7 or 10-bit addressing
SPI is a trademark of Motorola Semiconductor I2C is a trademark of Philips Semiconductors Microwire is a trademark of National Semiconductor
MCU 2121
Slide 147
MSSP
I2C Slave Mode
Data Bus
Read SSPBUF RC3/SCK/SCL RC4/SDI/SDA

MSb Shift Clock
Write
I2C read/write data Internal shift register No user access

Addr Match
SSPSR
LSb
Match Detect
SSPADD
I2C slave address

Set, Reset S, P bits
Start and Stop bit Detect
MCU 2121
Slide 148
MSSP
I2C Master Mode
SSPADD<6:0> Data Bus SSPM3:SSPM0 SSPM3:SSPM0 Write SSPBUF
SDA In
Read
SDA SSPSR
MSb
Receive Enable
Baud Rate Generator Shift Clock

Clock Arbitrate/WCOL Detect (hold off clock source)
LSb
Bus Collision
SCL
SCL In
Start, Stop, WCOL Detect Clock Arbitration State Counter for end of TX/RX
Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2)
MCU 2121
Clock Ctrl
Start bit, Stop bit, ACK Generate
Slide 149
SSP Configuration Register I2C Mode

SSPCON1 Register
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
SSPEN WCOL SSPOV CKP
=Synchronous Serial Port Enable Bit = Write Collision Detect Bit = Receive Overflow Indicator = Clock Polarity Bit (slave mode only)
SSPM<3:0>: Synchronous Serial Port Mode Select Bits 1111 = I2C Slave Mode, 10-Bit Address w/ Start/Stop interrupts 1110 = I2C Slave Mode, 7-Bit Address w/ Start/Stop interrupts 1011 = I2C Firmware controlled master mode (Slave Idle) 1000 = I2C Hardware master mode, clock = FOSC / (4 *(SSPADD+1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address
MCU 2121
Slide 150
SSP Configuration Register I2C Mode

SSPCON2 Register
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
GCEN: SEN (Master): SEN (Slave):
General Call Enable (Slave mode only) Start condition enable Clock stretching enable MASTER MODE ONLY Acknowledge status bit (Master xmit only) Acknowledge data bit (Master rcv) only Acknowledge sequence enable (Master rcv only) Receive Enable Stop condition enable Repeated start enable
MCU 2121 Slide 151
ACKSTAT: ACKDT: ACKEN: RCEN: PEN: RSEN:
SSP Status Register I2C Mode

SSPSTAT Register
SMP CKE D/A P S R/W UA BF
SMP CKE
Read / Write bits = Slew Rate Control for High Speed Enable = SMbus select
D/A P S R/W UA BF
Read Only bits = Data / Not Address Bit (Slave Mode only) = Stop Bit = Start Bit = Read / Not Write Bit = Update Address Bit (for 10-bit slave address mode) = Buffer Full
MCU 2121
Slide 152
SSPADD Register
SSPADD Register
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Reserve Addresses
B 0000 000 General Call Address 000 B0000 001 CBUS address 001 B0000 010 Reserved for different bus format 010 B0000 011 Future Purposes 011 B0000 1XX Hs-mode master code 1XX HsB1111 1XX Future Purposes 1XX B1111 0XX 10-bit Slave Address 0XX 10-
SLAVE: Holds slave device address MASTER: Lower 7 bits used by baud rate generator
MCU 2121
Slide 153
SSPADD Register Configure for 10-bit Addressing

SSPADD Register
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Load SSPADD with 11110 A9 A8 0

A9 and A8 are MSB of the slave address Match will set SSPSTAT<UA> bit
IF SSPSTAT<UA> = 1, Load SSPADD with lower byte
MCU 2121
Slide 154
MSSP
I2C Master Mode Baud Rate Generator
SSPADD<6:0> SSPM3:SSPM0 SSPM3:SSPM0 SSPADD<6:0>
SCL
Reload Control CLKO
Reload
BRG Down Counter Decremented twice per instruction cycle (TCY)
FOSC/4
FCY FCY
10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz
2*FCY 2*FCY
20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz 2 MHz 2 MHz 2 MHz
MCU 2121
BRG Value BRG Value SSPADD<6:0> SSPADD<6:0>

18h 18h 1Fh 1Fh 63h 63h 09h 09h 0Ch 0Ch 27h 27h 02h 02h 09h 09h 00h 00h
(2 Rollovers of BRG) (2 Rollovers of BRG) 400 kHz 400 kHz 312.5 kHz 312.5 kHz 100 kHz 100 kHz 400 kHz 400 kHz 308 kHz 308 kHz 100 kHz 100 kHz 333 kHz 333 kHz 100 kHz 100 kHz 1 MHz 1 MHz
Slide 155
FSCL FSCL
Address Masking Feature

Available in some PIC18s, see datasheets
What is it?
It allows a PIC MCU to ACK more than one address.
What is it good for?

Integrating multiple I2C devices in one PIC MCU SDA SCL Master
EEPROM, Real-Time Clock, Analog-to-Digital Converter, Fan Controller
PIC18F45K20
MCU 2121
Slide 156
Address Masking Feature Example A 0 in the SSPMSK register ignores the corresponding address bit Example: SSPADD = 0b1010111R SSPMSK = 0b1111100R Module will respond to addresses:
0b1010111R, 0b1010110R, 0b1010101R, 0b10101100R
MCU 2121
Slide 157
MSSP (I2C Slave Mode) Address Detection

Data Bus Read SSPBUF
Shift Clock
Write
1. Start Condition detected 2. Address shifted into SSPSR 3. SSPSR<7:1> compared to SSPADD<7:1> IF match AND no overflow
RC3/SCK/SCL RC4/SDI/SDA
MSb
SSPSR
LSb
Match Detect
Addr Match SSPIF
SSPADD
1. SSPSR loaded into SSPBUF 2. BF = 1; read SSPBUF to clear 3. ACK generated 4. SSPIF = 1 (must be cleared via software) 5. R/W bit updated in SSPSTAT
Set, Reset S, P bits (SSPSTAT)
MCU 2121
Slide 158
MSSP (I2C Slave Mode) Master Write

Shift Clock
Write
Data is shifted into SSPSR 8-bits => latch to SSPBUF IF BF and SSPOV = 0, ACK is sent Read SSPBUF to clear BF SSPIF = 1 (clear in s/w)
MSb
SSPSR
LSb
Match Detect
OVERFLOW Data fills SSPSR before SSPBUF is read SSPOV set and NACK sent Master sends STOP Addr Match
SSPIF
SSPADD
CLOCK STRETCHING SSPCON2<SEN> = 1; hold SSPCON<CKP> = 1; release

MCU 2121
Slide 159
MSSP (I2C Slave Mode) Master Read

Shift Clock
Write
SCL is held low Data loaded into SSPBUF

SSPSR auto loaded BF = 1
MSb
SCL enabled by setting SSPCON1<CKP> Data shifted out using SCL

BF = 0
SSPSR
LSb
Addr Match
ACK latched on 9th clock

IF NACK, xfer done, slave waits for another START
Match Detect
SSPADD
MCU 2121
Slide 160
MSSP (I2C Master Mode) Master Write

Send Start Condition
NO
Send Data Byte

NO
I2C Done?
YES
I 2C
YES
Done?
NO
Send Slave Address

NO
ACK?
YES
Send Stop Or Restart

NO
I 2C
Done?
YES
Xmit Done?
YES
ACK?
YES
Send Stop Or Restart
Send Stop Condition
MCU 2121
Slide 161
MSSP (I2C Master Mode) Example: Write to EEPROM

#define CNTL_IN #define EE_ADDR #define EE_DATA #define BAUD #define ACKSTAT #define SSPIF void main (void) { // Set up I/O pins TRISC = 0xFF; TRISB = 0X00; SSPCON1 = 0x28; SSPSTAT = 0x80; SSPADD = BAUD; SSPCON2bits.SEN = Wait_I2C(); 0xA0 //I2C value for writing to EEPROM (slave address included) 0x12 //Sample value for address 0xBE //Sample data to write 0x09 //Baud rate generation for Fcy = 1 MHz, Fscl = 100 kHz SSPCON2bits.ACKSTAT PIR1bits.SSPIF
1;
//Set PORTC to input, especially RC3 and RC4 //Set PORTB to output LEDs used to indicate error //Configure MSSP for Hardware Master Mode and enable //Disable slew rate and select I2C bus levels //Setup baud rate generator //Initiate START condition
CONTINUED ON NEXT SLIDE
MCU 2121
Slide 162
MSSP (I2C Master Mode) Example: Write to EEPROM CNTD

SSPBUF = CNTL_IN; Wait_I2C(); if (ACKSTAT) ack_error(); SSPBUF = EE_ADDR; Wait_I2C(); if (ACKSTAT) ack_error(); SSPBUF = EE_DATA; Wait_I2C(); if (ACKSTAT) ack_error(); SSPCON2bits.PEN = 1; } // END MAIN FUNCTION //Send EEPROM control byte (Slave Address) //Wait for I2C operation to complete //Check for ACK if NACK, call error function //Send EEPROM address byte
//Send EEPROM data byte
//Send STOP condition
void ack_error(void) { SSPCON2bits.PEN = 1; //Send STOP condition PORTB = 0xFF; //Turn on LEDs to indicate error while(1); //In real code this would be handled better } void Wait_I2C(void) { while(!SSPIF); //SSPIF is set after all I2C operations, wait for flag SSPIF = 0; //Clear flag } MCU 2121 2008 Microchip Technology Incorporated. All Rights Reserved.
Slide 163
MSSP (I2C Master Mode) Master Read

Enable Receive Send Start Condition I 2C I 2C
NO NO
Done?
NO
Done?
YES
YES
Send Slave Address

NO
Read Another?
YES
Send NACK
NO
Send ACK
NO
I2C Done?
YES
I 2C
Done?
YES
I2C Done? Send Stop Or Restart

YES
Send Stop Condition
ACK?
YES
Send Restart
MCU 2121 Slide 164
EUSART
Enhanced Universal Synchronous Receiver/Transmitter
EUSART
Summary
Full-duplex asynchronous -or- half-duplex synchronous 8- or 9-bit data Double-buffered transmit and receive buffers 9-bit addressable mode Auto-Wake-up on character reception Auto-Baud calibration Max baud rates @ 40 MHz Synchronous: 10 Mbaud Asynchronous: 625 Kbaud/2.5 Mbaud
MCU 2121
Slide 166
EUSART
Block Diagram
TX9D TXIE Interrupt 9 TX8/9 TXDATA
TXREG
TxSTA
RxSTA
TXIF
TSR
TXCLK
OERR FERR
RXDATA RCCLK ADDEN RC8/9 RX9D 9
RSR
C O N T R O L
Baud Rate Clock
RC6/TX/CK
RC7/RX/DT
RCREG
RCIF
RCIE
Baud Rate Generator
Tcy
MCU 2121
Slide 167
EUSART Transmit Status and Control

TXSTA Register
CSRC TX9 TXEN SYNC -BRGH TRMT TXD9
CSRC TX9 TXEN SYNC BRGH
TRANSMIT CONTROL = Clock Source Select (synchronous modes only) = Enable 9-bit transmission = Enable transmit = Select synchronous or asynchronous mode = High baud rate select (asynchronous mode only) TRANSMIT STATUS = Transmit shift register status (0= full, 1=empty) = Ninth bit of transmit data
TRMT TXD9
MCU 2121
Slide 168
EUSART Receive Status and Control

RXSTA Register
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
RECEIVE CONTROL SPEN = Serial port enable RX9 = Enable 9-bit reception SREN = Single receive enable (synchronous mode only) CREN (asynch) = Enable receiver CREN (sync) = Enable continuous receive (overrides SREN) ADDEN = Enable address detect (asynch = 1) RECEIVE STATUS = Framing error = Overrun error (cleared by clearing CREN) = Ninth bit of receive data
FERR OEFF RXD9
MCU 2121
Slide 169
EUSART Baud Rate Generator

Dedicated 8- or 16-bit Used in both synchronous and asynchronous modes TXSTA<BRGH> used with BRGCON<BRG16> to determine formula for SPBRG and SPBRGH
SYNC 0 0 1 1
BRG16 0 1 0 1
BRGH = 0 (FOSC / (64*BR)) - 1 (FOSC / (16*BR)) - 1 (FOSC / (4*BR)) - 1 (FOSC / (4*BR)) - 1
BRGH = 1 (FOSC / (16*BR)) - 1 (FOSC / (4*BR)) - 1 N/A N/A
MCU 2121
Slide 170

EXAMPLE: Calculate SPBRG value to achieve 9600 baud in 8-bit asynchronous high speed mode. FOSC = 4 MHz
SYNC 0 0 1 1 BRG16 0 1 0 1 BRGH = 0 (FOSC / (64*BR)) - 1 (FOSC / (16*BR)) - 1 (FOSC / (4*BR)) - 1 (FOSC / (4*BR)) - 1 BRGH = 1 (FOSC / (16*BR)) - 1 (FOSC / (4*BR)) - 1 N/A N/A
SPBRG = 4 X 106 / (16 * 9600)) 1 SPBRG = 25.042 Load SPBRG with nearest integer value: SPBRG=> 0x19 SPBRGH => 0x00
EUSART Baud Rate Error

Baud Rate Error = (BR Desired BR) / Desired BR For our example Actual Baud Rate = Fosc / (16*(SPBRG+1)) = 4x106 / (16*(25 +1)) = 9615.385 Baud Rate Error = (9615.385 9600) / 9600 = 0.16%
MCU 2121
Slide 172

BAUDCON Register
ABDOVF RCIDL -SCKP BRG16 -WUE ABDEN
ABDOVF RCIDL SCKP BRG16 WUE ADDEN
= Auto Baud Rate acquisition rollover status = Receive Operation Idle = Clock polarity (synch mode only) = Enable 16-bit baud rate register = Wake up enable (asynch mode only) = Auto baud detection enable (asynch mode only)
MCU 2121
Slide 173
EUSART
Transmit Operation
TXREG empty, will set TXIF Loading TXREG resets TXIF TSR empty will set TRMT Loading TSR resets TRMT If TXREG is loaded and TRMT is set, then data is immediately loaded to TSR. Serial data shifting starts and TXIF will be set
TXIF
TXREG
TRMT
TSR
RC6/TX/CK
MCU 2121
Slide 174
EUSART
Receive Operation
RSR receives data with valid start/stop Data loaded into RCREG FIFO and RCIF = 1 If 2nd byte is received before the 1st has been serviced, then new data will be placed in the 2nd location on the FIFO When servicing the receive interrupt, after reading the 1st byte, if another byte is still in the FIFO, then a second RCIF interrupt is generated
RSR ADDEN
RC7/RX/DT
RCREG RCIF
2 deep FIFO
MCU 2121
Slide 175
Oscillators & Power Saving Modes
PIC18F: Clock System Clock Sources

Primary
Fixed Selection LP, XT, HS, RC, EC, Int RC Osc
Secondary
Timer1 Oscillator - fixed frequency Required for Real Time Clock time base
Internal RC Oscillator
INTOSC (8 MHz) source
4, 2, 1 MHz, 500, 250, 125 and 31 kHz
INTRC (31 kHz) source
MCU 2121
Slide 177
PIC18 Oscillator Options

XT XT HS HS HS+PLL HS+PLL LP LP RC RC RCIO RCIO INTRC INTRC EC EC ECIO ECIO Standard frequency crystal oscillator Standard frequency crystal oscillator High frequency crystal oscillator High frequency crystal oscillator High frequency crystal with 4x PLL High frequency crystal with 4x PLL Low frequency crystal oscillator Low frequency crystal oscillator External RC oscillator External RC oscillator External RC oscillator, OSC2=RA6 External RC oscillator, OSC2=RA6 Internal RC oscillator Internal RC oscillator External Clock, OSC2=fosc/4 External Clock, OSC2=fosc/4 External Clock, OSC2=RA6 External Clock, OSC2=RA6 100kHz -- 4MHz 100kHz 4MHz DC -- 40MHz DC 40MHz 4MHz -- 10MHz 4MHz 10MHz 5kHz -- 200kHz 5kHz 200kHz DC -- 4MHz DC 4MHz DC -- 4MHz DC 4MHz Various Various DC -- 40MHz DC 40MHz DC -- 40MHz DC 40MHz
Selectable clock options provide greater flexibility for the designer:

LP Oscillator designed to draw least amount of current RC or INTRC provide ultra low cost oscillator solution XT optimized for most commonly used oscillator frequencies HS optimized to drive high frequency crystals or resonators
Speed ranges are guidelines only
MCU 2121
Slide 178
PIC18F: Clock System Internal RC Oscillator

2 separate RC sources
8 MHz (INTOSC) 31 kHz (INTRC)
2 - 31 kHz sources INTOSC 8 & 4 MHz can be routed through PLL

16 or 32 MHz
Modifying IRCF<2:0> bits immediately selects a different INTOSC postscaler tap
MCU 2121
Slide 179
PIC18F: Power Managed Modes
3 Categories
RUN - 3 clock sources IDLE - 3 clock sources SLEEP - no clocks Total = 7 Modes
PIC18F: Power Managed Modes

PRI_RUN Mode Config Word defines Primary Clock Source
FOSC3:FOSC0 (_CONFIG1H<3:0>) 10 modes
Crystal Oscillator - LP, XT, HS, HSPLL External Clock - EC, ECIO External RC Oscillator - RC, RCIO Internal RC Oscillator - INTIO1, INTIO2
SEC_RUN Mode
Clock switching mechanism in other PIC18 controllers Timer1 source, Primary oscillator is disabled
RC_RUN Mode
IRCF<2:0> selects clock speed IOFS set after 1us (typ.) delay if Freq 31 kHz
PIC18F Special Features

Wide operating voltage range: 2.0V to 5.5V 100,000 erase/write cycle Enhanced Flash program memory (typical) 1,000,000 erase/write cycle Data EEPROM memory (typical) Flash/Data EEPROM Retention: 100 years typical
MCU 2121
Slide 183
POR, OST, PWRT

POR: Power On Reset
With MCLR tied to VDD, a reset pulse is generated when VDD rise is detected
PWRT: Power Up Timer

Device is held in reset for 72ms (nominal) to allow VDD to rise to an acceptable level (after POR only)
OST: Oscillator Start-up Timer

Holds device in reset for 1024 cycles to allow crystal or resonator to stabilize in frequency and amplitude; not active in RC modes; used only after POR or Wake Up from SLEEP
MCU 2121
Slide 184
Sleep Mode
The processor can be put into a power-down mode by executing the SLEEP instruction
System oscillator is stopped Processor status is maintained (static design) Watchdog timer continues to run, if enabled Minimal supply current is drawn - mostly due to leakage (0.1 - 2.0A typical)
Events that wake processor from sleep Events that wake processor from sleep
MCLR MCLR WDT WDT INT INT TMR1 TMR1 ADC ADC CMP CMP CCP CCP PORTB PORTB SSP SSP PSP PSP Master Clear Pin Asserted (pulled low) Master Clear Pin Asserted (pulled low) Watchdog Timer Timeout Watchdog Timer Timeout INT Pin Interrupt INT Pin Interrupt Timer 1 Interrupt (or also TMR3 on PIC18) Timer 1 Interrupt (or also TMR3 on PIC18) A/D Conversion Complete Interrupt A/D Conversion Complete Interrupt Comparator Output Change Interrupt Comparator Output Change Interrupt Input Capture Event Input Capture Event PORTB Interrupt on Change PORTB Interrupt on Change Synchronous Serial Port (I2C Mode) Start // Stop Bit Detect Interrupt Synchronous Serial Port (I2C Mode) Start Stop Bit Detect Interrupt Parallel Slave Port Read or Write Parallel Slave Port Read or Write
MCU 2121 Slide 185
Watchdog Timer
Helps recover from software malfunction Uses its own free-running on-chip RC oscillator WDT is cleared by CLRWDT instruction Enabled WDT (WDTEN) cannot be disabled by software WDT overflow resets the chip Programmable timeout period: 18ms to 3.0s typical Operates in SLEEP; on time out, wakes up CPU
MCU 2121
Slide 186
In-Circuit Serial Programming

Only two pins required for programming Convenient for In-System Programming of
Calibration Data Serialization Data
Supported by MPLAB PM3 & ICD2
Pin Pin VPP VPP VDD VDD VSS VSS RB6 RB6 RB7 RB7
Function Function Programming Voltage = 13V Programming Voltage = 13V Supply Voltage Supply Voltage Ground Ground Clock Input Clock Input Data I/O & Command Input Data I/O & Command Input
PIC18Fxxxx
ICSP Connector
MCU 2121
Slide 187
BOR Brown Out Reset

When voltage drops below a particular threshold, the device is held in reset Prevents erratic or unexpected operation Eliminates need for external BOR circuitry
MCU 2121
Slide 188
PBOR Programmable Brown Out Reset

Configuration Option (set at program time) Cannot be enabled / disabled in software Four selectable BVDD trip points: 2.5V Minimum VDD for OTP PICmicro MCUs 2.7V 4.2V 4.5V For other thresholds, use an external supervisor (MCP1xx, MCP8xx/TCM8xx, or TC12xx)
MCU 2121
Slide 189
PBOR Programmable Brown Out Reset

Holds PICmicro MCU in reset until ~72ms after VDD rises back above threshold
MCU 2121
Slide 190
PLVD Programmable Low Voltage Detect

Early warning before brown out 16 selectable trip points:
1.8V up to 4.5V in 0.1 to 0.2V steps External analog input
16-bit Multiplexer
Internal VREF
MCU 2121
Slide 191

Resets
PIC18 RESETS
Power-on Reset (POR) MCLR Reset during normal operation Programmable Brown-out Reset (BOR) Watchdog Timer (WDT) Reset (during execution) RESET Instruction Stack Full Reset Stack Underflow Reset
For all the resets PC vectors to address 0
MCU 2121
Slide 192

RESET Registers
After RESET PC will have the address 0x000000 Following bits will be affected after each RESETS
POR = 0: Power On RESET BOR = 0 & POR = 1: BOR RESET TO = 0: WDT RESET RI = 0: RESET Instruction STKFUL = 1: Stack over flow RESET STKUNF = 1: Stack under flow RESET POR, BOR, TO & RI = 1 and STKFUL & STKUNF = 0: MCLR RESET
MCU 2121
Slide 193
Summary
Summary
We discussed PIC18 Architecture
Programmers Model Instruction set Overview Interrupt Handling and latency
Covered The Basic Peripherals

I/O Ports Development Tools Comparators, Voltage Reference ADC
MCU 2121
Slide 195
Summary
Timers CCP (Capture, Compare & PWM) MSSP (I2C & SPI / Microwire) USART
Discussed
Oscillator and power saving modes Special features of PIC18F controllers
MCU 2121
Slide 196
Summary
Carried out the Labs on
Basic C18 Project Creation IO Port initialization and reading and writing to the Ports Initialization and ADC conversion Timer configuration Generating PWM Capturing the input signal I2C module configuration EUSART configuration
MCU 2121
Slide 197
References
PIC18F4520 Datasheets PIC18F family reference manual PICDEM2 Plus Users Guide MPLAB C18 C Compiler Users Guide MPLAB C18 C Compiler Getting Started Guide MPLAB C18 C Compiler Libraries Guide Other PIC18-based classes
101_TLS: Introduction to MPLAB IDE, ICD2 102_ASP: Introduction to PIC18F Arch. 202_ASP: PIC18 Peripherals in Asm. 390_USB: USB From Scratch
MCU 2121
Slide 198
Please complete the review form

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies.
MCU 2121
Slide 200

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202 PRC

PIC18 Peripheral Configuration and MPLAB-C18 Programming Techniques

2008 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

2008 Microchip Technology Incorporated. All Rights Reserved.

2008 Microchip Technology Incorporated. All Rights Reserved.

2008 Microchip Technology Incorporated. All Rights Reserved.

Oscillators and Power Saving Modes Special features

2008 Microchip Technology Incorporated. All Rights Reserved.

Program Memory (Up to 2MB)

2008 Microchip Technology Incorporated. All Rights Reserved.

Program Memory Organization

Reset Vector @ 0x00 Interrupt Vectors

2008 Microchip Technology Incorporated. All Rights Reserved.

Return Address Stack

Top of Stack Registers:

RESET State: No RAM at level 0

No rollover back to level 0!

2008 Microchip Technology Incorporated. All Rights Reserved.

2008 Microchip Technology Incorporated. All Rights Reserved.

TBLWT instruction is used to load write buffer

TBLRD/TBLWT *auto post-decrement of table pointer

2008 Microchip Technology Incorporated. All Rights Reserved.

Data Memory Organization

PIC18F2520/4520 Register File Map

080h 0FFh 100h

Bank 2 Bank 2 GPR GPR

Access Bank Access RAM Access RAM

Bank 14 Bank 14 GPR GPR

Bank 15 GPR Bank 15 GPR Access SFR Access SFR

PIC18 Instruction Set

Instruction Set Overview

Branching / Conditional Branching

2008 Microchip Technology Incorporated. All Rights Reserved.

Instruction Set Overview

Most Instructions Are Single Cycle

Table Read/Write 8 Extended Instructions

2008 Microchip Technology Incorporated. All Rights Reserved.

PIC18F: Extended Mode

2008 Microchip Technology Incorporated. All Rights Reserved.

Extended Mode Advantage

2008 Microchip Technology Incorporated. All Rights Reserved.

MPLAB C18 C Language Extensions

MPLAB C18 Compiler

2008 Microchip Technology Incorporated. All Rights Reserved.

C18 C Language Extensions

2008 Microchip Technology Incorporated. All Rights Reserved.

Anywhere in program Anywhere in memory data memory

NOTE: C18 default is far ram

2008 Microchip Technology Incorporated. All Rights Reserved.

2008 Microchip Technology Incorporated. All Rights Reserved.

C18 C Language Extensions

2008 Microchip Technology Incorporated. All Rights Reserved.

Inline Assembly Insert assembly instructions into C Typical uses:

2008 Microchip Technology Incorporated. All Rights Reserved.

2008 Microchip Technology Incorporated. All Rights Reserved.

C18 C Language Extensions

2008 Microchip Technology Incorporated. All Rights Reserved.

Mixing C and Assembly

Described in the MPLAB C Compiler for PIC18 Users Guide

2008 Microchip Technology Incorporated. All Rights Reserved.

Example of Mixing C / Asm

C18 C Language Extensions