library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.

ALL; entity Adder is port ( nibble1, nibble2 : in unsigned(3 downto 0); sum : out unsigned(3 downto 0); carry_out : out std_logic ); end entity Adder; architecture Behavioral of Adder is signal temp : unsigned(4 downto 0); begin temp <= ("0" & nibble1) + nibble2; -- OR use the following syntax: -- temp <= ('0' & nibble1) + ('0' & nibble2); sum <= temp(3 downto 0); carry_out <= temp(4); end architecture Behavioral;

entity lab8_final is Port ( x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0); s0 : out std_logic_vector(3 downto 0)); end lab8_final; architecture Behavioral of lab8_final is signal c : std_logic_vector (3 downto 0):="0000"; component lab8ex3 port(a,b,cin:in std_logic; s,cout:out std_logic); end component; begin bit1: lab8ex3 port bit2: lab8ex3 port bit3: lab8ex3 port bit4: lab8ex3 port end Behavioral; map map map map (a=>x(0), (a=>x(1), (a=>x(2), (a=>x(3), b=>y(0), b=>y(1), b=>y(2), b=>y(3), s=>s0(0), s=>s0(1), s=>s0(2), s=>s0(3), cin=>c(0), cin=>c(1), cin=>c(2), cin=>c(3), cout=>c(1)); cout=>c(2)); cout=>c(3)); cout=>c(0));