Desarrollo de los circuitos.

1. Programar y simular en VHDL los siguientes circuitos:

y Flip-flop JK con entradas SET y RESET. Este circuito est hecho con un FF activado con flanco de elevacin.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;

ENTITY ff_jk IS PORT( J, K, SET, RESET : in std_logic ; CLK : in std_logic ; Q, Qn : OUT std_logic ); END ff_jk; ARCHITECTURE arch_ff_jk OF ff_jk IS SIGNAL p_q :std_logic; BEGIN PROCESS(clk) BEGIN IF clk='1' THEN IF (SET='0' AND RESET='0') THEN IF(J='0' AND K='1') THEN p_q <= '0'; ELSIF(J='1' AND K='0') THEN p_q <= '1'; ELSIF(J='1' AND K='1') THEN p_q <= NOT p_q; END IF;

ELSIF(SET='1' AND RESET='0') THEN p_q <= '1'; ELSIF(SET='1' AND RESET='0') THEN p_q <= '0'; ELSIF(SET='1' AND RESET='1') THEN p_q <= '0'; END IF; END IF; END PROCESS; Q <= p_q; Qn <= NOT p_q; END arch_ff_jk;

Captura del circuito

Flip-flop D con entradas SET y RESET.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; ENTITY ff_D IS PORT( D,RESET,SET CLK Q,Qn END ff_D; ARCHITECTURE arch_ff_D OF ff_D IS SIGNAL p_q : BEGIN std_logic ; :in std_logic ; :in std_logic ; :OUT std_logic );

PROCESS(clk) BEGIN IF clk='1' THEN IF(SET='0' AND RESET='0') THEN p_q <= D; ELSIF(SET='0' AND RESET='1') THEN p_q <= '0'; ELSIF(SET='1' AND RESET='0') THEN p_q <= '1'; ELSIF(SET='1' AND RESET='1') THEN p_q <= '0'; END IF; END IF; END PROCESS; Q <= p_q; Qn <= NOT p_q; END arch_ff_D;