Microprocessor – 8086 - II

N. Mathivanan
 Pins & Signals
• Common Signals • MN mode Signals GND 1 40 VCC
A D 14 2 39 A D 15
– MN/MX# – M/IO#,
A D 13 3 38 A 1 6 /S 3
– AD15-AD0 – WR#, A D 12 4 37 A 1 7 /S 4
A D 11 5 36 A 1 8 /S 5
– A19/S6 – A15/S3 – ALE A D 10 6 35 A 1 9 /S 6
A D9 7 34 B H E # /S 7
– BHE#/S7 – DT/R#, DEN# A D8 8 33 M N /M X #
A D7 9 32 RD#
– RD# – INTA#
A D6 10 31 R Q # /G T 0 # (H O L D )
– READY – HOLD, HLDA A D5 11 30 R Q # /G T 1 # (H L D A )
A D4 12 29 LO CK # (W R # )
– NMI, INTR • MX mode Signals A D3 13 28 S2# (M /IO # )
A D2 14 27 S1# (D T /R # )
– TEST#
• RQ#/GT1# A D1 15 26 S0# (D E N # )
A D0 16 25 QS0 (A L E )
– RESET
• RQ#/GT0# NM I 17 24 QS1 (IN T A # )
– CLK IN T R 18 23 TEST
• QS0-QS1 CLK 19 22 REA D Y
– VCC, GND GND 20 21 RESET
• S0#, S1#, S2#
• LOCK#
 Bus Cycles
M e m o ry R e a d M e m o r y W r it e
T1 T2 T3 T4 T1 T2 T3 T4 T1

C LK

ALE

M / IO #

A 1 9 /S 6 - A 1 6 /S 3
A19 - A16, BH E# S7 - S3 A19 - A16, BH E# S7 - S3
B H E # /S 7

F lo a t F lo a t F lo a t
AD 15 - AD 0 A15 - A0 D a t a in D 1 5 - D 0 V a lid A15 - A0 D a ta o u t D 1 5 - D 0

R D #

D T / R #

D EN #

W R #
 Basic System Components

• Clock generator, Bus buffering & demultiplexing, bus controller

• Clock generator (8284)

– Ready block

– Clock block

– Reset block

R ES# D
C LK _
Q R E SE T#
R ES ET B LO C K X1 X2

R ES#
X1
C ry s ta l
O S C 8284A
o s c illa t o r
X2
R ESET# R ESET
A D IV B Y D IV B Y
M U X 3 2 P C LK R EAD Y R EAD Y
F /C # B S Y N C SY N C
S e le c t C LK C LK
E F I R D Y 1
C S Y N C AEN 1# AEN 2#
8086
C LK
C LO C K BLO C K
R D Y 1

AE N 1#

D Q D Q R E AD Y
R D Y 2 C LK C LK
AE N 2#
F F ! F F 2
AS Y N C # R EA D Y B LO C K
 Wait state generation
+ 5 V

X1 X2

R ES#

8284A

R ES ET# R ESET

R EAD Y R EAD Y
C h ip s e le c t f r o m m e m o r y d e v ic e
C LK C LK
7 6 5 4 3 2 1 0 R D Y 1
AEN 1# AEN 2#
8086

Q H Q G Q F Q E Q D Q C Q B Q A
C LK
74LS164
C LR

R D #
W R #
IN T A #
Bus buffering & demultiplexing
U 1 D 15
8 0 8 6

74LS 245
D IR C E # D 8

D A T A
D T /R #

B U S
D E N #
U 2 D 7

74LS 245
D IR C E # D 0

B H E # /S 7 U 3 B H E #

74LS 373
A 1 9 A 1 9

A 1 6 G O C # A 1 6

A 1 5 U 4 A 1 5

A D D R E S S B U S
74LS 373
A 8 G O C # A 8

A 7 U 5 A 7

A 0 G
74LS 373
O C # A 0

A L E

M /IO # U 6 U 7
74LS 244

W R # IO R #
74LS 138

R D # IO W #

V c c
M E M R #
M E M W #
 Bus controller (8288)
M R D C #
M W TC #
S0# AMW C #

C om m and

G e n e ra to r
S1# IO R C #

S ig n a l
S2# IO W C #
A IO W C #

Block diagram
IN TA #

AEN # D T /R #

G e n e ra to r
C LK D EN #

C o n tro l
S ig n a l
C EN A LE
IO B M C E /P D E N #

8288

M R D C # M e m o ry R ead
C LK S0# S0# M W TC # M e m o ry W r it e
AM W C # Adv anced M W
8284 R EAD Y S1# S1# IO R C # I/O R e a d
IO W C # I / O W r it e
R ESET S2# S2# A IO W C # Adv anced I/O W
IN T A # In te rru p t A c k n o w le d g e
8288
ALE
D T /R #
D EN G
8086
G N D O C #

Interfacing to 8086 A d d re s s /D a ta L a tc h e s AD D R ESS BU S

BH E# BH E#

M N /M X#

D IR

C E#
T r a n s c e iv e r
D A TA B U S
 Memory Banks
D A T A B U S
D 0 D 0

D 7 D 7
D 8 D 8

D 15 D 1 5
U PPER B A N K LO W ER B A N K
FFFFFH FFFFEH
FFFFD H FFFFC H
D 8 D 0
FFFFB H FFFFA H

D 15 O D D D 7
A D D R ES S ED EV EN
A D D R ES S ED

A 1 A 1

0000 7H 00006H
0000 5H 00004H
A 19 0000 3H A 19 00002H
0000 1H 00000H

C E# C E#
B H E# B H E#
A 0 A 0
A 1 A 1

A 19 A 1 9
A D D R E S S B U S
 Interfacing Four 4K x 8 EPROM (2732) devices

D 1 5 -D 8

D 7 -D 0

A 1 2 -A 1

E P R O M -1 E P R O M -0 E P R O M -3 E P R O M -2
A 0 D 0 A 0 D 0 A 0 D 0 A 0 D 0
A 1 D 1 A 1 D 1 A 1 D 1 A 1 D 1
A 2 D 2 A 2 D 2 A 2 D 2 A 2 D 2
A 3 D 3 A 3 D 3 A 3 D 3 A 3 D 3
A 4 D 4 A 4 D 4 A 4 D 4 A 4 D 4
A 5 D 5 A 5 D 5 A 5 D 5 A 5 D 5
A 6 D 6 A 6 D 6 A 6 D 6 A 6 D 6
A 7 D 7 A 7 D 7 A 7 D 7 A 7 D 7
A 8 A 8 A 8 A 8
A 9 A 9 A 9 A 9
A 10 A 10 A 10 A 10
A 11 A 11 A 11 A 11

O E O E O E O E
C E 4 K x8 C E 4 K x8 C E 4 K x8 C E 4 K x8
BH E#

M EM R # H MEM R #

LM EM R #
A0
74LS138
A 13 A Y 0
A14 B Y 1
A 15 C Y 2
A 16 Y 3
A 17 G 1 Y 4
Y 5 F C 0 0 0 H -F D F F F H
A 18 G 2A Y 6
A 19 G 2B Y 7
F E 0 0 0 H -F F F F F H
Interfacing Two 16K x 8 RAM (62128)devices
D 1 5 -D 8

D 7 -D 0

A 1 4 -A 1

R A M -1 R A M -0
A 0 D 0 A 0 D 0
A 1 D 1 A 1 D 1
A 2 D 2 A 2 D 2
A 3 D 3 A 3 D 3
A 4 D 4 A 4 D 4
A 5 D 5 A 5 D 5
A 6 D 6 A 6 D 6
A 7 D 7 A 7 D 7
A 8 A 8
A 9 A 9
A 1 0 A 1 0
A 1 1 A 1 1
A 1 2 A 1 2
A 1 3 A 1 3
1 6 K x8 1 6 K x8

W E

W E
O E

C E

O E

C E
M E M R #
M E M W #

7432 7432

B H E #
A 0
74 LS 138
0 0 0 0 0 H -0 7 F F F H
A 15 A Y 0
A 16 B Y 1
A 17 C Y 2
Y 3
A 18 G 2B Y 4
A 19 G 2A Y 5
Y 6
+ 5 V G 1 Y 7
 Interfacing EPROM & RAM devices
F i g u r e 3 .1 8 . In te r fa c i n g E P R O M a n d R A M , ( a ) th e c i r c u i t, ( b ) m e m o r y m a p
D 0 -D 7
D 8 -D 1 5
A 1 -A 1 5
74LS138
A 16 A Y 0
A 17 B Y 1 EPR O M -1 EPR O M -0 EPR O M -3 EPR O M -2
A 18 C Y 2
Y 3 A 0 D 0 A 0 D 0 A 0 D 0 A 0 D 0
A 19 G 1 Y 4 A 1 D 1 A 1 D 1 A 1 D 1 A 1 D 1
G 2A Y 5 A 2 D 2 A 2 D 2 A 2 D 2 A 2 D 2
G 2B Y 6 A 3 D 3 A 3 D 3 A 3 D 3 A 3 D 3
Y 7 A 4 D 4 A 4 D 4 A 4 D 4 A 4 D 4
A 5 D 5 A 5 D 5 A 5 D 5 A 5 D 5
A 6 D 6 A 6 D 6 A 6 D 6 A 6 D 6
A 7 D 7 A 7 D 7 A 7 D 7 A 7 D 7
A 8 A 8 A 8 A 8
A 9 A 9 A 9 A 9
BHE# A 1 0 A 1 0 A 1 0 A 1 0
A 1 1 A 1 1 A 1 1 A 1 1
A 1 2 A 1 2 A 1 2 A 1 2
A 1 3 A 1 3 A 1 3 A 1 3
A 1 4 A 1 4 A 1 4 A 1 4
A 0 O E O E O E O E
C E 27256 C E 27256 C E 27256 C E 27256

A 0 D 0 A 0 D 0 A 0 D 0 A 0 D 0
M EM R # A 1 D 1 A 1 D 1 A 1 D 1 A 1 D 1
M EM W # A 2 D 2 A 2 D 2 A 2 D 2 A 2 D 2 FFFFFH
A 3 D 3 A 3 D 3 A 3 D 3 A 3 D 3 E P R O M -2
A 16 A Y 0 A 4 D 4 A 4 D 4 A 4 D 4 A 4 D 4 and
A 17 B Y 1 A 5 D 5 A 5 D 5 A 5 D 5 A 5 D 5 64K
A 18 C Y 2 A 6 D 6 A 6 D 6 A 6 D 6 A 6 D 6 E P R O M -3
Y 3 A 7 D 7 A 7 D 7 A 7 D 7 A 7 D 7 F0000H
A 19 G 2A Y 4 A 8 A 8 A 8 A 8
G 2B Y 5 A 9 A 9 A 9 A 9 E P R O M -0
Y 6 A 1 0 A 1 0 A 1 0 A 1 0
VC C G 1 Y 7 A 1 1 A 1 1 A 1 1 A 1 1
and 64K
A 1 2 A 1 2 A 1 2 A 1 2 E P R O M -1
A 1 3 A 1 3 A 1 3 A 1 3 E0000H
A 1 4 A 1 4 A 1 4 A 1 4

BHE# O E O E O E O E
W E 62256 W E 62256 W E 62256 W E 62256
C E C E C E C E

A 0 R A M -1 R A M -0 R A M -3 R A M -2

1FFFFH
R A M -2
and 64K
R A M -3
10000H
R A M -0
and 64K
R A M -1
00000H
 Interfacing DRAM devices

O D D BAN K
82C 08 TM S 41C 256 x 8
R AS1# D R AM - 1
C AS1#
256 K x 8
S0# W R #
A 0 8 -0 EVEN BAN K
S1# R D # W E # D I/O
S2# P C TL TM S 41C 256 x 8

D R AM - 0
A19 PE#
W E /P C L K 256 K x 8
R AS0#
A18 - A1
C AS0# W E # D I/O
AAC K#
R D Y
BH E# D
C LK

A0 D
C LK

D 15 - D 8

D 7 - D 0