(G] adaptec, inc. The Winchester Controller Chip DESCRIPTION ‘The Winchester Controller Chip is @ Silicon Gate NMOS device that provides the ‘major portion of hardware necessary to Dulld a Winchester, disk Conirolier. “It ig, intended to be used with a microprocessor of the Intel. 8085 family. The focpin package requires only a single +SVDC supply. This device is designed to work with an external Separator, such as the two chip implementa ailable’ from Adaptec. “This combination of along with host memory bus Interface provides ‘the. system designer a versatile Unit design capability ate minimum chip count. “Ar. disk manufacturers increase” track Gensiiy, bit density, and the number of heads Der drive in their, future products, the Adaptec Winchester Controller Chip will easily accomodate these changes. Sevices, FEATURES Up to 10 MHz bit rate Multiple sector read/write 32 bit ECC polynomial High speed correction support Single 5V supply NR? serial, interface High Speed Data Search Sector defect handling Variable sector size capability in mu bytes Hard Sectored Disk Copability Ioles of 128 APPLICATIONS. Seagate $1506, ST412 compatible drives ‘Shugart 41000 compatible drives SMO. drives ANSI compatible Interface drives ae [fo] ces ||? 3 tune: |] 3% tee: ||? 3 ose: || % wer: || s wor || x eur. |[s 3 oarniren: |12—conrrouten #2 o | CHIP a secron. || 3 me || = svstuie [13 2 nc. ||se 2 we [fis FA or {fie zg bs: {fo x be: || 3 oe {ls B ono. [20 i AIC-100 FUNCTIONAL DESCRIPTION Internal to the Controller Chip are three functional Microprocessor interface decoder Sector format sequencer Date flow ‘The microprocessor Interface is an 6085 family interface. ‘There are 19 registers that provide for operation control, ECC “control, drive interface and format control. The device architecture is Structured to allow the firmware of an. NMOS Procestor to determine what functions are to be Incorporated In the control unit design. The sector format the basi whieh sequencer performs ‘drive read/write functions for a disk Include: Read 10 Read ID & Read Date Read 1D & Write Data Write 1D & Write Data These functions can be modified to perform the search data or verify date functions The track format Is the same as that recommended by" several disk manufacturers except for the addition of a flag byte in the ID field, providing Gefect lagging at the sector level, and 4 bytes of ECC rather than 2 CRC bytes. The addition of these bytes in ID and data flelds Is accommodated by “a Corresponding. decrease in the VFO syne fields. “A 256-byte ate field requires a total of 315 bytes per sector. The Winchester Controller Chip interfaces with the bidirectional data bus which is connected to an ‘external RAM buffer. The CS, WE and address increment signals required for the sector” buffer ere derived from the Clock A and Clock B outputs. The dataflow portion of the controller chip is composed of a 32-bit ECC and. a serializer/de- Serlalizer, Data to be written to the disk enters the" device "in obit “parallel format. It is Gerialized, and run. through a 32-bit ECC ‘Generator. The controller chip outputs NRZ serial Gata followed by 4 bytes of ECC check burst. The 32-bit ECC does not use the industry standard polynomial. Adaptec has employed @ polynomial that will coreect B-bit_ single. burst errors with "an “exicemely low probability of Imiscorrection and a fed errors. lower probability. of undetec=2, noe = ] rrr BLOCK DIAGRAM FUNCTIONAL. OPERATION the desired sector is found. In either case, the “The Winchester Controller Chip is designed to be last ID field read may be "popes" rem the Used "with an NMOS processor rather than the high stack (RTF). Speed It slice designs required for controtiers in if an ECC error Is. detected sflec a read data iRepast. This NMOS processor is wed fo maintain Speraion, the syndrane te. saved ‘nthe ECE Toose"" synchronization with what tt happening Ksealiet rael t Portod (osprey oy real “tine "on" the. dink “through the ‘Oh Command Gy"Ns"csarteg." By employing registers “71. 72 and (R79) and Sequencer Status (R79) registers. The 3 the microprocessor can determine If the error Witehestor Gontrelier Chip in retorn nainiaiss the [o WOtattaey "ane if ao, the error pattern an lose" synchronization of data to and from the isplacement fram the beginning of the sector: disk and “provides "the signals necessary the ECC polynomial. ie a computer selected cove control this path. With this device, @ lower total that will ‘correct B-bit_ single burst errors. After pert count ean "be achieved with the ame or greater. performance Processor design. than thet of @ bit slice Because the Winchester Controller Chip controls primarily the high speed signals associated with the Winchester disk, the designer Is. free to choose "which type of drive to. interface, e.8. ‘51506, ANSI, SMD, etc. Each of these interfaces can be accommodated with the 4 signal pins ROSE, WAGE," ROGF, "and WREF. An example of an ST5O6 application "Is. shown in the diagram. ‘These & Eignals are Used to read or write drive control tines. The basic read/write and format sequences are Gescrived in the following pages. Note that for the read or write operations a match between the Cylinder, head, and sector registers and 1D field Being read. must occur before the operation Continues. If" a. match doesnot occur, the operation will stop” and_must_be restarted! until the error pattern Is determined, it the data byte (bytes) ig ExORed with Tn the RAM buffer. The flag byte of the 1D field Is used for Setective sector handling. When an ID field is read, the flag register and the flag byte from the 'gisk’ are not compared. The flag byte is puthed onto. the LIF. stack along. with the Cylinder ead and sector. ‘The flag byte ean be Ute to implement. one of the meny defect handling schemes the control unit designer deems ClkA, CIkB and Dataxfer outputs are used to Control the external RAM. buffer address counter Gnd long. with RG and WG. generate the CS and WE signals ‘to the RAM. ClkB should be interpre- ted as the beginning of = Controller Chip menery access with a Clock A. period equal to the RAM Recess time. ‘The D(O-?) pins will contain. valic Gata during that time of ‘the cycle when CIKA. IsREGISTER ASSIGNMENT ‘decoded by the chip. These registers are Intended to be memory mapped In an address. block XX50 0 The Winchester Controller Chip has register XXFF. ‘The upper byte ‘of the addrese is decoded Address locations between §0 hex and FF hex. to provide the chip select function. Table 1 gives Most of these locations are not used; however, @ summary ‘of the registers, and their functions, Unused locations ‘above sddress 70 must not be Following the table is a detailed discussion of Used by the system since they are not fully these functions. REG. Time REREAD; WeWRITE FUNCTION 50 Butter cat B/W Buffer data access 31 Date Bus B/W Host. Com cE Driv intr o B/W Drive oF Driv Inte Y Fw Drive Interface Port 1 % Not Uses n ECC Controt w ECC correction contro! n Ecc 0-23 R ECC syndrome Bits, 2 ECC 24-31 R ECC ERR pattern Es ECC POLY W Low Order Bits n ECC POLY w High Order Bits 7% OP Command W Read/Write sequence contro! 2 Start OP/Stat B/W Operation Status © Go bits m OP "Modifier FW Operation Modifiers 7 Spectal 1/0, R Input & Date transfer bits a Pop Stack R LIFO stack Reag 0 Gap 1&3 Len w S-bit Gap! & Gap3 Length FO Cylinder yw Block address Cyi byte et Head aw Block address Head byte 2 Sector aw Block address Sector byte 53 Fiag Rw Block address Flag byte aL Search bit w Enables Search Co. co Length Sector w Programmable Sector Length TABLE 1 ‘57-806 Application