module counter(

input CLK,
input RST,
input UPDN,
output reg [7:0] Q_OUT= 8'h00
);
reg [26:0] inp= 27'h0000000;
always @ (posedge CLK)
if (RST)
begin
Q_OUT <= 8'h00;
inp <= 27'h0000000;
end
else if (inp <= 27'h5F5E100)
inp <= inp+1;
else if (UPDN)
begin
inp <= 27'h0000000;
Q_OUT <= Q_OUT+1;
end
else
begin
inp <= 27'h0000000;
Q_OUT <= Q_OUT-1;
end

endmodule