Assignment 3

EC104 - Introduction to Digital Circuits

August 30, 2009
Q1 A possible definition of a BUT gate is Y1 is 1 if both A1 and B1 are
1 but either A2 or B2 is 0; Y2 is defined symmetrically. Write the
truth table and find minimal sum-of-products expressions for the BUT
gate outputs. Draw the logic diagram for a NAND-NAND circuit for the
expressions. BUT gate has four inputs A1, A2, B1 and B2 & two outputs
Y1 and Y2.
P
Q2 Butify the function F (w, x, y, z) =
(5, 7, 10, 11, 13, 14). That is, show
how to perform F with a single BUT gate as defined in previous question
and a 2-input OR gate.
Q3 Suppose that you are asked to design a new component, a decimal decoder
that is optimized for application in which only decimal input combination
are expected to occur. How can the cost of such a decoder be minimized
compared to one that is simply a 4-to-16 decoder with six outputs removed? Write the logic equations for all ten outputs of the minimized
decoder, assuming active high inputs and outputs and no enable inputs.
Q4 How many Karnaugh maps would be required to complete previous question using the formal multiple-output minimization procedure.
Q5 Tabulate the PLA programming table for the following Boolean functions
after minimizing
Pthe number of product terms:
a. A(x, y, z) = P(1, 2, 4, 6)
b. B(x, y, z) = P (0, 1, 6, 7)
c. C(x, y, z) = P(2, 6)
d. D(x, y, z) = (1, 2, 3, 5, 7)
Q6 List the PAL programming table for the BCD-to-excess-3-code converter.