IC-UNICAMP

MC 602
IC/Unicamp
2011s2
Prof Mario Crtes

VHDL
Mquina de Estados (FSM)

MC602 2011

IC-UNICAMP

Tpicos

Mquinas de estados
Moore
Mealy

Dois templates para implementao em VHDL

MC602 2011

IC-UNICAMP

Forma geral de um circuito sncrono

Combinational
circuit

Flip-flops

Combinational
circuit

Clock

MC602 2011

Mquina de Moore

IC-UNICAMP

Reset
w = 1
Az= 0

w = 0

Bz = 0
w = 0
w = 1

w = 0

Cz = 1

z=1 se w=1 nos dois ltimos ciclos de clock

z=0 caso contrrio
Clockcycle:
w:
z:
MC602 2011

t0
0
0

t1
1
0

t2
0
0

t3
1
0

t4
1
0

w = 1

t5
0
1

t6
1
0

t7
1
0

t8
1
1

t9
0
1

t10
1
0
4

Diagrama de Estados
IC-UNICAMP

Rese
t
w= 1
w= 0

A z = 0

B z = 0
w= 0
w= 1

w= 0

C z = 1

w= 1

MC602 2011

Next state
Present
state w = 0 w = 1
A
B
C

A
A
A

B
C
C

Output
z

0
0
1

Implementao

IC-UNICAMP

Y1

y1

Combinational
circuit

Combinational
circuit
Y2

y2

Clock

MC602 2011

FSM de Moore
IC-UNICAMP

Reset
w= 1
w= 0

B z=0
w= 0

USE ieee.std_logic_1164.all;
ENTITY simple IS
PORT (Clock, Resetn, w : IN
z
: OUT
END simple;

A z=0

w= 1

w= 0
C z=1

STD_LOGIC;
STD_LOGIC );

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C); --SIGNAL y : State_type;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN -- A
y <= A;
ELSIF (Clock'EVENT AND Clock

w= 1

Tipo Enumerado para

definir os Estados

o estado inicial
= '1') THEN

cont ...
MC602 2011

FSM de Moore
IC-UNICAMP

CASE y IS
WHEN A =>
IF w = '0
THEN y <= A;
ELSE y <= B;
END IF;
WHEN B =>
IF w = '0
THEN y <= A;
ELSE y <= C;
END IF;
WHEN C =>
IF w = '0'
THEN
y <= A;
ELSE
y <= C;
END IF;
END CASE;
END IF;
END PROCESS;
z <= '1' WHEN y = C ELSE '0';
END Behavior;

MC602 2011

Reset
w= 1
w= 0

A z=0

B z=0
w= 0
w= 1

w= 0
C z=1
w= 1

IC-UNICAMP

FSM de Moore - Simulao

Reset
w= 1

w= 0

A z=0

B z=0
w= 0
w= 1

w= 0
C z=1
w= 1

MC602 2011

IC-UNICAMP

FSM de Moore
Codificao Alternativa (2 processos)
Reset
w= 1
w= 0

A z=0

USE ieee.std_logic_1164.all;

B z=0
w= 0
w= 1

w= 0

ENTITY simple IS
PORT (Clock, Resetn, w : IN
z
: OUT
END simple;

C z=1

STD_LOGIC;
STD_LOGIC );

w= 1

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C);
SIGNAL y_present, y_next : State_type;

MC602 2011

10

IC-UNICAMP

FSM de Moore
Codificao Alternativa (2 processos)
Reset

BEGIN
PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0'
y_next
ELSE
y_next
END IF;
WHEN B =>
IF w = '0'
y_next
ELSE
y_next
END IF;
MC602 2011

w= 1
w= 0

A z=0

B z=0
w= 0
w= 1

w= 0
C z=1

THEN
<= A;

w= 1

<= B;

THEN
<= A;
<= C;

11

FSM de Moore - Codificao Alternativa

IC-UNICAMP

WHEN C =>
IF w = '0' THEN
y_next <= A;
ELSE
y_next <= C;
END IF;
END CASE;
END PROCESS;

Reset
w= 1
w= 0

A z=0

B z=0
w= 0
w= 1

w= 0
C z=1
w= 1

PROCESS (Clock, Resetn)

BEGIN
IF Resetn = '0' THEN
y_present <= A;
ELSIF (Clock'EVENT AND Clock = '1') THEN
y_present <= y_next;
END IF;
END PROCESS;
z <= '1' WHEN y_present = C ELSE '0';
END Behavior;
MC602 2011

12

Resumo alternativas prx estado: Moore

IC-UNICAMP

PROCESS ( Resetn, Clock )

BEGIN
IF Resetn
y <= A;
ELSIF (Clock'EVENT AND
Clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0
THEN y <= A;
ELSE y <= B;
END IF;
WHEN B =>
..
END CASE;
END PROCESS;

MC602 2011

PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN
y_next <= A;
ELSE
y_next <= B;
END IF;
WHEN B => .
END CASE;
END PROCESS;
PROCESS (Clock, Resetn)
BEGIN
IF Resetn .
y_present <= A;
ELSIF (Clock'EVENT AND
Clock = '1') THEN
y_present <= y_next;
END IF;
END PROCESS;
13

IC-UNICAMP

FSM - Especificando a Atribuio de

Estados

ARCHITECTURE Behavior OF simple IS

TYPE State_TYPE IS (A, B, C);
ATTRIBUTE ENUM_ENCODING : STRING;
ATTRIBUTE ENUM_ENCODING OF State_type: TYPE IS "00 01
11";
SIGNAL y_present, y_next : State_type;
BEGIN
cont ...
Obs: Atributo Enum_Encoding especfico da ferramenta Quartus. Esta
soluo pode no funcionar em outras ferramentas CAD
MC602 2011

14

IC-UNICAMP

FSM - Especificando a Atribuio de

Estados

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY simple IS
PORT ( Clock, Resetn, w : IN
STD_LOGIC;
z
: OUT STD_LOGIC );
END simple;
ARCHITECTURE Behavior OF simple IS
SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT A
: STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT B
: STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT C
: STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
BEGIN
PROCESS ( w, y_present )
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN y_next <= A;
ELSE y_next <= B;
END IF;
cont

MC602 2011

15

IC-UNICAMP

FSM - Especificando a Atribuio de

Estados
WHEN B =>
IF w = '0' THEN y_next <= A;
ELSE y_next <= C;
END IF;
WHEN C =>
IF w = '0' THEN y_next <= A;
ELSE y_next <= C;
END IF;
WHEN OTHERS =>
y_next <= A;
END CASE;
END PROCESS;
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
y_present <= A;
ELSIF (Clock'EVENT AND Clock = '1') THEN
y_present <= y_next;
END IF;
END PROCESS;
z <= '1' WHEN y_present = C ELSE '0';

END Behavior;
MC602 2011

16

Mquina de Mealy
IC-UNICAMP

Reset
w= 1z= 0
w= 0z= 0

w= 1z= 1

w= 0z= 0

MC602 2011

17

FSM de Mealy

IC-UNICAMP

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mealy IS
PORT (Clock, Resetn, w : IN
z
STD_LOGIC );
END mealy;

STD_LOGIC;
: OUT

cont

MC602 2011

18

IC-UNICAMP

FSM de Mealy

Reset
ARCHITECTURE Behavior OF mealy IS
w= 1 z=0
TYPE State_type IS (A, B);
w= 0 z=0
A
B
SIGNAL y : State_type;
w= 0 z=0
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= A;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN y <= A;
ELSE y <= B;
END IF;
WHEN B =>
IF w = '0' THEN y <= A;
ELSE y <= B;
END IF;
END CASE;
END IF;
END PROCESS;
cont

MC602 2011

w= 1 z=1

19

FSM de Mealy
IC-UNICAMP
Reset
w= 1 z=0
w= 0 z=0

PROCESS ( y, w )
BEGIN
CASE y IS
WHEN A =>
z <= '0';
WHEN B =>
z <= w;
END CASE;
END PROCESS;
END Behavior;

MC602 2011

w= 1 z=1

w= 0 z=0

20