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Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\ivan12\desktop\dec_cod\run_options.txt
Written on Tue Oct 14 17:16:57 2014

#project files
add_file -vhdl -lib work "./dec_cod.vhd"

#implementation: "dec_cod"
impl -add dec_cod -type fpga
#device options
set_option -technology ispGAL
set_option -part ispGAL22LV10
set_option -package LJ
set_option -speed_grade -4
set_option -part_companion ""
#compilation/mapping options
set_option -top_module "DEC_COD"
# mapper_options
set_option -frequency 1
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Lattice ispLSI1K/1KE
set_option -disable_io_insertion 0
set_option -RWCheckOnRam 1
# Lattice ispGAL
set_option -areadelay 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./DEC_COD.edi"
#set log file
set_option log_file "C:/users/ivan12/desktop/dec_cod/dec_cod.srf"
impl -active "dec_cod"