Algoritmos

Diseo de Sistemas con FPGA

Cuenta Ceros, versin en C

int cuentaceros(int a[8])
{
int count,i;
count=0;
for(i=0;i<8;i++)
{
if(a[i]) count=count+1;
}
return count;
}

Cuenta Ceros, versin en C y en Verilog

int cuentaceros(int a[8])
{
int count,i;
count=0;
for(i=0;i<8;i++)
{
if(a[i]) count=count+1;
}
return count;
}

module cuentaceros (
int [7:0] a,
output reg[2:0] Count
);
integer i;
always @*
begin
Count= 3'b0;
for (i = 0; i < 8; i = i+1)
begin
if (!a[i])Count= Count+1;
end
end
endmodule

Cuenta Ceros
module cuentaceros (
int [7:0] a,
output reg[2:0] Count
);
integer i;
always @*
begin
Count= 3'b0;
for (i = 0; i < 8; i = i+1)
begin
if (!a[i])Count= Count+1;
end
end
endmodule

Synthesizing Unit <cuentaceros>.

Related source file is "cuentaceros.v".
Found 3-bit adder for signal
<Count$addsub0000> created at line 34.
Found 3-bit adder for signal
<old_Count_2$addsub0000> created at line 34.
Found 3-bit adder for signal
<old_Count_3$addsub0000> created at line 34.
Found 3-bit adder for signal
<old_Count_4$addsub0000> created at line 34.
Found 3-bit adder for signal
<old_Count_5$addsub0000> created at line 34.
Found 3-bit adder for signal
<old_Count_6$addsub0000> created at line 34.
Found 3-bit adder for signal
<old_Count_7$addsub0000> created at line 34.
Summary:
inferred 7 Adder/Subtractor(s).
Unit <cuentaceros> synthesized.

Que pas?
Que el for de C es secuencial en el tiempo, y el
de Verilog es en rea!
Es decir, la semntica es distinta!
Lo mismo ocurre con las funciones que tambin
existen en Verilog. Dos invocaciones significa dos
reas ocupadas con la misma funcin.
Ojo! XST infiere hardware para estas
construcciones, pero tenemos que tener muy
claro lo que queremos hacer.

Otra versin en Verilog

module countzeros (
input [7:0] a,
input clk,
input reset,
output reg[2:0] Count
);
reg [2:0] count_reg, count_next;
reg [7:0] a_reg,a_next
always @(posedge clk)
begin
if (reset)
begin
a_reg<=a;
count_reg<=3'b0;
end
else
begin
a_reg<=a_next;
count_reg<=count_next;
end
end

always @ *
begin
a_next = a_reg << 1;
if (a[0]==0)
count_next=count_reg + 1 ;
else
count_next=count_reg;
end
assign count=count_reg;
endmodule

Otra versin en Verilog

Hacer el cuentaceros con una mquina de
estados.

done

cuenta
clk
start