SUMADORES

DISEO DE UN SUMADOR MEDIO

-- Declaracin de la Entidad de un Sumador Medio.
entity HA is
Port (A : in bit;
B : in bit;
Co : out bit;
S : out bit);
end HA;
-- Declaracin de la Arquitectura de un Sumador Medio.
architecture HA_arch of HA is
begin
S <= A xor B;
Co <= A and B;
end HA_arch;
________________________________________________________________________________

DISEO DE UN SUMADOR COMPLETO

-- Declaracin de la Entidad de un Sumador Completo.
entity FA is
Port ( A : in bit;
B : in bit;
Ci : in bit;
Co : out bit;
S : out bit);
end FA;
-- Declaracin de la Arquitectura de un Sumador Completo.
architecture FA_arch of FA is
begin
S <= A xor B xor Ci;
Co <= (A and B) or (A and Ci) or (B and Ci);
end FA_arch;
________________________________________________________________________________

DISEO DE UN SUMADOR COMPLETO CON INSTANCIACIN

-- Declaracin de la Entidad de un Sumador Completo.
entity FA is
Port (A : in BIT;
B : in BIT;
Ci : in BIT;
Co : out BIT;
S : out BIT);
end FA;
-- Declaracin de la Arquitectura de un Sumador Completo.
architecture FA_Arch of FA is
signal S0, Co0, Co1: bit;
component HA is -- componente ya compilada
port(A,B: in bit;
Co,S: out bit);
end component;
begin
HA0: HA port map ( A, B, Co0, S0); -- instanciacin del primer sumador
HA1: HA port map ( S0, Ci, Co1, S); -- instanciacin del segundo sumador
Co <= Co0 or Co1;
end FA_Arch;
________________________________________________________________________________

DISEO DE UN SUMADOR COMPLETO DE 2 BITS CON INSTANCIACIN

entity FA2 is
port ( A : in BIT_VECTOR (1 downto 0);
B : in BIT_VECTOR (1 downto 0);
Ci: in bit;
Co : out BIT;
S : out BIT_VECTOR (1 downto 0)
);
end FA2;
architecture FA2_Arch of FA2 is
signal C: bit_vector (1 downto 0);
component FA is
port(A,B,Ci: in bit;
Co, S: out bit);
end component;

-- componente ya compilada

begin
sum0: FA port map(A(0), B(0), Ci, C(0), S(0));
sum1: FA port map(A(1), B(1), C(0), C(1), S(1));
Co <= C(1);
end FA2_Arch;
________________________________________________________________________________

DISEO DE UN SUMADOR COMPLETO DE 4 BITS CON INSTANCIACIN

entity FA4 is
port ( A : in BIT_VECTOR (3 downto 0);
B : in BIT_VECTOR (3 downto 0);
Co : out BIT;
S : out BIT_VECTOR (3 downto 0)
);
end FA4;
architecture FA4_Arch of FA4 is
signal cero: bit;
signal C: bit_vector (3 downto 0);
component FA is
port(A,B,Ci: in bit;
Co, S: out bit);
end component;

-- componente ya compilada

begin
cero <= '0';
sum0: FA port
sum1: FA port
sum2: FA port
sum3: FA port
Co <= C(3);

map(A(0),
map(A(1),
map(A(2),
map(A(3),

B(0),
B(1),
B(2),
B(3),

cero, C(0), S(0));

C(0), C(1), S(1));
C(1), C(2), S(2));
C(2), C(3), S(3));

end FA4_Arch;
________________________________________________________________________________