Está en la página 1de 2

CODIGO VHDL DEL CONTROLADOR DEL

SISTEMA
library ieee;
use ieee.std_logic_1164.all;
entity controlador is
port( y_pr: in std_logic_vector(3 downto 0);
y_sg: out std_logic_vector(3 downto 0);
star: in std_logic;
copr: in std_logic;
o1 : in std_logic;
c30 : in std_logic;
ccom: in std_logic;
cret: in std_logic;
cma0: in std_logic;
list: in std_logic;
cont: in std_logic;
restt: out std_logic;
reR30: out std_logic;
enLOP: out std_logic;
en30 : out std_logic;
enS2A: out std_logic;
enS1 : out std_logic;
reL : out std_logic;
enR : out std_logic;
div : out std_logic;
enSal: out std_logic);
end entity;
architecture bady of controlador is
begin
process(y_pr, star, copr, o1, c30, ccom, cret, cma0, list, cont)
begin
case y_pr is
when "0000" => if star='0' then y_sg<="0000"; else
y_sg<="0001"; end if;
when "0001" => if copr='0' then y_sg<="0011";
elsif cma0='0' then y_sg<="0000";
elsif cma0='1' then y_sg<="0101"; end if;
when "0011" => y_sg<="1011";
when "1011" => if o1='0' and c30='0' then y_sg<="1011";
elsif o1='0' and c30='1' then
y_sg<="1100";
elsif o1='1' and ccom='1' then
y_sg<="1001";
elsif o1='1' and ccom='0' then
y_sg<="1100"; end if;
when "1001" => y_sg<="1101";

when "1101" => y_sg<="1100";


when "1100" => if cont='0' then y_sg<="1100"; else
y_sg<="0001"; end if;
when "0101" => y_sg<="0111";
when "0111" => if list='0' then y_sg<="0111"; else
y_sg<="0110"; end if;
when "0110" => if cont='0' then y_sg<="0110"; else
y_sg<="0000"; end if;
when others => y_sg<="0000";
end case;
end process;
restt <= '0' when y_pr="0000" else '1';
reR30 <= '0' when (y_pr="0000" or y_pr="0001") else '1';
enLOP <= '1' when y_pr="0011" else '0';
en30 <= '1' when y_pr="1011" else '0';
enS2A <= '1' when y_pr="1001" else '0';
enS1 <= '1' when y_pr="1101" else '0';
reL <= '0' when (y_pr="1100" or y_pr="0000") else '1';
enR <= '1' when y_pr="1100" else '0';
div <= '1' when y_pr="0101" else '0';
enSal <= '1' when y_pr="0110" else '0';
end bady;

También podría gustarte