Samsung - T370HW02 Ve Bn07 00644a Memc T Con - SCH PDF

5
U2811
D0004
TP1978
TP2820
TP2821
TP1982
TP1981
TP1983
SW_PVCC
R105
2
CIS
BD103
CIS
CIS
R101
C107
1
2
3
4
CIS
IC101
S
S
S
G
D
D
D
D
8
7
6
5
B12V
B0005
C0022
V12
PANEL_VCC
B3.3VD
F0002
Close to J1
CISCN2615
B12V
B3.3VD
GND
PANEL_VCC
C0021
J5
R0062
Close to U300
RN002
RXINCLKCP
RXINCLKCN
RXINCP[0..4]
RXINCN[0..4]
NC
12Vin
RN003
CIS
RXINCLKAP
RXINCLKAN
RXINAP[0..4]
RXINAN[0..4]
C0009
YDIOU
YOE
YOE
YDIOU
YCLK
YDIOD
XSTB_M
YCLK_M
XPOL_M
YOE_M
04.TCON_M
R0055
R0053
YV1C
R0056
MAIN_CHECK
HSYNC
SW_PVCC
CIS
MGND2
MGND1
I2C_SDA
I2C_SCL
FRC_NRESET
WP
R104
Q101
12Vin1
I2C_SDA
I2C_SCL
NC
CIS
CIS
4
3
2
1
R0633
NC
EDID_WP
R0604
SCL R2760_DE
SDA R2761_DE
FRC_RST CIS
R657
PVCC CIS R2770
M_CHECKCIS R2765
NC
NC
HSYNC_F R2763
AG CIS R2766
CIS
CIS
YOE_M
YV1C_M
V3D3
V1D2
YOE3_M
YOE4_M
RST
AGBSEN
LVDSORD
Close to U401
C502
4
3
2
1
G
R656CIS
CIS
R658
HSYNC
AGING
Q0602
D0006
C0024
YDIOD
YDIO_M
R0027
T2_RVP[4..6]
NC
C0012
YDIO_M R0066
C0013
YCLK_M
C0014
R0033
R0018
YOE3_M
YOE4_M
RST
high Aging
Path balance between U300 &U401
VGHC
R544
CN901
G2
G1
V3D3
R0094
R0634
R0010
R0615
EDID_WP
SCL_I
SDA_I
Model Name
Date:
1
PAD
PAD
PAD
1
PAD
GH1
GH2
D0002
R0052
D0003
R0025 AGING
R0054
C0017
R0051
R539_DE
LVDS_FORMAT
V3D3
EDID_WP
SCL_I
SDA_I
8
7
6
5
GH6
GH9
GH7
GH11
I2C_SCL
I2C_SDA
VCC
A0
WP
A1
SCL
A2
SDA GND
U0106
Size
Document Number
Custom
T315HW02
Wednesday, October 01, 2008
Sheet
YCLK
RXINDP[0..4]
YOE
YDIOD
M_VCOMI2
YDIOU
YCLK
XVCC
M_VCOMI2
PAD
VGL
XVCC
T2_LVCLKP
T2_LVCLKN
T2_LVP[0..2]
T2_LVN[0..2]
VGHC
VGL
AGBSEN
LVDSORD
RXCLKDP
RXCLKDN
T2_LVP[4..6]
VCOMF2
VGHC
R0060
T2_LVN[4..6]
T2_RVN[0..2]
XHAVDD
R0057
RXINDP[0..4]
T2_RVP[0..2]
T2_RVN[0..2]
XHAVDD
NC
T2_RVP[0..2]
T2_RVCLKP
T2_RVCLKN
T2_RVP[4..6]
T2_RVN[4..6]
XSTB
XPOL
T1_LVN[0..2]
T1_LVP[0..2]
XHAVDD
XAVDD
T2_LVP[0..2]
T2_LVN[0..2]
T2_LVN[4..6]
T2_LVP[4..6]
VGMA22
VGMA21
VGMA19
VGMA17
VGMA15
VGMA13
VGMA12
VGMA11
VGMA10
VGMA8
VGMA6
VGMA4
VGMA2
VGMA1
T1_LVN[0..2]
T1_LVP[0..2]
T1_LVN[4..6]
T1_LVP[4..6]
PAD
PAD
XVCC
XVCC
T2_RVP0
T2_RVN0
T2_RVP1
T2_RVN1
T2_RVP2
T2_RVN2
T2_RVCLKP
T2_RVCLKN
T1_RVP0
T1_RVN0
T1_RVP1
T1_RVN1
T1_RVP2
T1_RVN2
T2_RVP4
T2_RVN4
T2_RVP5
T2_RVN5
T2_RVP6
T2_RVN6
T1_RVCLKP
T1_RVCLKN
T1_RVP4
T1_RVN4
T1_RVP5
T1_RVN5
T1_RVP6
T1_RVN6
YDIOU
YCLK
U_DF
YOE
YDIOD
M_VCOMI2
VGL
VGHC
VCOMF2
XPOL
XSTB
XDIOF
T2_LVP0
T2_LVN0
T2_LVP1
T2_LVN1
T2_LVP2
T2_LVN2
T2_LVCLKP
T2_LVCLKN
T1_LVP0
T1_LVN0
T1_LVP1
T1_LVN1
T1_LVP2
T1_LVN2
T2_LVP4
T2_LVN4
T2_LVP5
T2_LVN5
T2_LVP6
T2_LVN6
T1_LVCLKP
T1_LVCLKN
T1_LVP4
T1_LVN4
T1_LVP5
T1_LVN5
T1_LVP6
T1_LVN6
G2
G1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V1D2
1
R0050
RXINDN[0..4]
T1_LVP[0..2]
T1_LVN[0..2]
T1_LVCLKN
T1_LVCLKP
T2_RVN[0..2]
T2_RVP[0..2]
T1_RVN[0..2]
T1_RVP[0..2]
XAVDD
J4
R0059
R0041
R0058
R0061
RXINBP[0..4]
R0039
RXINCP[0..4]
RXINDN4
RXINDP4
RXINBN[0..4]
RXINDN3
RXINDP3
RXINCN[0..4]
RXCLKDN
RXCLKDP
High Aging
RXINDN2
RXINDP2
GND
EXSCL
EXSDA
RXINDN[0..4]
RXINDP[0..4]
RXINCLKDN
RXINCLKDP
SCL_I
SDA_I
RXINDN1
RXINDP1
RST
XOUT_M
RXINDN[0..4]
RXINDP[0..4]
XOUT_M
PI_EVEN_RIN4N
PI_EVEN_RIN4P
R0071
R0023
YV1C_M
V3D3
V1D2
RXINDN0
RXINDP0
YOE4_S
R0015
PI_EVEN_RINCLKN
PI_EVEN_RINCLKP
PI_EVEN_RIN3N
PI_EVEN_RIN3P
NC
RXCLKBP
Close to U401
R0070
R0014
YOE3_S
XSTB_M
XPOL_M
RXCLKBN
NC
R0013
RXINBP[0..4]
YCLK_S
RXINBN[0..4]
PAD YOE_S
YV1C
T1_RVP[4..6]
R0043
AGBSEN
LVDSORD
YV1C_S
V3D3
V1D2
T2_RVN[4..6]
PI_EVEN_RIN2N
PI_EVEN_RIN2P
R0040
RST
PAD
T2_RVCLKP
PI_EVEN_RIN1N
PI_EVEN_RIN1P
RN001
RXCLKCP
T1_LVCLKP
VCOMF2
C106
NC
T1_LVCLKN
XAVDD
CIS
C178
T1_LVN[4..6]
T1_LVP[4..6]
XAVDD
CIS
C177
R0042
YOE_S1
YDIO_S
PI_EVEN_RIN0N
PI_EVEN_RIN0P
03.TCON_S
YOE4_S
YCLK_S
1
PAD
T2_RVCLKN
RXINBN4
RXINBP4
R0049
RXCLKCN
T1_LVP[4..6]
XPOL
XSTB
I2C_SDA
CIS
XPOL XSTB
PI_ODD_RIN4N
PI_ODD_RIN4P
R0044
YOE3_S
YDIO_S
1
1
RXCLKBN
RXCLKBP
RXINBN3
RXINBP3
R0045
PAD
PI_ODD_RINCLKN
PI_ODD_RINCLKP
PI_ODD_RIN3N
PI_ODD_RIN3P
R0047
T1_LVN[4..6]
YV1C
RXINBN2
RXINBP2
RXINAN[0..4]
RXINBN[0..4]
RXINBP[0..4]
RXINAP[0..4]
U300
RXINBN1
RXINBP1
R0046
RXINCP[0..4]
YOE_S
I2C_SCL
B12V
RXINCN[0..4]
XPOL_S
RXINBN[0..4]
RXINBP[0..4]
RXINCLKBN
RXINCLKBP
YCLK_S
PI_ODD_RIN2N
PI_ODD_RIN2P
C0008
RXINBN0
RXINBP0
VGL
Normal / Mirror Setting Table
PAD
TP1979
XHAVDD
XSTB
XPOL
XDIOB
G2
G1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
X-BACK/Right
PAD
TP2819
PAD
TP2818
XSTB_S
PI_ODD_RIN1N
PI_ODD_RIN1P
R0048
YDIO_S
PI_ODD_RIN0N
PI_ODD_RIN0P
XHAVDD
DP4
U_DB
DN4
U_DF
Mirror
WP_E
DP3
T1_RVN[4..6]
T2_RVP[4..6]
YDIOD
Normal
CIS
1
2
3
4
5
6
7
8
9
PI_ODD_RIN0N
10
PI_ODD_RIN0P
11
PI_ODD_RIN1N
12
PI_ODD_RIN1P
13
PI_ODD_RIN2N
14
PI_ODD_RIN2P
15
16
PI_ODD_RINCLKN
17
PI_ODD_RINCLKP
18
19
PI_ODD_RIN3N
20
PI_ODD_RIN3P
21
PI_ODD_RIN4N
22
PI_ODD_RIN4P
23
24
PI_EVEN_RIN0N
25
PI_EVEN_RIN0P
26
PI_EVEN_RIN1N
27
PI_EVEN_RIN1P
28
PI_EVEN_RIN2N
29
PI_EVEN_RIN2P
30
31
PI_EVEN_RINCLKN
32
PI_EVEN_RINCLKP
33
34
PI_EVEN_RIN3N
35
PI_EVEN_RIN3P
36
PI_EVEN_RIN4N
37
PI_EVEN_RIN4P
38
39
40
41
42
43
44
LVDS_FORMAT
45
46
47
48
49
50
51
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
DN3
T2_RVN[4..6]
XVCC
YDIOU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
V1D2
EXSCL
EXSDA
AGBSEN
SCL_GA1
LVDSORD
SCL_I
SDA_I
XVCC
B0001
V3D3
XIN_S
SDA_GA1
RXINCN3
RXINCP3
RXINCN4
RXINCP4
VGHC
T1_RVN[4..6]
U_DB
MGND1
MGND2
CLKDP
T1_RVP[4..6]
VGMA22
VGMA21
VGMA19
VGMA17
VGMA15
VGMA13
VGMA12
VGMA11
VGMA10
VGMA8
VGMA6
VGMA4
VGMA2
VGMA1
VCOMF
VCOMF2
VGHC
VGL
M_VCOMI2
YDIOD
YOE
U_DB
YCLK
YDIOU
XVCC
G1
G2
CLKDN
1
2
3
4
DP2
RXINCN[0..4]
RXINCP[0..4]
RXCLKCN
RXCLKCP
XIN_S
YV1C
YV1C_S
RXINCN2
RXINCP2
C0011
C0010
RXINCN1
RXINCP1
PAD
PAD
YV1C_S
PAD
DN2
C0007
1
XPOL_S
RXINCN0
RXINCP0
PANEL_VCC
3
VGL
XPOL_S PAD
XSTB_S
XAVDD
1
RXCLKAP
B0002
PAD
RXCLKAN
XSTB_S
RXINAN4
RXINAP4
Close to J3,J4
RXINAN3
RXINAP3
T1_RVN[4..6]
T1_RVP[0..2]
T1_RVCLKP
T1_RVN[0..2]
NCR0063
DP1
PAD
DN1
T1_RVCLKN
RXINAP[0..4]
VCOMF2
RXINAN[0..4]
01.Gamma
DP0
XPOL
XSTB
RXINAN2
RXINAP2
VGMA[1..22]
T1_RVP[4..6]
VCOMF
RXINAN1
RXINAP1
VGMA[1..22]
Close to J4
DN0
RXINAN[0..4]
RXINAP[0..4]
RXCLKAN
RXCLKAP
GND
RXINAN0
RXINAP0
B0004
PAD
CP4
C0006
SDA_E
V3D3
PAD
C0003
PAD
C0005
C0004
FRC_RST
PAD
C0002
PAD
RXINAP4
CN4
PAD
C0001
AVDD
SCL_E
RXINCP4
AP4
PAD
BP4
PAD
NC
LVDS_FORMAT 1
RXINBP4
YCLK
YDIOU
YDIOD
YOE
R0022
1
2
3
4
TP1993
PAD
AN4
PAD
R0036
PAD
RXINDP4
RXINAN4
CP3
PAD
AP3
PAD
NCR0038
PAD
TP1994
1
TP1989
1
TP1990
WP_E
TP1991
HSYNC_F
TP1992
1
RXINAP3
CN3
PAD
VCOMF2
Close to J4
PAD
TP1987
TP1988
TP1985
RXINCN4
AN3
PAD
HAVDD
AG
TP1986
U2810
PAD
BN4
PAD
RXINCP3
RXINAN3
CLKCP
PAD
NCNC
M_CHECK
TP1995
1
TP1996
SDA
RXINBN4
BP3
PAD
VGMA[1..22]
PAD
TP1999
PAD
RXINBP3
RXINCN3
SCL_GA
SDA_GA
V3D3
VCOMF
R0021
RXINDN4
PAD
BN3
PAD
YV1C
V3D3
SCL_GA
SDA_GA
AVDD
NC
PVCC
TP2000
PAD
RXINBN3
PAD
PAD
TP2003
RXINDP3
PAD
RXCLKAP 1
PAD
SCL_I
SDA_I
R0092
PAD
TP2004
1
CLKBP
RXINDN3
CLKBN
CLKAP
PAD
RXCLKCP 1
VGL
VGHC
AVDD
M_VCOMI2
SCL
PI_ODD_RIN4P 1
PAD
AVDD
HAVDD
PAD
PI_ODD_RIN4N 1
RXCLKBP 1
PAD
PAD
PAD
PANEL_VCC
PAD
PAD
CLKCN
PAD
PAD
PI_EVEN_RIN4P 1
TP2005
RXCLKDP 1
RXCLKAN 1
CP2
PAD
RXINAP2
CN2
PAD
PAD
CLKAN
PAD
RXCLKCN 1
RXINCP2
RXINAN2
CP1
PAD
PAD
R0037
PI_EVEN_RIN4N1
PI_ODD_RIN3P 1
TP2006
PAD
BP2
PAD
RXINAP1
AP2
PAD
R0091
PAD
RXCLKBN 1
BN2
PAD
RXINCN2
RXINAN1
CN1
PAD
AN2
PAD
RXINBP2
BP1
PAD
RXINAP0
CP0
PAD
AP1
RXCLKDN 1
PAD
RXINBN2
RXINCP1
RXINCN1
RXINAN0
CN0
PAD
AN1
PAD
RXINDP2
PAD
PAD
RXINBP1
BN1
PAD
RXINCP0
AP0
PAD
RXINDN2
RXINBN1
BP0
PAD
RXINCN0
XVCC
PI_EVEN_RIN3P 1
PI_ODD_RIN3N 1
RXINDP1
PAD
RXINBP0
BN0
PAD
AN0
PAD
PI_ODD_RINCLKP
1
PAD
PAD
RXINDN1
PAD
RXINBN0
GND
PAD
PI_ODD_RINCLKN
1
PAD
RXINDP0
PAD
PI_EVEN_RIN3N1
PI_ODD_RIN2P 1
RXINDN0
PI_EVEN_RINCLKP
1
PAD
PAD
PI_ODD_RIN2N 1
PAD
TP2001
PI_EVEN_RINCLKN
1
PAD
PI_ODD_RIN1P 1
PAD
PAD
TP2002
PI_EVEN_RIN2P 1
PI_ODD_RIN1N 1
PAD
TP2007
PI_EVEN_RIN2N1
PAD
PI_ODD_RIN0P 1
TP2008
PI_EVEN_RIN1P 1
PAD
PAD
PI_ODD_RIN0N 1
TP2009
PI_EVEN_RIN1N1
PAD
TP2010
PI_EVEN_RIN0P 1
PI_EVEN_RIN0N1
J3
1
X-FRONT/Left
XVCC
U_DF
R0019
NC
R0020
Close to J3
D
VGMA[1..22]
XPOL
XSTB
R0064
M_VCOMI2
YDIOU
YCLK
YOE
YDIOD
U401
NC
NC
NC
C0015
NC
C
Close to U401
RST
R0001
GND
V3D3
C0026
Td(sec) = R() * C(F) * 0.79

=0.022u * 5.62M * 0.79 = 97mS
RXINDN[0..4]
Path balance between U300 &U401
GH3
GH4
V3D3
NC
R555_DE
GH10
NC
RN004
B
FRCBlock
GH8
GH5
HSYNC
MAIN_CHECK
SW_PVCC
R14_OP
R15_OP
CIS
B3.3VD
CIS
SCL_I
R0095
SDA_I
FRC_NRESET
NC
CIS
C111
R0635
R0028
1
2
3
4
R0093
R2764
A
SCL_E
SDA_E
SCL_I
SDA_I
FRC_NRESET
SW_PVCC
MAIN_CHECK
<Variant Name>
T315HW02 V3 Tcom MEMC Board
Top View
V3 Tcom\MEMC Board
1
of
10
Rev
EC02
AUO Confidential
80
J4
80
T-CON_1(Slave)
AUO-12401 B1
T-CON_2(Master)
AUO-12401 B1
U0300
1
U0401
1
J3
GAMMA
C
I2C Connector(4Pin)
CN901
DC-DC
FRC PART
[Page: FRC_IO,
FRC_DDR
and FRC_POWER]
DDR
1
IC500
DDR
4
1
Power Connector(4Pin)
51
LVDS Connector(51Pin)
CN2615
J1
<Variant Name>
Model Name
Placement
Size
C
Date:
5
Document Number
Rev
EC02
T315HW02 V3 Tcom\MEMC Board

1
Sheet
of
10
AVDD
SW
PANEL_VCC
D0201
PAD
R0221
Layout closely to IC, far from D201 and L201

TI65161: R201=127K; R203=10K; C206=120pF
BD8160: R201=127K; R203=10.2K;C206=200pF
NC
Vo1
15.730.08V
410mA(avg)/680mA(peak)
AVDD_F
AVDD
L0201
R0225
R0201
C0201
Q0201
D
C0202
R0220
C0203
C0204
C0213
C0214
C0215
C0216
C0217
C0218
C0206
R0202
C209: AVDD soft-start time control

TI65161: R213=0 ; C207=22n
BD8160: R213=7.5K; C207=2.2n
C201, C202 put closed to L201
U0201
C0209
R0212
C0207
R0213
FB
SS
COMP
GD
28
R0203
Vo1
OS
DLY2
27
GD
C0210
26
C210: AVDD and VGH delay time control

C211: VGL delay time control
C0208
Trace overlapping
SW
C0256
NC
NC NC
D0207
C
D0206
SW
DLY1
SW
REF
PGND
GND
PGND
AVIN
SUP
VINB
C0211
25
24
REF
C0212
23
22
C109 put closed to Pin 8

C
Vo1
PANEL_VCC
21
C0255
D0205
D0204
C0251
C0231
PANEL_VCC
R0230
EN2
VINB
DRP
NC
DRN
SWB
C0230
20
V3D3
C0252
C0257
VGL
REF
11
K
R0211
L0202
18
3.3V
Layout close to IC
R207
C0232
PAD
Current limit R to reduce inrush

current during YV1C switch
J
C0254
VGH
12
PANEL_VCC
FREQ
BOOT
V3D3_F
17
V3D3
V3D3
V1D2
R0222
VGL
D0202
R0208
13
FBN
EN1
FBP
FBB
16
PANEL_VCC
C0233
C234
PAD
C0258
C0253
R0204
C0235
R0262
Vin
Vout
R0205
V1D2
V1D2_F
U0204
GND
15
G1
G1
U0302
14
Layout closely to Pin13 and far from D203, D204, D205,D206 and D207
TI65161: R207=49.9K; R208=10K
BD8160: R207=61.2K; R208=10K
1.2V
1000mA(avg)
C0261
PAD
R0231
19
D0203
R0223
10
VGL
PAD
R0224
C237
V1D2
C238
2
3
NC
R0228
C0259
NC
C0260
R0252
R0251
R0250
R0253
R0254
R0255
11
GND
VFLK
VGHM
CD
SVGHM
RE
NC
VGH
VDPM
GND
R0227
R0209
VD
10
GND
GND
YV1C
Layout closely to pin15 and far from L202 and D202

TI65161: R204=191K; R205=110K; C235=10pF
BD8160: R204=191K; R205=110K; C235=68pF
9
R0210
C0275
C0270
VGHM
GND
VGH
250mA(avg)
VGHC
G1
GND
12
C0236
G1
R0257
AVDD
R0258
R0248
AVDD
Layout close to Pin14 and far from D203, D204, D205,D206 and D207
TI65161: R209=226K; R210=10.2K
BD8160: R209=226K; R210=10.2K
1/2 AVDD soft-start

U0208
1
C0263
2
PANEL_VCC
C0626
EN
BST
COMP
VIN
FB
SW
GND
close pin6
R0261
7
6
VFB=0.9V
R0259
R0260
C0271
C0268
G1
C0264
close pin7
SS
G1
R0249
PAD
HAVDD
MAX : 3.2 mm
7.020.1V
L0203
HAVDD_F
HAVDD
HAVDD
R0256
D0208
C0265
NCC0266
C0267
<Variant Name>
Model Name
DC-DC
Size
Document Number
Custom
T315HW02
Date:
5
Rev
EC02
V3 Tcom\MEMC Board
Sheet
of
10
VGMA_REF
PAD
AVDD
REFB1
R0107
Close to U103 pin38
Close to U103 pin32
R0106
GND
REF_F11
C0103
VG10
VGMA11
5
6
7
8
RN105
C0107
4
3
2
1
C0119
VG11
VGMA12
REFB12
C0108
AVDD
C0123
R0125
VCOMO
REFB1
VCOMF2
REF_F10
C0122
REFB22
REFB21
VG13
VGMA15
REFB15
C0110
8
VCOM_FB
10
AVDD
VDD_AMP
11
AGND
13
12
GMA0
10
GMA14
G1
28
G1
11
G1
U108B
U108C
12
13
U108D
C0120
REFB17
C0111
C0163
VCOMF
R0148
BANK_SEL
R0167
AVDD
NC
R0161
NCR0160
NC
AVDD_GA
Close to U103 pin47

REFB11
VG17
VGMA19
REFB19
R0166
R0168
R0162
R0159
C0161
V3D3
R0163
VG19
VGMA21
REFB21
R0158
C0160
PAD
R0155
PVGMA22
R0139
NC
R0154
VGMA22
PVGMA1
VGMA1
NC
PVGMA13
PVGMA12
PVGMA11
PVGMA10
1
2
3
4
NC
8
7
6
5
VGMA13
VGMA12
VGMA11
VGMA10
C0158
2
3
RN102
R0140
REF21
VDD
VSS
PA5(HS)
PA0(HS)
PA4(HS)
PA1(HS)
PA3(HS)
PA2(HS)
8
R0182
7
6
5
R0183
RN103
ISL24813 Programmable Gamma Buffer
25
27
26
INNCOM
INPCOM/DVROUT
OUTCOM
Model Name
PVGMA17
20
C0159
19
AVDD_GA
18
17
PA2_A
PA3_A
PA4_A
PA5_A
3
Gamma
Size
Document Number
Custom
T315HW02
Date:
PVGMA19
21
VGMA21
VGMA19
VGMA17
VGMA15
PAD
NC
RN101
8
7
6
5
1
2
3
4
REFB22
PVGMA21
22
<Variant Name>
PVGMA21
PVGMA19
PVGMA17
PVGMA15
8
7
6
5
NC
PAD
R0142
1
2
3
4
PAD
R0141
VGMA8
VGMA6
VGMA4
VGMA2
PAD
PVGMA8
PVGMA6
PVGMA4
PVGMA2
28
29
30
OUT13
G1
REF_F21
SET
DVDD
STD_REG
OUT14
OUT6
REF_F19
OUT5
PVGMA8
REF19
AVDD
PVGMA22
23
OUT12
G1
R0138
AVDD
24
PVGMA15 16
U0102
GND
OUT11
SCL_GA
OUT15
OUT10
SDA_GA
OUT16
PVGMA13 15
V3D3
R0137
PAD
OUT17
U101
PVGMA12 14
AVDD_GA
OUT18
GND
SCL
C0157
REF_F17
OUT4
13
SDA
OUT9
PVGMA6
OUT3
12
OUT2
PVGMA11 11
PVGMA4
OUT1
31
32
REFIN
OUT8
REF17
PVGMA2
OUT7
R0136
VG22
PVGMA1
PVGMA10 10
REF_F15
VGMA22
C0114
PAD
R0134
1
REFB22
VG1 & VG22 => L255.

VG2 & VG21 => L254
VG4 & VG19 => L223
VG6 & VG17 => L128
VG8 & VG15 => L32
VG10 & VG13 => L1
VG11 & VG12 => L0
BANK_SELECT
R0143
R0135
PAD
VCOMF2
C0156
REF_F13
REF15
PAD
R0164
NC
VG21
R0133
PAD
C0113
R0132
REF13
PAD
Close to U103 pin8
R0165
R0131
AVDD_GA
PAD
C0121
Negative Gamma Value
C0162
NC
C0112
AVDD
REFB12
VCOMF2
AVDD_MGA
PAD
Close to U103 pin15
RN106
NC
AVDD_MGA
REFB2
REFB4
REFB6
REFB8
REFB10
REFB11
R0130
5
6
7
8
R0179
1
R0170
14
VG15
VGMA17
4
3
2
1
U108A
V3D3
R0129
11
11
36
35
34
33
32
31
30
29
28
27
26
25
C0126
REFB19
5
1
C0109
AVDD
PAD
PAD
REF_F21
REF_F22
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
R0147
R0128
REF10
Bi
Ai
VDD
VSS
Ao
VSS
Bo
N.C.
N.C.
VDD
N.C.
Co
REFB12
REFB13
REFB15
REFB17
PAD
REF_F8
Mi
Ni
Vcomi
N.C.
N.C.
N.C.
VDD
VSS
VDD
VSS
Vcomo
No
NC
Close to U103 pin43
REF8
37
38
39
40
41
42
43
44
45
46
47
48
V3D3_MGA
VCOMF
VG12
VGMA13
REFB13
R0178
R0169
R0122
R0145
Close to U103 pin22
R0181
Max9669 Programmable Gamma Buffer
PAD
VCOMF
R0180
REF_F2
REF_F1
C0127 VCOMI
R0144
R0121
MPVGMA22
PAD
REF_F6
Li
Ki
Ji
Ii
Hi
VSS
VDD
Gi
Fi
Ei
Di
Ci
PAD
R0146
Mo
Lo
Ko
Jo
Io
Ho
VSS
VDD
Go
Fo
Eo
Do
REF6
U0103
GMA15
PAD
AVDD
R0117
R0177
R0116
NC
C0173
C0174
REF_F4
REF_F12
REF_F13
REF_F15
REF_F17
REF_F19
REF_F4
REF_F6
REF_F8
REF_F10
REF_F11
R0111
REF4
R0176
4
PAD
R0110
R0175
V3D3_MGA
11
REFB11
AVDD
PAD
AGND
V3D3
SDA_GA
REF_F2
NC
NC
SCL_GA
R0104
1
SCL
PAD
Close to U103 pin30
PAD
21
SDA
AVDD
C0106
VGMA22
MPVGMA21
REFB10
GMA7
GMA13
20
A0
GMA12
19
AVDD_MGA
GMA6
27
MPVGMA11
DVDD
26
18
VCOM
GMA5
MPVGMA19
MPVGMA10
R0174
GND_AMP
GMA11
17
VG8
VGMA10
R0103
REF2
VGMA21
VGMA19
VGMA17
VGMA15
VCOMF2
NC
U0105
GMA4
25
MPVGMA8
GMA3
MPVGMA17
16
C0105
R0127
Positive Gamma Value
REFB1
14
MPVGMA6
VG6
VGMA8
PAD
R0126
15
GMA10
REFB8
MPVGMA4
24
C0118
Close to U103
MPVGMA22
R0172
MPVGMA15
R0124
C0116
C0104
REF_F12
GMA1
PAD
R0123
PAD
GMA2
REF_F12
REF_F22
8
7
6
5
R0173
VG4
VGMA6
REFB6
Close to U103 pin29
MPVGMA2
RN104
GMA9
R0120
5
6
7
8
GMA8
4
3
2
1
Close to U103 pin23
NC
R0157
23
R0114
PAD
MPVGMA211
MPVGMA192
MPVGMA173
MPVGMA154
VG2
VGMA4
REFB4
22
R0115
R0112
REF_F22
VGMA8
VGMA6
VGMA4
VGMA2
RN109
MPVGMA1
C0117
U0104
R0118
8
7
6
5
NC
C0102
MPVGMA13
C0115
R0113
REF
VGMA13
VGMA12
VGMA11
VGMA10
RN107
MPVGMA8 1
MPVGMA6 2
MPVGMA4 3
MPVGMA2 4
C0171
PAD
PAD
PAD
REF_F1
VG1
VGMA2
REFB2
REF_F11
C
CATH
VZREF
PAD
8
7
6
5
PAD
REF_F1
R0108
ANODE
GND
NC
RN108
AVDD_MGA
C0170
MPVGMA12
C0125
NC
NC
PAD
C0124
VGMA1
R0105
C0101
MPVGMA1
R0171
VGMA1
VGMA_REF
AVDD
VGMA[1..22] VGMA[1..22]
R0101
R0100
AVDD
MPVGMA131
MPVGMA122
MPVGMA113
MPVGMA104
R0156
Rev

1
EC02
V3 Tcom\MEMC Board
Sheet
of
10
T2_LVN[0..2]
C0404
RN0400
T2_LVP1
T2_LVN1
T2_LVP2
T2_LVN2
R0407
VDD_V1D2_M
V3D3
VDD_V3D3_M
R0408
L0403
C0416
C0418
C0419
XIN_M
C0417
PAD
PAD 1
XOUT_M
Closed to pin117 of U401
XOUT_M
CHRB
CHPN
120HZ
When ODEN is high,

OD_EN(Internal Register )
0 : OD enable
1 : OD disable
R0405
ODEN_M
AGBSEN
LVDSORD
NC
L0401
VDD_V3D3_M
V3D3
C0430
C0411
AGBSEN
LVDSORD
XSTB_M
XPOL_M
YDIO_M
YCLK_M
YOE_M
XPOL_M
YDIO_M
YCLK_M
YOE_M
RST
INSDA_M
INSCL_M
EPWP_M
EXSDA
EXSCL
C0410
XSTB_M
YOE3_M
YOE4_M
YV1C_M
On Bottom Layer
YOE3_M
YOE4_M
YV1C_M
U0402
5 SDA
6 SCL
7 WP
8 VCC
RST
EXSDA
EXSCL
R0401
R0409
GND
A2
A1
A0
4
3
2
1
R0410
R0411
D0401
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V3D3
T2
CHML
GNDE_M
GND
PAD
GND
AUO12401 K1
CHFB
R0406
VCCE_M
T2_RVN4
T2_RVP4
CHPXB
PAD
C0415
EPWP_M
C0414
C0413
CHPXF
PAD
C0412
V1D2
L0402
BRVS
INSCL_M
V1D2
T2_RVN6
T2_RVP6
T2_RVN5
T2_RVP5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
INSDA_M
NC
TEST
SWAPL
GOAEN
SPDEN
DCREN
ODEN
AGBSEN
LVDSORD
VDDIO
GND
VDDC12
VSEL
XSTB
XBDO
XPOL
YDIO
YCLK
YOE1
YOE2
VDDIO
GND
YOE3
YOE4
YV1C
GND
VDDC12
RSTN
INSDA
INSCL
EPWP
EXSDA
EXSCL
FRVS2
G1
R0404
PV3P
RV3N
VDDWR
PFCAP
RVCLKP
RVCLKN
RV4P
RV4N
RV5P
RV5N
VDDM
GND
RV6P
RV6N
RV7P
RV7N
GND
RMLVDS
VDDIO
REXT
VDDC12
VDDC12
GND
VDDIO
GND
GND
VDDIO
GND
PWM
OSCSEL
XIN
XOUT
RXINO0N
RXINO0P
RXINO1N
RXINO0P
RXINO2N
RXINO2P
VDDL
GND
RXCLKON
RXCLKOP
RXINO3N
RXINO3P
RXINO4N
RXINO4P
VDDL
GND
VDDC12
VDDC12
GND
RXINE0N
RXINE0P
RXINE1N
RXINE1P
RXINE2N
RXINE2P
VDDL
RXCLKEN
RXCLKEP
RXINE3N
RXINE3P
RXINE4N
RXINE4P
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
OSCSEL_M 126
127
128
RV2N
RV2P
GND
VDDM
RV1N
RV1P
RV0N
RV0P
LV7N
LV7P
LV6N
LV6P
GND
VDDM
LV5N
LV5P
LV4N
LV4P
GND
VDDC12
LVCLKN
LVCLKP
LV3N
LV3P
LV2N
LV2P
GND
VDDM
LV1N
LV1P
LV0N
LV0P
NC
C0408
When ODEN is low or OPEN,

0 : OD disable
1 : OD enable
R0403
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
U0401
C0409
VDD_V3D3_M
VDD_V1D2_M
G1
VDD_V3D3_M
VDD_V1D2_M
FRVS1
PAD
T2_LVP0
T2_LVN0
T2_LVP5
T2_LVN5
T2_LVP6
T2_LVN6
T2_LVP4
T2_LVN4
T2_RVP1
T2_RVN1
T2_RVP2
T2_RVN2
KME use
R0402
C0407
C0405
T2_RVP0
T2_RVN0
For
C0406
VDD_V1D2_M
MODE41
PAD
C0402
T2_LVP[0..2]
T2_LVN[0..2]
T2_LVP[0..2]
C0403
PIX_SFT_EN
T2_LVCLKN
T2_LVCLKN
T2_lVCLKP
T2_LVCLKP
VDD_V3D3_M
Close to U401
VDD_V1D2_M
Data Mapping Setting Table

RN0401
T2_LVN[4..6]
T2_LVN[4..6]
T2_LVP[4..6]
T2_LVP[4..6]
T2_RVN[0..2]
T2_RVN[0..2]
T2_RVP[0..2]
T2_RVCLKN
Close to U401
T2_RVP[0..2]
T2_RVN[4..6]
T2_RVP[4..6]
T2_RVCLKN
T2_RVCLKP
T2_RVN[4..6]
T2_RVCLKP
T2_RVP[4..6]
RXINDN3
RXINDP3
RXINDN4
RXINDP4
R0412
RXINDN0
RXINDP0
RXINDN1
RXINDP1
RXINDN2
RXINDP2
C0421
RXINBN3
RXINBP3
RXINBN4
RXINBP4
VDD_V1D2_M
VDD_V3D3_M
RXINBN0
RXINBP0
RXINBN1
RXINBP1
RXINBN2
RXINBP2
Y0401
VDD_V3D3_M
GND
VDD_V1D2_M
VDD_V3D3_M
C0420
VDD_V1D2_M
C0422
C0401
C0423
RXINDP[0..4]
RXCLKDN
RXCLKDP
RXINDN[0..4]
RXCLKBN
RXCLKBP
C0424
RXINBP[0..4]
VDD_V3D3_M
RXINBN[0..4]
R0413
C0426
C0425
C0427
A
RXCLKDN
RXCLKDP
RXINDP[0..4]
RXINDN[0..4]
RXCLKBP
RXCLKBN
RXINBP[0..4]
RXINBN[0..4]
<Variant Name>
Model Name
Tcom(Master)
Size
Document Number
Custom
T315HW02
Date:
Rev
EC02
V3 Tcom\MEMC Board

1
Sheet
of
10
PI_ODD_RIN0N
PI_ODD_RIN1N
PI_ODD_RIN2N
PI_ODD_RIN3N
PI_ODD_RIN4N
PI_ODD_RIN0N
PI_ODD_RIN1N
PI_ODD_RIN2N
PI_ODD_RIN3N
PI_ODD_RIN4N
PI_ODD_RIN0P
PI_ODD_RIN1P
PI_ODD_RIN2P
PI_ODD_RIN3P
PI_ODD_RIN4P
PI_ODD_RIN0P
PI_ODD_RIN1P
PI_ODD_RIN2P
PI_ODD_RIN3P
PI_ODD_RIN4P
PI_ODD_RINCLKN
PI_ODD_RINCLKP
RX1B_AP
RX1B_BP
RX1B_CP
RX1B_DP
RX1B_EP
PI_ODD_RIN0P
PI_ODD_RIN1P
PI_ODD_RIN2P
PI_ODD_RIN3P
PI_ODD_RIN4P
RX1B_CLKN
RX1B_CLKP
PI_ODD_RINCLKN
PI_ODD_RINCLKP
FRC_NRESET
I2C_SCL
I2C_SDA
HSYNC
MAIN_CHECK
SW_PVCC
RX3B_AN
RX3B_BN
RX3B_CN
RX3B_DN
RX3B_EN
FRC_NRESET
I2C_SCL
RX3B_AP
RX3B_BP
RX3B_CP
RX3B_DP
RX3B_EP
I2C_SDA
HSYNC
RX3B_CLKN
RX3B_CLKP
MAIN_CHECK
SW_PVCC
PI_EVEN_RIN0N
PI_EVEN_RIN1N
PI_EVEN_RIN2N
PI_EVEN_RIN3N
PI_EVEN_RIN4N
PI_EVEN_RIN0N
PI_EVEN_RIN1N
PI_EVEN_RIN2N
PI_EVEN_RIN3N
PI_EVEN_RIN4N
PI_EVEN_RIN0P
PI_EVEN_RIN1P
PI_EVEN_RIN2P
PI_EVEN_RIN3P
PI_EVEN_RIN4P
PI_EVEN_RIN0P
PI_EVEN_RIN1P
PI_EVEN_RIN2P
PI_EVEN_RIN3P
PI_EVEN_RIN4P
PI_EVEN_RINCLKN
PI_EVEN_RINCLKP
RX2B_AN
RX2B_BN
RX2B_CN
RX2B_DN
RX2B_EN
PI_EVEN_RIN0N
PI_EVEN_RIN1N
PI_EVEN_RIN2N
PI_EVEN_RIN3N
PI_EVEN_RIN4N
RX2B_AP
RX2B_BP
RX2B_CP
RX2B_DP
RX2B_EP
PI_EVEN_RIN0P
PI_EVEN_RIN1P
PI_EVEN_RIN2P
PI_EVEN_RIN3P
PI_EVEN_RIN4P
RX2B_CLKN
RX2B_CLKP
RX4B_AN
RX4B_BN
RX4B_CN
RX4B_DN
RX4B_EN
GND
PI_EVEN_RINCLKN
PI_EVEN_RINCLKP
RX4B_AP
RX4B_BP
RX4B_CP
RX4B_DP
RX4B_EP
B3.3VD
RX1B_AN
RX1B_BN
RX1B_CN
RX1B_DN
RX1B_EN
PI_ODD_RIN0N
PI_ODD_RIN1N
PI_ODD_RIN2N
PI_ODD_RIN3N
PI_ODD_RIN4N
RX4B_CLKN
RX4B_CLKP
FRC_IO
05A.FRC_IO
RXINAN0
RXINAN1
RXINAN2
RXINAN3
RXINAN4
RXINAP0
RXINAP1
RXINAP2
RXINAP3
RXINAP4
RXINCLKAN
RXINCLKAP
Power
B12V
RXINAN[0..4]
B12V
B3.3VD
RXINCLKCN
RXINCLKCP
RXINCLKBN
RXINCLKBP
B1.8V_DDR GND
RXINAP[0..4]
RXINCLKAN
RXINCLKAP
05C.FRC_Power
RXINCN[0..4]
DDR
RXINCP[0..4]
RXINCLKCN
RXINCLKCP
RXINBN0
RXINBN1
RXINBN2
RXINBN3
RXINBN4
RXINBP0
RXINBP1
RXINBP2
RXINBP3
RXINBP4
VREF
B1.8V_DDR
RXINCN0
RXINCN1
RXINCN2
RXINCN3
RXINCN4
RXINCP0
RXINCP1
RXINCP2
RXINCP3
RXINCP4
B3.3VD
VREF
B1.8V_DDR
VREF
RXINBN[0..4]
B1.8V_DDR
VREF
GND
05B.FRC_DDR
RXINBP[0..4]
RXINCLKBN
RXINCLKBP
B
RXINDN0
RXINDN1
RXINDN2
RXINDN3
RXINDN4
RXINDP0
RXINDP1
RXINDP2
RXINDP3
RXINDP4
RXINCLKDN
RXINCLKDP
RXINDN[0..4]
RXINDP[0..4]
RXINCLKDN
RXINCLKDP
GND
B3.3VD
<Variant Name>
Model Name
FRC Top
Size
B
Date:
5
Document Number
Rev

Sheet
1
EC02
of
10
PI_ODD_RIN4P
PI_ODD_RIN4N
PI_ODD_RIN4P
PI_ODD_RIN4N
PI_ODD_RIN3P
PI_ODD_RIN3N
PI_ODD_RIN3P
PI_ODD_RIN3N
PI_ODD_RIN2P
PI_ODD_RIN2N
PI_ODD_RIN2P
PI_ODD_RIN2N
R619
R611
IC500C
R595
PI_ODD_RIN1P
PI_ODD_RIN1N
PI_ODD_RIN1P
PI_ODD_RIN1N
PI_ODD_RIN0P
PI_ODD_RIN0N
PI_ODD_RIN0P
PI_ODD_RIN0N
R1
PI_ODD_RINCLKP
PI_ODD_RINCLKN
PI_EVEN_RIN4P
PI_EVEN_RIN4N
PI_EVEN_RIN3P
PI_EVEN_RIN3N
PI_EVEN_RIN3P
PI_EVEN_RIN3N
PI_EVEN_RIN2P
PI_EVEN_RIN2N
PI_EVEN_RIN2P
PI_EVEN_RIN2N
R618
R610
R602
RX4B_EP
RX4B_EN
RX4B_DP
RX4B_DN
RX4B_CP
RX4B_CN
RX4B_BP
RX4B_BN
RX4B_AP
RX4B_AN
RX4B_CLKP
RX4B_CLKN
R594
PI_EVEN_RIN1P
PI_EVEN_RIN1N
PI_EVEN_RIN1P
PI_EVEN_RIN1N
PI_EVEN_RIN0P
PI_EVEN_RIN0N
PI_EVEN_RIN0P
PI_EVEN_RIN0N
R586
R578
C
RX1B_AN
RX1B_AP
D
R579
PI_EVEN_RIN4P
PI_EVEN_RIN4N
RX1B_CLKN
RX1B_CLKP
FRC
R603
PI_ODD_RIN4P
PI_ODD_RIN4N
PI_ODD_RIN3P
PI_ODD_RIN3N
PI_ODD_RIN2P
PI_ODD_RIN2N
PI_ODD_RIN1P
PI_ODD_RIN1N
PI_ODD_RIN0P
PI_ODD_RIN0N
PI_ODD_RINCLKP
PI_ODD_RINCLKN
PI_EVEN_RIN4P
PI_EVEN_RIN4N
PI_EVEN_RIN3P
PI_EVEN_RIN3N
PI_EVEN_RIN2P
PI_EVEN_RIN2N
PI_EVEN_RIN1P
PI_EVEN_RIN1N
PI_EVEN_RIN0P
PI_EVEN_RIN0N
PI_EVEN_RINCLKP
PI_EVEN_RINCLKN
R537
R538
R539
R540
R541
R542
R543
U2850
R545
R546
R547
R548
M1
M2
L1
L2
J1
J2
H1
H2
G1
G2
K1
K2
F1
F2
E1
E2
C1
C2
B1
B2
A1
A2
D1
D2
T21
T22
R21
R22
N21
N22
M21
M22
L21
L22
P21
P22
PI_EVEN_RINCLKP
PI_EVEN_RINCLKN
P_ZB_RX4_P
P_ZB_RX4_N
P_ZB_RX3_P
P_ZB_RX3_N
P_ZB_RX2_P
P_ZB_RX2_N
P_ZB_RX1_P
P_ZB_RX1_N
P_ZB_RX0_P
P_ZB_RX0_N
P_ZB_CLK_P
P_ZB_CLK_N
P_ZA_RX4_P
P_ZA_RX4_N
P_ZA_RX3_P
P_ZA_RX3_N
P_ZA_RX2_P
P_ZA_RX2_N
P_ZA_RX1_P
P_ZA_RX1_N
P_ZA_RX0_P
P_ZA_RX0_N
P_ZA_CLK_P
P_ZA_CLK_N
P_YB_TX4_P
P_YB_TX4_N
P_YB_TX3_P
P_YB_TX3_N
P_YB_TX2_P
P_YB_TX2_N
P_YB_TX1_P
P_YB_TX1_N
P_YB_TX0_P
P_YB_TX0_N
P_YB_CLK_P
P_YB_CLK_N
P_XA_CLK_N
P_XA_CLK_P
P_XA_RX0_N
P_XA_RX0_P
P_XA_RX1_N
P_XA_RX1_P
P_XA_RX2_N
P_XA_RX2_P
P_XA_RX3_N
P_XA_RX3_P
P_XA_RX4_N
P_XA_RX4_P
P_XB_CLK_N
P_XB_CLK_P
P_XB_RX0_N
P_XB_RX0_P
P_XB_RX1_N
P_XB_RX1_P
P_XB_RX2_N
P_XB_RX2_P
P_XB_RX3_N
P_XB_RX3_P
P_XB_RX4_N
P_XB_RX4_P
P_YA_CLK_N
P_YA_CLK_P
P_YA_TX0_N
P_YA_TX0_P
P_YA_TX1_N
P_YA_TX1_P
P_YA_TX2_N
P_YA_TX2_P
P_YA_TX3_N
P_YA_TX3_P
P_YA_TX4_N
P_YA_TX4_P
R501
R502
R503
R504
R505
R506
R507
R508
R509
R510
R511
R512
R513
R514
R515
R516
R517
R518
R519
R520
R521
R522
R523
U2849
R525
R526
R527
R528
R529
R530
R531
R532
R533
R534
R535
R536
A16
B16
A13
B13
A14
B14
A15
B15
A17
B17
A18
B18
B22
B21
A19
B19
A20
B20
A22
A21
C22
C21
D22
D21
H22
H21
E22
E21
F22
F21
G22
G21
J22
J21
K22
K21
RX1B_BN
RX1B_BP
RX1B_CLKN
RX1B_CLKP
RX1B_AN
RX1B_AP
RX1B_BN
RX1B_BP
RX1B_CN
RX1B_CP
RX1B_DN
RX1B_DP
RX1B_EN
RX1B_EP
RX1B_CN
RX1B_CP
RX1B_DN
RX1B_DP
RX1B_EN
RX1B_EP
RX2B_CLKN
RX2B_CLKP
RX2B_CLKN
RX2B_CLKP
RX2B_AN
RX2B_AP
RX2B_BN
RX2B_BP
RX2B_CN
RX2B_CP
RX2B_DN
RX2B_DP
RX2B_EN
RX2B_EP
RX2B_AN
RX2B_AP
RX2B_BN
RX2B_BP
RX2B_CN
RX2B_CP
RX2B_DN
RX2B_DP
RX3B_CLKN
RX3B_CLKP
RX3B_AN
RX3B_AP
RX3B_BN
RX3B_BP
RX3B_CN
RX3B_CP
RX3B_DN
RX3B_DP
RX3B_EN
RX3B_EP
RX2B_EN
RX2B_EP
RX3B_CLKN
RX3B_CLKP
RX3B_AN
RX3B_AP
RX3B_BN
RX3B_BP
C
RX3B_CN
RX3B_CP
RX3B_DN
RX3B_DP
RX4B_EP
RX4B_EN
RX3B_EN
RX3B_EP
RX4B_DP
RX4B_DN
RX4B_CP
RX4B_CN
RX4B_BP
RX4B_BN
B3.3VD
RX4B_AP
RX4B_AN
B3.3VD
B3.3VD
C501
RX4B_CLKP
RX4B_CLKN
B3.3VD
R513_DE
CIS
R584
NC
IC500B
MAIN_CHECK
SW_PVCC
FRC_NRESET
R631
R632
R5841_DE R5842_DE
NC
R627
R628
R629
R630
IC503
R582
R590
R598
R606
R614
R622
R583
R591
R599
R607
R642
R615
R623
T_RST
MAIN_CHECK
SW_PVCC
A11
B10
A10
B9
A9
B8
A8
B7
A7
P2
P3
R2
R3
B6
A6
FRC_NRESET
R644
GND
R585_1
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
RESET_N
TM
FRC
SSDA
SSCL
MSDA
MSCL
V
PWM
H
TRST_N
TMS
TDO
TDI
TCLK
XOUT
XIN
N2
N1
M3
N3
A12
B11
B12
A3
A5
B5
A4
B4
P1
R1
R633
I2C_SDA
R634
I2C_SCL
R635
EEPROM_SDA
R636
EEPROM_SCL
R637_DE
8
7
6
5
VCC
WP
SCL
SDA
NC
A1
A2
GND
1
2
3
4
R524
NC
R638
R639_DE
EEPROM_SCL
EEPROM_SDA
NC
HSYNC
HSYNC
HSYNC
NC
R640
1
R641_DE
PAD
TP501
NC
R643
PAD
TP502
R585
CIS
X501
B3.3VD
B3.3VD
R588
C586_1
/RESET
VDD
3
C586
A
GND
IC589
<Variant Name>
Model Name
FRC IO
Size
C
Date:
5
Document Number
Rev
EC02

1
Sheet
of
10
L102
GND
B12V
B3.3VD
B1.8V_DDR
VREF
C122_1
B3.3VD
B2.5V_VDDL_PLL
R113_2
CIS
BS
BD129
C604
C605
C588
C589
C505
C506
C507
C508
C509
C503
CIS
CIS
C156
C127
GND
C129
CIS
CIS
C157
C158
CIS
CIS
CIS
C510
C511
C512
C513
C514
C515
C516
CIS
C2729
CIS
C2730
CIS
C2731
CIS
C2732
CIS
C2733
CIS
C2734
C2735
R119_1
D105_1
C517
C146_1
NC
B1.05V_MPLL
CIS
CIS
CIS
CIS
C518
C519
C520
C521
C522
R157_DE
CIS
CIS
BD120
R113_OP
CIS
NC
B3.3VD
BD2711
B3.3V_OSC
CIS
BD2713
B1.05V_PLL
CIS L103
CIS
C122
CIS
CIS
CIS
C612
C613
C523
C524
CIS
CIS
C159
C120
CIS
B1.05V
CIS
C526
C527
CIS
C528
CIS
CIS
C529
CIS
C530
CIS
C531
BS
SS
IN
EN
SW
GND
COMP
FB
CIS
C160
U2841
C2789
8
C147_OP
C145
CIS
R115
7
6
CIS
CIS
C152
C121
CIS
CIS
C2788
CIS
R113_1
CIS
CIS
R114
CIS
IC110
CIS
CIS
CIS
CIS
PAD
TP_B3D3V
B1.8V_DDR
C525
CIS
CIS
C153
C2736
C2737
CIS
C2738
CIS
C2739
CIS
C2740
CIS
CIS
CIS
C2741
C2742
C2743
CIS
R118
CIS
D105
CIS
CIS
DE
CIS
CIS
R119
NC
C148_OP C149_DE
C146
2
FRC
IC500D
CIS
C2728
R118_1
B2.5V_VDDL
CIS
CIS
C134
C149_1_DE
J7
T13
H4
J4
K19
M19
H19
D14
D16
D12
P4
D8
D7
M4
P16
T15
T12
T8
P7
R4
T9
T16
R16
R9
P9
J16
J9
H16
H9
G16
G9
R15
C148_1_OP
VDD105_S
VDD105DLL
VDDLZ25PLL
VDDLZ25
VDDLY25PLL
VDDLY25
VDDLY25
VDDLX25PLL
VDDLX25
VDDLX25
VDD33OSC
VDD33
VDD33
VDD33
VDD18
VDD18
VDD18
VDD18
VDD18
VDD105PLL
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
DRAM_VREF
VDD105
VDD105
VDD106
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
VDD105
GND
W12
G7
G14
H7
H14
J10
J13
J14
P14
R7
R14
T7
T14
G8
G15
H8
H15
J8
J15
K9
K10
K13
K14
N9
N10
N13
N14
P8
P10
P13
P15
R8
CIS
C145_1
C689
R108
FB
NCV1.05VF
CIS BD2007
COMP
MGND1
C688
BD109_DE
C130_OP
MGND1
CIS
CIS BD108
EN
SW
CIS DE
B1.05V
PAD
SS
IN
C504
FRC
IC500E
CIS
B12V
B3.3V_OSC
VREF
TP_B1D05V
CIS
IC104
B1.05V_DLL
GND
GND
B12V
B3.3VD
B1.8V_DDR
VREF
CIS 47NF/10%/16V/X7R/0603
CIS
CIS
CIS
CIS
CIS
CIS
CIS
C536
C537
C539
C541
C542
C543
C544
CIS
1
CIS
CIS
CIS
CIS
CIS
CIS
CIS
C538
C540
U502
U503
U504
U505
IC102
U501
L116
PAD
B3.3VD
CIS 10NF/10%/50V/X7R/0603
Vin
B2.5V_VDDL
CIS
TP_B2D5V
GND
CIS
CIS
U2842
C108
Vout
CIS
C112
B2.5V_VDDL_PLL
CIS
L117
CIS
CIS
C163
C183
CISBD160
CIS
CIS
C161
C162
B1.05V
CIS
C534
C535
B3.3VD
CIS
L111
IC109
1
CIS
CIS
C195
C194
CIS
C191
CIS
C196_1
C196
CIS
C125
IN
CISBD163
OUT
B1.05V_DLL
V1.05VF
CIS
CIS
GND
R137
CIS
/EN
FB
R140
C190_1
C190_2
CISBD2712
CIS
CIS
C165
CIS
C190
R125
CIS
C164
C192_2
B1.05V_PLL
C192
CIS
R141
CIS
CIS
C189
C2748
CIS
C533
PAD
CIS
C532
TP_B1D8V
B3.3VD
PAD
CIS
CIS
IC107
CIS
TP_B1D05V_PLL
B1.8V_DDR
L112
3
Vin
Vout
2
R142
CIS
R138
CIS
CIS
R139
CIS
CIS
C103
CIS
C109
C014
CIS
C101
CIS
C102
<Variant Name>
C105
CIS
R143
CIS
Model Name
FRC Power
Size
Document Number
Custom
T315HW02
Date:
B1.05V_MPLL
CIS 100NF/10%/16V/X7R/0603
W19
W18
W17
W16
W15
W14
W13
W11
W10
W9
W8
W4
V19
V4
U22
U20
U19
U4
U3
U2
T20
T19
T11
T10
T4
T3
T2
R20
R19
R13
R12
R11
R10
P20
P19
P12
P11
N20
N19
N16
N15
N12
N11
N8
N7
N4
M20
M16
M15
M14
M13
M12
M11
M10
M9
M8
M7
L20
L19
L16
L15
L14
L13
L12
L11
L10
L9
L8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS105MPLL
VSS105PLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS33OSC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADJ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS105_S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D3
D4
D5
D6
D9
D10
D11
D13
D15
D17
D18
D19
D20
E3
E4
E19
E20
F3
F4
F19
F20
G3
G4
G10
G11
G12
G13
G19
G20
H3
H10
H11
H12
H13
H20
J3
J11
J12
J19
J20
K3
K4
K7
K8
K11
K12
K15
K16
K20
L3
L4
L7
Rev
EC02
V3 Tcom\MEMC Board

1
Sheet
of
10
FRC_DQ0
FRC_DQ1
FRC_DQ7
FRC_DM0
FRCD_DQS0_P
B1.8V_DDR
FRC_DQ6
FRC
IC500A
FRCD_DQS0_N
FRC_DQ13
FRC_DQ10
VTT_FRC
FRCD_ADDR[0..12]
FRCD_BA0
FRCD_BA1
FRCD_BA2
FRCD_NCAS
FRCD_CLK
FRCD_NCLK
FRCD_CLKE
FRCD_NCS
FRC_DM0
FRC_DM1
FRC_DM2
FRC_DM3
FRC_DQ[0..31]
W7
W6
W5
AA13
AB14
AA12
AB4
AA4
AA3
Y3
AA22
AB22
AA21
AB20
AA18
W20
W22
AA17
U21
AB16
AA5
Y1
AA20
Y6
W1
AA1
Y4
W2
Y5
AA6
W3
AB6
U1
V21
V3
[MDSD32M16B]
FRC_DQ11
FRC_DQ12
FRC_DQ8
FRC_DQ9
FRC_DQ15
FRCD_DQS1_P
FRC_DM1
FRC_DQ14
FRCD_DQS1_N
D3
D2
D1
C9
C8
C7
C3
C2
C1
B9
B8
B7
B3
B2
B1
A9
A8
A7
A3
A2
A1
DQ11
[VSSQ]
DQ12
[VDDQ]
DQ8
[VDDQ]
[VDDQ]
DQ9
[VDDQ]
DQ15
[VSSQ]
UDQS
UDM
[VSSQ]
DQ14
[VDDQ]
/UDQS
[VSSQ]
[VSS]
NC4
[VDD]
H1
H2
H3
H7
H8
H9
J1
J2
J3
J7
J8
J9
K2
K3
K7
K8
K9
L1
L2
L3
L7
R326
R318
R319
R320
R321
R322
R323
R324
R317
DQ4
[VSSQ]
DQ3
DQ2
[VSSQ]
DQ5
[VDDL]
[VREF]
[VSS]
[VSSDL]
CK
[VDD]
CKE
/WE
/RAS
/CK
ODT
BA2
BA0
BA1
/CAS
R325
IC301
D7
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
FRCD_NWE
FRCD_NRAS
FRCD_ODT
FRCD_DQS3_N
FRCD_DQS3_P
FRCD_DQS2_N
FRCD_DQS2_P
FRCD_DQS1_N
FRCD_DQS1_P
FRCD_DQS0_N
FRCD_DQS0_P
FRC_DQ9
FRC_DQ8
FRC_DQ7
FRC_DQ6
FRC_DQ5
FRC_DQ4
FRC_DQ31
FRC_DQ30
FRC_DQ3
FRC_DQ29
FRC_DQ28
FRC_DQ27
FRC_DQ26
FRC_DQ25
FRC_DQ24
FRC_DQ23
FRC_DQ22
FRC_DQ21
FRC_DQ20
FRC_DQ2
FRC_DQ19
DQ10
[VSSQ]
DQ13
[VDD]
NC5
[VSS]
[VSSQ]
/LDQS
[VDDQ]
DQ6
[VSSQ]
LDM
LDQS
[VSSQ]
DQ7
[VDDQ]
DQ1
[VDDQ]
[VDDQ]
DQ0
[VDDQ]
DRAM_A0
DRAM_TEST_D2
DRAM_A1
DRAM_TEST_D1
DRAM_A10 DRAM_TEST_ANALOG
DRAM_A11
DRAM_WE_N
DRAM_A12
DRAM_RAS_N
DRAM_A2
DRAM_ODT
DRAM_A3
DRAM_DQS3_N
DRAM_A4
DRAM_DQS3
DRAM_A5
DRAM_DQS2_N
DRAM_A6
DRAM_DQS2
DRAM_A7
DRAM_DQS1_N
DRAM_A8
DRAM_DQS1
DRAM_A9
DRAM_DQS0_N
DRAM_BA0
DRAM_DQS0
DRAM_BA1
DRAM_DQ9
DRAM_BA2
DRAM_DQ8
DRAM_CAS_N
DRAM_DQ7
DRAM_CK
DRAM_DQ6
DRAM_CK_N
DRAM_DQ5
DRAM_CKE
DRAM_DQ4
DRAM_CS_N
DRAM_DQ31
DRAM_DM0
DRAM_DQ30
DRAM_DM1
DRAM_DQ3
DRAM_DM2
DRAM_DQ29
DRAM_DM3
DRAM_DQ28
DRAM_DQ0
DRAM_DQ27
DRAM_DQ1
DRAM_DQ26
DRAM_DQ10
DRAM_DQ25
DRAM_DQ11
DRAM_DQ24
DRAM_DQ12
DRAM_DQ23
DRAM_DQ13
DRAM_DQ22
DRAM_DQ14
DRAM_DQ21
DRAM_DQ15
DRAM_DQ20
DRAM_DQ16
DRAM_DQ2
DRAM_DQ17
DRAM_DQ19
DRAM_DQ18
FRC_DQ4
FRC_DQ3
FRC_DQ2
FRC_DQ5
B1.8V_DDR
BD508
VREF
C301
C302
C771
C773
C313
C314
C316
C317
C319
C325
C327
C329
C331
C332
C344
C341
C340
FRCD_CLK
FRCD_CLKE
FRCD_NWE
FRCD_NRAS
FRCD_NCLK
FRCD_ODT
FRCD_BA2
FRCD_BA0
FRCD_BA1
FRCD_NCAS
C335
VTT_FRC
R357
R8
R7
R3
R2
R1
P9
P8
P7
P3
P2
N8
N7
N3
N2
N1
M9
M8
M7
M3
M2
L8
FRC_DQ0
FRC_DQ1
FRC_DQ10
FRC_DQ11
FRC_DQ12
FRC_DQ13
FRC_DQ14
FRC_DQ15
FRC_DQ16
FRC_DQ17
FRC_DQ18
AA9
AB8
AA15
AA16
Y16
AA8
Y9
Y8
AA7
Y7
AA14
Y14
Y15
AA11
Y11
Y10
Y13
AA10
AB10
Y12
AB12
Y20
Y19
AB1
Y2
V20
Y17
AB21
AA19
Y18
W21
AB18
Y21
AB2
V2
AA2
NC1
NC3
NC2
A12
[VDD]
[VSS]
A8
A11
A9
A7
A4
A6
A5
A3
[VSS]
[VDD]
A0
A2
A1
A10/AP
/CS
FRCD_ADDR0
FRCD_ADDR1
FRCD_ADDR10
FRCD_ADDR11
FRCD_ADDR12
FRCD_ADDR2
FRCD_ADDR3
FRCD_ADDR4
FRCD_ADDR5
FRCD_ADDR6
FRCD_ADDR7
FRCD_ADDR8
FRCD_ADDR9
R372_DE
R358
R359
R360
R361
R362
R363
R364
R365
R366
R367
R368
R369
R370
R371
NC
FRCD_NCS
FRCD_ADDR10
FRCD_ADDR1
FRCD_ADDR2
FRCD_ADDR0
FRCD_ADDR3
FRCD_ADDR5
FRCD_ADDR6
FRCD_ADDR4
FRCD_ADDR7
FRCD_ADDR9
FRCD_ADDR11
FRCD_ADDR8
FRCD_ADDR12
FRCD_ADDR[0..12]
B1.8V_DDR
VTT_FRC
VREF
R387
R388
R389
R390
R391
VTT_FRC
C306
C307
C759
C760
C761
C762
C763
C169
C170
NC
VTT
GND
PVIN
VSENSE AVIN
VREF
VDDQ
8
7
6
5
R386
R385
R384
R383
R382
R381
R380
R379
R378
R377
R376
R375
R374
R373
IC108
1
2
3
4
B1.8V_DDR
VTT_FRC
C167
C168
U2839
VTT_FRC
U2840
BD509
C772
C349
C351
C352
C354
GND
C305
C304
C303
C764
C765
C766
C767
FRCD_DQS3_N
FRC_DQ30
FRC_DM3
FRCD_DQS3_P
FRC_DQ31
FRC_DQ25
FRC_DQ24
FRC_DQ28
[VDD]
NC4
[VSS]
[VSSQ]
/UDQS
[VDDQ]
DQ14
[VSSQ]
UDM
UDQS
[VSSQ]
DQ15
[VDDQ]
DQ9
[VDDQ]
[VDDQ]
DQ8
[VDDQ]
DQ12
[VSSQ]
DQ11
/CAS
BA1
BA0
BA2
ODT
/CK
/RAS
/WE
CKE
[VDD]
CK
[VSSDL]
[VSS]
[VREF]
[VDDL]
DQ5
[VSSQ]
DQ2
DQ3
[VSSQ]
DQ4
L7
L3
L2
L1
K9
K8
K7
K3
K2
J9
J8
J7
J3
J2
J1
H9
H8
H7
H3
H2
H1
FRCD_BA2
C360
C362
C364
C366
C368
C370
C308
C309
VREF
FRC_DQ21
FRC_DQ18
FRC_DQ19
FRC_DQ20
C379
C375
C376
D7
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
DQ10
[VSSQ]
DQ13
[VDD]
NC5
[VSS]
[VSSQ]
/LDQS
[VDDQ]
DQ6
[VSSQ]
LDM
LDQS
[VSSQ]
DQ7
[VDDQ]
DQ1
[VDDQ]
[VDDQ]
DQ0
[VDDQ]
FRC_DQ27
A1
A2
A3
A7
A8
A9
B1
B2
B3
B7
B8
B9
C1
C2
C3
C7
C8
C9
D1
D2
D3
R398
R399
R397
R394
R395
NC1
NC3
NC2
A12
[VDD]
[VSS]
A8
A11
A9
A7
A4
A6
A5
A3
[VSS]
[VDD]
A0
A2
A1
A10/AP
/CS
R8
R7
R3
R2
R1
P9
P8
P7
P3
P2
N8
N7
N3
N2
N1
M9
M8
M7
M3
M2
L8
C348
IC302
[MDSD32M16B]
FRCD_DQS2_N
FRC_DM2
FRC_DQ26
FRC_DQ29
FRC_DQ22
FRCD_DQS2_P
FRC_DQ23
FRC_DQ17
FRC_DQ16
CIS
<Variant Name>
Model Name
FRC DDR
Size
Document Number
Custom
T315HW02
Date:
5
Rev
EC02
V3 Tcom\MEMC Board

1
Sheet
of
10
T1_LVN[0..2]
T1_LVN[0..2]
C0323
C0325
T1_LVP1
T1_LVN1
T1_LVP2
T1_LVN2
VDD_V1D2_S
V3D3
V3D3
L0302
VDD_V3D3_S
R0342
C0305
C0307
C0308
C0306
XIN_S
PAD
XIN_S
B
PAD
XOUT_S
CHRB
CHPN
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
120HZ
When ODEN is high,

0 : OD enable
1 : OD disable
R0308
ODEN_S
AGBSEN
LVDSORD

C
L0301
NC VDD_V3D3_S
C0330
C0320
C0319
AGBSEN
LVDSORD
XSTB_S
XSTB_S
XPOL_S
YDIO_S
YCLK_S
YOE_S
XPOL_S
YDIO_S
YCLK_S
YOE_S
YOE3_S
YOE4_S
YV1C_S
YOE3_S
YOE4_S
YV1C_S
RST
INSDA_S
INSCL_S
EPWP_S
EXSDA
EXSCL
V3D3
On Bottom Layer
U0301
5 SDA
6 SCL
7 WP
8 VCC
RST
EXSDA
EXSCL
R0303
R0304
GND
A2
A1
A0
4
3
2
1
R0305
R0306
D0300
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
T1
GNDE_S
R0313
CHML
PAD
GND
GND
AUO12401 K1
CHFB
VCCE_S
R0312
PAD
T1_RVN4
T1_RVP4
CHPXB
EPWP_S
C0304
PAD
C0303
C0302
CHPXF
C0301
L0300
BRVS
When ODEN is low or OPEN,

0 : OD disable
1 : OD enable
R0309
TEST
SWAPL
GOAEN
SPDEN
DCREN
ODEN
AGBSEN
LVDSORD
VDDIO
GND
VDDC12
VSEL
XSTB
XBDO
XPOL
YDIO
YCLK
YOE1
YOE2
VDDIO
GND
YOE3
YOE4
YV1C
GND
VDDC12
RSTN
INSDA
INSCL
EPWP
EXSDA
EXSCL
U0300
INSDA_S
V1D2
T1_RVN6
T1_RVP6
T1_RVN5
T1_RVP5
PV3P
RV3N
VDDWR
PFCAP
RVCLKP
RVCLKN
RV4P
RV4N
RV5P
RV5N
VDDM
GND
RV6P
RV6N
RV7P
RV7N
GND
RMLVDS
VDDIO
REXT
VDDC12
VDDC12
GND
VDDIO
GND
GND
VDDIO
GND
PWM
OSCSEL
XIN
XOUT
FRVS2
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
OSCSEL_S 126
127
128
RV2N
RV2P
GND
VDDM
RV1N
RV1P
RV0N
RV0P
LV7N
LV7P
LV6N
LV6P
GND
VDDM
LV5N
LV5P
LV4N
LV4P
GND
VDDC12
LVCLKN
LVCLKP
LV3N
LV3P
LV2N
LV2P
GND
VDDM
LV1N
LV1P
LV0N
LV0P
G1
R0311
RXINO0N
RXINO0P
RXINO1N
RXINO0P
RXINO2N
RXINO2P
VDDL
GND
RXCLKON
RXCLKOP
RXINO3N
RXINO3P
RXINO4N
RXINO4P
VDDL
GND
VDDC12
VDDC12
GND
RXINE0N
RXINE0P
RXINE1N
RXINE1P
RXINE2N
RXINE2P
VDDL
RXCLKEN
RXCLKEP
RXINE3N
RXINE3P
RXINE4N
RXINE4P
C0327
V1D2
VDD_V3D3_S
VDD_V1D2_S
G1
VDD_V3D3_S
VDD_V1D2_S
C0328
PAD
T1_LVP0
T1_LVN0
T1_LVP5
T1_LVN5
T1_LVP6
T1_LVN6
T1_LVP4
T1_LVN4
T1_RVP1
T1_RVN1
T1_RVP2
T1_RVN2
T1_RVP0
T1_RVN0
KME use
FRVS1
C0326
C0324
R0310
INSCL_S
VDD_V1D2_S
For
MODE41
PAD
T1_LVP[0..2]
C0322
Close to U300
VDD_V1D2_S
VDD_V3D3_S
C0321
RN0300
PIX_SFT_EN
T1_LVP[0..2]
T1_LVCLKN
T1_lVCLKP
T1_LVCLKN
T1_LVCLKP
RN0301
Data Mapping Setting Table
T1_LVN[4..6]
T1_LVN[4..6]
T1_LVP[4..6]
T1_LVP[4..6]
T1_RVN[0..2]
T1_RVP[0..2]
Close to U300
T1_RVN[0..2]
T1_RVP[0..2]
T1_RVCLKN
T1_RVCLKN
T1_RVCLKP
T1_RVN[4..6]
T1_RVN[4..6]
T1_RVP[4..6]
T1_RVCLKP
T1_RVP[4..6]
VDD_V3D3_S
RXINCN3
RXINCP3
RXINCN4
RXINCP4
R0301
NC
RXINCN0
RXINCP0
RXINCN1
RXINCP1
RXINCN2
RXINCP2
RXINAN0
RXINAP0
RXINAN1
RXINAP1
RXINAN2
RXINAP2
C0309
NC
RXINAN3
RXINAP3
RXINAN4
RXINAP4
VDD_V1D2_S
VDD_V3D3_S
NC
Y0301
GND
VDD_V1D2_S
VDD_V3D3_S
C0317
VDD_V1D2_S
C0312
C0311
C0313
R0302
VDD_V3D3_S
RXINCP[0..4]
RXCLKCN
RXCLKCP
C0315
C0314
C0316
A
RXCLKCP
RXINCP[0..4]
RXCLKCN
RXINCN[0..4]
RXINCN[0..4]
RXCLKAP
RXINAP[0..4]
RXINAN[0..4]
RXCLKAN
RXCLKAP
NC
A
RXCLKAN
C0310
RXINAP[0..4]
RXINAN[0..4]
NC
<Variant Name>

Model Name
Tcom(Slave)
Size
Document Number
Custom
T315HW02
Date:
5
Rev
EC02
V3 Tcom\MEMC Board

1
Sheet
of
10

Samsung - T370HW02 Ve Bn07 00644a Memc T Con - SCH PDF

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Samsung - T370HW02 Ve Bn07 00644a Memc T Con - SCH PDF

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5

Path balance between U300 &U401

Normal / Mirror Setting Table

Td(sec) = R() * C(F) * 0.79

Path balance between U300 &U401

T315HW02 V3 Tcom MEMC Board

T315HW02 V3 Tcom MEMC Board

T315HW02 V3 Tcom\MEMC Board

Layout closely to IC, far from D201 and L201

C209: AVDD soft-start time control

C201, C202 put closed to L201

C210: AVDD and VGH delay time control

C109 put closed to Pin 8

C231 put closed to Pin 20

Current limit R to reduce inrush

C230 put closed to Pin 22

Layout closely to pin15 and far from L202 and D202

1/2 AVDD soft-start

T315HW02 V3 Tcom MEMC Board

Wednesday, October 01, 2008

Close to U103 pin38

Close to U103 pin32

Close to U103 pin47

ISL24813 Programmable Gamma Buffer

T315HW02 V3 Tcom MEMC Board

VG1 & VG22 => L255.

Close to U103 pin8

Negative Gamma Value

Close to U103 pin15

Close to U103 pin43

Close to U103 pin22

Max9669 Programmable Gamma Buffer

Close to U103 pin30

Positive Gamma Value

Close to U103 pin29

Close to U103 pin23

Wednesday, October 01, 2008

Closed to pin117 of U401

When ODEN is high,

Closed to pin56 of U401

When ODEN is low or OPEN,

Data Mapping Setting Table

Closed to pin65 of U401

Closed to pin8 of U402

Closed to pin127 of U401

Closed to pin33 of U401

T315HW02 V3 Tcom MEMC Board

Wednesday, October 01, 2008

T315HW02 V3 Tcom MEMC Board

T315HW02 V3 Tcom\MEMC Board

T315HW02 V3 Tcom MEMC Board

T315HW02 V3 Tcom\MEMC Board

T315HW02 V3 Tcom MEMC Board

Wednesday, October 01, 2008

T315HW02 V3 Tcom MEMC Board

Wednesday, October 01, 2008

When ODEN is high,

Closed to pin56 of U300

Closed to pin117 of U300

When ODEN is low or OPEN,

Data Mapping Setting Table

Closed to pin65 of U300

Closed to pin8 of U301