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B GIO DC V O TO

TRNG I HC S PHM K THUT HNG YN


PHM C THUN

TRIN KHAI H THNG NHNG TRN NIOS
V NG DNG IU KHIN THIT B
QUA MY TNH
N TT NGHIP I HC
HNG YN - 2014
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B GIO DC V O TO
TRNG I HC S PHM K THUT HNG YN
PHM C THUN
TRIN KHAI H THNG NHNG TRN NIOS
V NG DNG IU KHIN THIT B
QUA MY TNH
NGNH: CNG NGH THNG TIN
CHUYN NGNH: CNG NGH MY TNH

N TT NGHIP I HC
NGI HNG DN
Th.S L TRUNG HIU



HNG YN - 2014
Trin khai h thng nhng trn NIOS v iu khin thit b qua my tnh

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MC LC
MC LC ...................................................................................................... 3
DANH SCH HNH V ................................................................................ 6
DANH SCH BNG BIU ........................................................................... 9
DANH SCH T VIT TT ...................................................................... 10
CHNG 1: TNG QUAN V TI ................................................... 11
L do chn ti ......................................................................... 11 1.1
Mc tiu ca ti ...................................................................... 12 1.2
Gii hn v phm vi ca ti .................................................... 12 1.3
Ni dung thc hin ...................................................................... 12 1.4
Phng php tip cn .................................................................. 13 1.5
CHNG 2: C S L THUYT ............................................................ 14
Tng quan v FPGA .................................................................... 14 2.1
2.1.1 FPGA l g? .............................................................................. 14
2.1.2 Tm tt lch s pht trin ca FPGA ......................................... 14
2.1.3 Ti sao cn s dng FPGA ........................................................ 15
2.1.4 Cc ng dng ca FPGA ........................................................... 16
2.1.5 Cu trc ca FPGA ................................................................... 16
2.2. KIT Altera DE2. ........................................................................ 18
2.3. Phn mm Quartus II ................................................................... 21
2.3.1. Gii thiu Quartus II ................................................................. 21
2.3.2. Thit k d n bng Quartus II. ................................................. 23
2.3.3. Xy dng h thng bng SoPC( Qsys) trn Quartus II ............... 30
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2.4. Phn mm lp trnh NIOS II ........................................................ 35
2.5. Truyn thng qua my tnh .......................................................... 39
2.6. Avalon Bus ................................................................................. 43
2.6.1. Avalon Bus Module .................................................................. 45
2.6.2. Cc thit b ngoi vi Avalon ...................................................... 46
CHNG 3: NI DUNG THC HIN ..................................................... 48
S tng qut h thng ............................................................. 48 3.1
Chi tit thit k h thng ............................................................. 50 3.2
3.2.1. NIOS II Processor nios2_qsys_0 .............................................. 50
3.2.2. JTAG Debug Module jtag_uart_0 ........................................... 51
3.2.3. Rs232 UART( Rs232 Serial Port) ........................................... 51
3.2.4. SRAM On Chip onchip_memory2_0 ...................................... 52
3.2.5. EFAN ........................................................................................ 52
3.2.6. LCD .......................................................................................... 53
3.2.7. LED Controler pio_0 led_green ........................................... 56
3.2.8. Avalon Bus ............................................................................... 56
Thit k giao din iu khin trn my tnh. ................................ 59 3.3
Lu thut ton ........................................................................ 61 3.4
3.4.1. Qu trnh gi ............................................................................... 61
3.4.2. Qu trnh nhn ........................................................................... 62
S nguyn l. ......................................................................... 64 3.5
3.5.1. Kt ni chn tn hiu iu khin ngoi vi ..................................... 64
3.5.2. S ghp ni Rs232. ............................................................... 65
3.5.3. S module mn hnh LCD .................................................... 66
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3.5.4. S nguyn l Relay 4 knh ................................................... 67
Hnh nh module thc t ............................................................. 69 3.6
CHNG 4: KT LUN .......................................................................... 70
Kt qu t c ca ti ......................................................... 70 4.1
Hn ch ca ti ....................................................................... 71 4.2
Hng pht trin ca ti.......................................................... 71 4.3
TI LIU THAM KHO ............................................................................. 72
PH LC ..................................................................................................... 73



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DANH SCH HNH V
Hnh 2-1: Cu trc tng th ca FPGA ......................................................... 16
Hnh 2-2: Khi logic FPGA ......................................................................... 17
Hnh 2-3: KIT Altera DE2............................................................................ 19
Hnh 2-4: Cc thnh phn trn KIT Altera DE2............................................ 19
Hnh 2-5: Giao din chnh ............................................................................ 21
Hnh 2-6: Design Flow ................................................................................. 22
Hnh 2-7: Khi to d n.............................................................................. 23
Hnh 2-8: ng dn, tn d n, tn thc th chnh. .................................... 24
Hnh 2-9: Add file. ....................................................................................... 24
Hnh 2-10: Chn Device .............................................................................. 25
Hnh 2-11: Cng c thit k, m phng. ....................................................... 26
Hnh 2-12: Kt thc...................................................................................... 26
Hnh 2-13: New Source ................................................................................ 27
Hnh 2-14: Trnh son tho trn Quartus II ................................................... 27
Hnh 2-15: Ca s Assignment Editor dng gn chn .............................. 28
Hnh 2-16: Ca s Programer ....................................................................... 29
Hnh 2-17: ng dn n th mc Usb-Blaster Driver. .............................. 30
Hnh 2-18: Chn h thng SoPC da trn ngn ng Verilog hoc VHDL ... 31
Hnh 2-19: Chn NIOS II processor ............................................................ 32
Hnh 2-20: Chn Debug level ....................................................................... 32
Hnh 2-21: To b nh h thng. .................................................................. 33
Hnh 2-22: JTAG UART .............................................................................. 34
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Hnh 2-23: H thng SoPC ti thiu. ............................................................ 34
Hnh 2-24: To thm I/O cn thit cho h thng NIOS II ............................. 35
Hnh 2-25: Chn workspace cho d n. ........................................................ 36
Hnh 2-26: Giao din chng trnh phn mm NIOS II ................................ 36
Hnh 2-27: To d n mi vi NIOS II ........................................................ 37
Hnh 2-28: Trnh son tho .......................................................................... 38
Hnh 2-29: Np xung KIT .......................................................................... 38
Hnh 2-30: Rs232 Pin table .......................................................................... 41
Hnh 2-31: S khi mt Avalon bus module trong thit k ...................... 46
Hnh 3-1: S tng qut h thng .............................................................. 48
Hnh 3-2: Chn phin bn NIOS II/e ............................................................ 50
Hnh 3-3: Component Jtag_uart ................................................................... 51
Hnh 3-4: Component Rs232 ........................................................................ 51
Hnh 3-5: SRAM On Chip............................................................................ 52
Hnh 3-6: EFAN ........................................................................................... 52
Hnh 3-7: Lcd_data ...................................................................................... 53
Hnh 3-8: Lcd_rw ......................................................................................... 54
Hnh 3-9: Lcd_rs .......................................................................................... 54
Hnh 3-10: Lcd_e ......................................................................................... 55
Hnh 3-11: Led control ................................................................................. 56
Hnh 3-12: Giao tip gia cng Slave v Avalon Bus Module trong qu trnh
c t Slave .................................................................................................. 57
Hnh 3-13: Thi gian trong qu trnh c d liu t cng slave .................... 57
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Hnh 3-14: Cc tn hiu giao tip v thi gian trong khi ghi d liu ra cng
slave .............................................................................................................. 58
Hnh 3-15: Giao din chng trnh chnh ..................................................... 60
Hnh 3-16: Giao din chng trnh iu khin ............................................. 60
Hnh 3-17: Lu thut ton qu trnh gi d liu ...................................... 61
Hnh 3-18: Lu thut ton qu trnh nhn d liu .................................... 63
Hnh 3-19: Connect to GPIO1( DE2 KIT) .................................................... 64
Hnh 3-20: Mch chun giao tip Rs232 dng IC Max232 ........................... 65
Hnh 3-21: S module mn hnh LCD ..................................................... 66
Hnh 3-22: S nguyn l Module Relay 4 knh ....................................... 68
Hnh 3-23: Module Relay 4 knh - 5V-220V/10A ........................................ 69

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DANH SCH BNG BIU
Bng 3-1: Chn kt ni tn hiu iu khin GPIO1 ....................................... 65
Bng 3-2: Rs232 pin assignments ................................................................. 66
Bng 3-3: LCD Module pin assignment ....................................................... 67


Trin khai h thng nhng trn NIOS v iu khin thit b qua my tnh

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DANH SCH T VIT TT
T vit tt T y Gii thch
ASIC Application-Specific Integrated
Circuit
Vi mach tch hp chuyn dng

CPLD Complex Programmable Logic
Device
Thit b logic c th lp trnh
c.
DE Development and Education
FPGA Field programmable gate array Vi mch dng cu trc mng
phn t logic lp trnh c
LUT Look Up Table Bng tm kim
PLA Programmable Logic Array Mng logic kh trnh
SOPC System on a Programmable Chip
Builder
Xy dng h thng trn mt
CHIP
VHDL VHSIC Hardware Description
Language
Ngn ng lp trnh phn cng




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CHNG 1: TNG QUAN V TI
Trong chng ny s trnh by tng quan v ti bao gm l do chn ti,
mc tiu, gii hn, phm vi nghin cu, ni dung thc hin v phng php tip
cn ca ti.
L do chn ti 1.1
Trong nhng nm gn y, xu hng ca th gii l pht trin mnh cng
ngh bn dn. Mt chip c th tch hp trn n nhiu cng logic c th ng dng
trong nhiu lnh vc. Ngy nay, ngnh cng nghip ch to phn cng lun c
nhng t ph khng ngng. T cc mch in n gin n cc mch s, mch
tch hp, kin trc mch ngy mt tr nn phc tp hn.
Cc h thng nhng c pht trin trn FPGA ang c s dng rng ri
cho cc nghin cu, ng dng, v o to hin nay bi c tnh linh hot cho cc
thit k thit b trn FPGA. c tnh c th cu hnh li ca FPGA cho php to ra
phin bn thit k ca mt thit b mong mun cho cc ng dng khc nhau. Nh s
dng cc ngn ng m phng phn cng VHDL, Verilog v mt s cng c thit
k, m phng, ngy nay, phng th nghim, c s o to, hay mt c nhn c th
a ra tng, mt mu thit k mt b x l mong mun, v thc thi n trn
FPGA. Vi nhng ng dng rng ri trong nhiu ngnh cng nghip a dng, hu
ht cc h nhng hin nay u c pht trin trn cng ngh FPGA. Mt khc,
FPGA c h tr rt nhiu cc thit b ngoi vi to iu kin thun li cho vic
pht trin h thng nhng, pht trin cc ng dng iu khin trn FPGA kt ni
vi cc thit b ngoi vi.
c c bc u lm quen v nghin cu v cng ngh FPGA t c
th nghin cu su hn v cng ngh nn Em chn ti nghin cu: Trin
khai h thng nhng trn nios v iu khin thit b qua my tnh lm ti
tt nghip i hc ca mnh.
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Trong qu trnh thc hin ti ny, do cn hn ch v kin thc v thi
gian nn khng trnh c nhng thiu st. Em knh mong qu thy c
thng cm v b qua ng thi em cng mong nhn c nhng gp v
ch bo thm ca qu thy c.
Mc tiu ca ti 1.2
To bc u cho Sinh Vin nghin cu ng dng ca Altera DE2 Cylone
II ni ring v FPGA ni chung.
Nm c trnh t thit k mt ng dng s dng NIOS trn DE2: Cch
lp trnh, thit k phn cng, cng nh cch vn hnh giao tip gia Kit
DE2 vi cc thit b ngoi vi.
Thit k h thng nhng trn NIOS v ng dng iu khin thit b qua
my tnh.
Rn luyn kh nng t duy, sng to v kinh nghim lm vic trong thc t.
Gii hn v phm vi ca ti 1.3
Nghin cu FPGA ca Altera. nguyn l hot ng ca Kit Altera DE2
Cylone II. Tm hiu v cc cng vo ra ca Kit DE2, kt ni vi my tnh
v cc thit b ngoi vi.
a ra c gii php v chc nng ca sn phm, thit k mch v lp
trnh t c yu cu t ra ca h thng iu khin.
Nghin cu v pht trin h thng nhng trn FPGA ca hng Altera.
Vit chng trnh iu khin trn my tnh kt ni vi FPGA iu khin
thit b ngoi vi.
Ni dung thc hin 1.4
Tm hiu, nghin cu nguyn l hot ng ca Kit Altera DE2 Cylone II.
Tm hiu v cc cng vo ra ca Kit DE2, kt ni vi my tnh v cc thit
b ngoi vi.
Trin khai h thng nhng trn NIOS v iu khin thit b qua my tnh

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a ra c gii php v chc nng ca sn phm, thit k mch v lp
trnh t c yu cu t ra ca h thng iu khin.
S dng tt cng c lp trnh NIOS to ng dng iu khin thit b qua
my tnh.
Lp t, chy th v hon thin h thng.
Quyn bo co vit v trnh by theo ng mu quy nh.
Phng php tip cn 1.5
Cch tip cn : Nghin cu cc ngn ng, phn mm thit k h thng nhng
trn nn tng Altera nh VHDL, Verilog, Qsys trn Quartus II v vit phn mm
trn NIOS II. Lp trnh giao din iu khin thit b trn my tnh bng Visual
Studio 2010.
S dng cc phng php nghin cu:
Phng php c ti liu.
Phng php phn tch mu.
Phng php thc nghim.
Trin khai h thng nhng trn NIOS v iu khin thit b qua my tnh

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CHNG 2: C S L THUYT
Chng ny s trnh by c s l thuyt ca ti bao gm tng quan v
FPGA, gii thiu phn mm, cng c s dng trong ti, cc bc trin khai h
thng, truyn thng qua my tnh.
Tng quan v FPGA 2.1
2.1.1 FPGA l g?
Field-programmable gate array( FPGA) l vi mch dng cu trc mng
phn t logic m ngi dng c th lp trnh c.( Ch field y mun ch n
kh nng ti lp trnh "bn ngoi" ca ngi s dng, khng ph thuc vo dy
chuyn sn xut phc tp ca nh my bn dn). Vi mch FPGA c cu thnh t
cc b phn:
Cc khi logic c bn lp trnh c( logic block)
H thng mch lin kt lp trnh c
Khi vo/ra( IO Pads)
Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...
2.1.2 Tm tt lch s pht trin ca FPGA
FPGA c thit k u tin bi Ross Freeman, ngi sng lp cng ty Xilinx
vo nm 1984, kin trc mi ca FPGA cho php tch hp s lng tng i ln
cc phn t bn dn vo 1 vi mch so vi kin trc trc l CPLD. FPGA c kh
nng cha ti t 100.000 n hng vi t cng logic, trong khi CPLD ch cha t
10.000 n 100.000 cng logic; con s ny i vi PAL, PLA cn thp hn na ch
t vi nghn n 10.000.
CPLD c cu trc t s lng nht nh cc khi SPLD( Simple
programmable devices, thut ng chung ch PAL, PLA). SPLD thng l mt mng
logic AND/OR lp trnh c c kch thc xc nh v cha mt s lng hn ch
cc phn t nh ng b( clocked register). Cu trc ny hn ch kh nng thc
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hin nhng hm phc tp v thng thng hiu sut lm vic ca vi mch ph
thuc vo cu trc c th ca vi mch hn l vo yu cu bi ton.
Kin trc ca FPGA l kin trc mng cc khi logic, khi logic, nh hn
nhiu nu em so snh vi mt khi SPLD, u im ny gip FPGA c th cha
nhiu hn cc phn t logic v pht huy ti a kh nng lp trnh ca cc phn t
logic v h thng mch kt ni, t c mc ch ny th kin trc ca FPGA
phc tp hn nhiu so vi CPLD.
Mt im khc bit vi CPLD l trong nhng FPGA hin i c tch hp
nhiu nhng b logic s hc s b ti u ha, h tr RAM, ROM, tc cao,
hay cc b nhn cng( multiplication and accumulation, MAC), thut ng ting
Anh l DSP slice dng cho nhng ng dng x l tn hiu s DSP.
Ngoi kh nng ti cu trc vi mch ton cc, mt s FPGA hin i cn h
tr ti cu trc cc b, tc l kh nng ti cu trc mt b phn ring l trong khi
vn m bo hot ng bnh thng cho cc b phn khc.
2.1.3 Ti sao cn s dng FPGA
FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC,
nhng nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k
trn th vin logic th FPGA khng t c mc ti u nh nhng loi ny, v
hn ch trong kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u
vit hn ch c th ti cu trc li khi ang s dng, cng on thit k n gin
do vy chi ph gim, rt ngn thi gian a sn phm vo s dng.
Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc
mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im: tc v
ti lp trnh ca FPGA thc hin n gin hn; kh nng lp trnh linh ng hn; v
khc bit quan trng nht l kin trc ca FPGA cho php n c kh nng cha khi
lng ln cng logic( logic gate), so vi cc vi mch bn dn lp trnh c c
trc n.
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2.1.4 Cc ng dng ca FPGA
ng dng ca FPGA bao gm: x l tn hiu s DSP, cc h thng hng
khng, v tr, quc phng, tin thit k mu ASIC( ASIC prototyping), cc h
thng iu khin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m
hc, m hnh phn cng my tnh, my nh c( My nh c Hydra c 32 b vi x
l cng thm FPGA chin thng kin tng quc t Michael Adams trong nm
2005.
Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp
nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi
ra nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi
lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.
2.1.5 Cu trc ca FPGA
Cu trc tng th ca mt FPGA c minh ha hnh sau:

Hnh 2-1: Cu trc tng th ca FPGA
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Khi Logic FPGA

Hnh 2-2: Khi logic FPGA
Phn t chnh ca FPGA l cc khi logic(logic block). Khi logic c cu
thnh t LUT v mt phn t nh ng b flip-flop.
LUT( Look up table) l khi logic c th thc hin bt k hm logic no t 4
u vo, kt qu ca hm ny ty vo mc ch m gi ra ngoi khi logic trc tip
hay thng qua phn t nh flip-flop.
Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi
nim SLICE, 1 Slice to thnh t gm 4 khi logic, s lng cc Slices thay i t
vi nghn n vi chc nghn ty theo loi FPGA.
Nu nhn cu trc tng th ca mng LUT th ngoi 4 u vo k trn cn h
tr thm 2 u vo b sung t cc khi logic phn b trc v sau n nng tng s
u vo ca LUT ln 6 chn. Cu trc ny l nhm tng tc cc b s hc logic.
H thng mch lin kt
Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai
phng ngang v ng, ty theo tng loi FPGA m cc ng kt ni c chia
thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c 3 loi kt ni: ngn,
di v rt di. Cc ng kt ni c ni vi nhau thng qua cc khi chuyn
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mch lp trnh c( programmable switch), trong mt khi chuyn mch cha mt
s lng nt chuyn lp trnh c m bo cho cc dng lin kt phc tp khc
nhau.
Cc phn t tch hp sn.
Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch
hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4,5
ca Xilinx c cha nhn x l PowerPC, hay trong Atmel FPSLIC tch hp nhn
AVR, hay cho nhng ng dng x l tn hiu s DSP trong FPGA c tch hp
cc DSP Slide l b nhn cng tc cao, thc hin hm A*B+C, v d dng
Virtex ca Xilinx cha t vi chc n hng trm DSP slices vi A, B, C 18-bit.
Block RAM
Ngoi ra nhng FPGA ca Xilinx cn c block RAM, c th mng tng
nh l b nh nh nm trong FPGA. Nhng FPGA ny tuy nh( khong vi chc k
l bit cho n vi triu bit ty theo loi FPGA) nhng c th dng to mt b
nh nh nh ROM, FIFO.
2.2. KIT Altera DE2.
DE2( Development and Education ) la mt cng c cho vic thit k nng cao
cc thit b a phng tin, lu tr v mng.
DE2 s dng cng ngh state-of- the-art trong c phn cng v cc cng c
thit k nh my tnh gip m rng phm vi ng dng. DE2 c nhiu tnh nng ph
hp vi c vic s dng trong cc phng lab v cc h thng s tinh vi. Altera cung
cp cc cng c h tr ph hp cho DE2, gm c cc hng dn, cc bi lab trn
DE2, v cc bi minh ha
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Hnh 2-3: KIT Altera DE2
Cc thnh phn v thng s ca KIT

Hnh 2-4: Cc thnh phn trn KIT Altera DE2
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Altera Cyclone II 2C35 FPGA
Altera Serial Configuration device - EPCS16
USB Blaster dng lp trnh h thng t PC, h tr cc ch JTAG cng
nh iu khin trc tip khi s dng NIOS II
512 Kbyte SRAM
8 Mbyte SDRAM
4 Mbyte Flash memory
Khe cm SD Card
4 phm nhn PushButton KEY[3:0]
18 Switch( cp mc 0 hay 1)
18 n LEDR v 9 n LEDG
C hai ngun clock l 50 MHz v 27 MHz
Chip gii m m thanh 24 bits vi cc jack cm line-in, line-out v
microphone
VGA DAC( 10-bit high-speed triple DACs) vi cng VGA
TV Decoder( NTSC/PAL) vi TV-in( Video-in)
Cng 10/100 Ethernet
B iu khin USB host/slave
RS 232 vi cng kt ni 9 chn
Cng PS/2 giao tip vi chut v keyboard
Cng hng ngoi
40 chn m rng
LDC 2x16
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2.3. Phn mm Quartus II
2.3.1. Gii thiu Quartus II
Quartus II l cng c chnh c s dng trong qu trinh thc hin ti.
c cung cp v cp nht thng xuyn bi Altera. y l cng c thit k tt
nht cho cc dng chip FPGA ca Altera bao gm c Cyclon II 2C35 c trn DE2.
L cng c phn tch v tng hp thit k HDL, n cho php nh pht trin
thc hin thit k ca h, ng thi cho php phn tch thi gian, kim tra s
RTL, m phng h thng v cu hnh sn phm mt cch ph hp nht.

Hnh 2-5: Giao din chnh




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Thit k FPGA vi SoPC( Qsys) trn Quartus II.
Di y l quy trnh thit k FPGA vi cc phn mm thit k FPGA ni
chung v Quartus II ni ring:

Hnh 2-6: Design Flow
Design Entry Mch sau thit k s c m t bi cc ngn ng m t
phn cng nh VHDL hay Verilog, hoc cng c th dng s
Schematic.
Synthesis Cng c t hp s t hp mch to ra mt file netlist c cha
cc phn t logic v cc kt ni gia chng.
Function Simulation Chc nng ca mch sau t hp s c kim nh.
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Fitting Cng c my tnh s t cc phn t logic c nh ngha trong
file netlist xung cc phn t logic trong con chip FPGA thc t. ng thi
chn ra cc ng dy kt ni chng vi nhau.
Timming Analysis Phn tch tr truyn dn trn cc ng dy khc
nhau nhm a ra cc ch th gip ci thin hiu nng lm vic ca mch.
Timming Simulation Kim tra ng thi c v mt chc nng ln thi
gian ca mch.
Programming and Configuration Thc hin mch trn con chip vt l
bng cch cu hnh cc phn t logic trn chip v thnh lp cc kt ni cn
thit

2.3.2. Thit k d n bng Quartus II.
To d n, vit source code, bin dch v np xung KIT trn Quartus II.
ti s dng phin bn phn mm Quartus 12.0 Web Edition.
Khi to d n: File New Project Wizard Next.

Hnh 2-7: Khi to d n
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24

in ng dn lu d n, tn d n v tn thc th chnh ca d n Next.

Hnh 2-8: ng dn, tn d n, tn thc th chnh.
Thm file thit k vo trong d n Next.

Hnh 2-9: Add file.
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- Thm file mi cho d n: in tn file name Add.
- Thm file c sn: Browse ng dn n file to sn v Add.
- Nu to xong d n m mun thm file thit k VHDL vo trong d n:
mc Project Navigator, chuyn sang tab file, click chut phi vo file
Add/Remove File in Project Add.
Chn dng thit b s dng.

Hnh 2-10: Chn Device
i vi ti s dng KIT Altera Cyclone II DE2:
- Family: Cyclone II.
- Available device: EP2C35F672C6( DE2).





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26


Cc cng c thit k vi mch khc s dng vi phn mm Quartus II pht
trin d n Next.

Hnh 2-11: Cng c thit k, m phng.
Kt thc qu trnh khi to d n: Finish.

Hnh 2-12: Kt thc
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Chn File New VHDL File Ok Chn ni lu d n Save.

Hnh 2-13: New Source
Trnh son tho:

Hnh 2-14: Trnh son tho trn Quartus II
Gn chn:
- Nhp chn Assignments > Assignment Editor. Nhp i vo <<new>>.
Nhp chn tn hiu t danh sch tri xung lm chn c gn. Tip n
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28

nhp i vo hp bn phi hp dnh cho tn hiu cn gn( ct

Location).
Chn chn PIN_XYZ t danh mc hoc c th g trc tip vo hp
Location.

Hnh 2-15: Ca s Assignment Editor dng gn chn
- Tng t nh trn, thc hin gn chn cho cc u vo khc
- Sau khi hon thnh vic gn chn, nhp chn File > Save. ng ca s
Assignment Editor, nhp chn Yes v bin dch li mch.
Ch : Nn chn tn cc tn hiu trng vi trong bng
DE1_pin_assigment.csv th khi gn chn ta ch cn vo assigment > import
assigment,trong ng dn ta tr n file DE1_pin_assigment.csv ri n OK v lm
theo bc 3 l xong.Khng mt thi gian gn chn bng tay.
Bin dch
- Khi vit code xong cho mt chng trnh no bn cn bin dch
to ra nhng file dng np ln KIT DE2
- Bc 1: Nhp chn mc Processing > Start Complication. Bin dch thnh
cng( hay khng thnh cng) s c thng bo trn hp thoi bung ra sau
khi qu trnh bin dch kt thc. Xc nhn bng cch nhp nt OK.
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- Bc 2: Khi bin dch hon thnh, mt bo co bin dch c a ra. Ca
s ny cng c th m ra bt k lc no bng cch nhp chn Processing >
Complication Report. Trong bo co ny bao gm mt s danh mc bn
tri ca s, nhp vo cc danh mc ny thy thng tin chi tit ca danh
mc ny hin ln bn phi ca s.
- Bc 3: Sa cc li: Chn mc Analysis & Synthesis > Messages hin
th thng bo li. Nhp i vo thng bo li u tin, dng lnh li s
c nh du trn trnh son tho vn bn, sa li cho ng ri bin dch
li d n.
Np xung KIT
- Gt chuyn mch RUN/PROG sang v tr RUN. Nhp chn Tools >
Programmer c ca s nh trong hnh. nh du vo ty chn
Program/Configue cho php np tp cu hnh xxxxxx.sof.

Hnh 2-16: Ca s Programer
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Ci Driver Usb-Blaster.
- c th np code xung KIT, ta phi ci Driver Usb-Blaster.
- Vo Manage(Chut phi vo Computer) Device ManageOther Device
- Chut phi vo Usb-Blaster Update Driver SoftwareBrowse my
computer for driver softwareChn ng dn ti th mc Driver/Usb-
Blaster(C sn trong th mc ci Altera Quartus) Next Close.

Hnh 2-17: ng dn n th mc Usb-Blaster Driver.
2.3.3. Xy dng h thng bng SoPC( Qsys) trn Quartus II
H thng SoPC( System on Programable Chip) bao gm cc thnh phn
chnh:
CPU Nios II
Memory( onchip memory hoc Ram ngoi)
JTAG
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Port I/O
Cc component
Ta m tool SoPC builder( Qsys) trong phn mm QUATUS II
Sau t tn h thng, chn ngn ng m t phn cng l Verilog hay
VHDL, nhn OK.

Hnh 2-18: Chn h thng SoPC da trn ngn ng Verilog hoc VHDL
To VXL NIOS cho h thng.
Chn kiu NIOS II: ty vo tnh nng ca h thng m chn li NIOS II cho
ph hp. Trong vi d ny v khng cn nhiu chc nng nn ta chon phin bn n
gin nht l phin bn NIOS II/e bng cch check vo mc NIOS II/e nh hnh bn
di.
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Hnh 2-19: Chn NIOS II processor
i vi kiu NIOS n gin ta tip tc next n phn chn thnh phn JTAG.
Trong bi ny ta s dng phin bn NIOS II/e nn ch cho php chn JTAG level 1.
Ri nhn next hon thnh khai bo

Hnh 2-20: Chn Debug level
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To b nh cho NiOS II.
Nios II ch l mt li vi x l ch cha phi l vi iu khin do n cn phi
c ti thiu nh d liu v b nh chng trnh c th hot ng c.
n gin nht l dng On-Chip Memory bng cch double_click On-Chip
Memory(RAM or ROM). Nhng lu nn chn dung lng b nh ph hp tng
ng dng. Chiu rng mi nh l 32 bit nu l kit DE2, nu l DE1 ta chn b
nh l 16KB. Sau chn Finish hon thnh.
Khi to b nh xong, ta to kt ni gia Nios II v b nh nu n cha c
kt ni. Ch l phi kt ni c hai bus instruction_master v data_master.

Hnh 2-21: To b nh h thng.

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To UART thng qua chun JTAG cho NIOS
Trong Communication double click chn JTAG UART. Nu khng bit chnh
g ht th c nhn Finish hon thnh.

Hnh 2-22: JTAG UART
Sau bc ny ta c h thng n gin c th hot ng c nh hnh sau

Hnh 2-23: H thng SoPC ti thiu.
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To I/O port cho NIOS II

Hnh 2-24: To thm I/O cn thit cho h thng NIOS II
2.4. Phn mm lp trnh NIOS II
Vic vit phn mm cho phn cng FPGA cng tng t nh qu trnh pht
trin phn mm cho bt k h vi iu khin no khc. B cng c phn mm Nios II
EDS chuyn dng vit phn mm chy trn b vi x l NiosII.
Nios II Software Build Tools for Eclipse cung cp 2 quy trnh khc nhau gm
rt nhiu thuc tnh v cng c m ngun m nhm to ra chng trnh phn mm
Nios II.









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Cc bc lm vic trn NIOS
Chn khng gian lu tr d n

Hnh 2-25: Chn workspace cho d n.
Giao din chnh

Hnh 2-26: Giao din chng trnh phn mm NIOS II





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To d n

Hnh 2-27: To d n mi vi NIOS II
u tin chn SOPC Information File name chnh l h thng SOPC m
chng ta to ra bng tool SoPC trn Quartus II. Browse vo h thng SOPC
to ra.
Khi chn xong SOPC th CPU name s hin ln tn CPU m chng ta t
phn xy dng h thng. V sau l t Project name ri Finish. Kt thc qu
trnh to d n.
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Trnh son tho

Hnh 2-28: Trnh son tho
Np phn mm xung KIT

Hnh 2-29: Np xung KIT
Right Click, chn Run As 3 Nios II Hardware.
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2.5. Truyn thng qua my tnh
Ngy nay cc thit b o lng, iu khin ... u phi giao tip vi my tnh
quan st thng s v ch hot ng ca thit b nh th no? Chun giao tip
c coi l n gin v d dng l RS232. Hu nh cc thit b u c giao
tip vi my tnh thng qua chun ny.
Vn giao tip gia PC v vi iu khin rt quan trng trong cc ng dng
iu khin, o lng... Ghp ni qua cng ni tip RS232 l mt trong nhng k
thut c s dng rng ri ghp ni cc thit b ngoi vi vi my tnh.N l mt
chun giao tip ni tip dng nh dng khng ng b, kt ni nhiu nht l 2 thit
b , chiu di kt ni ln nht cho php m bo d liu l 12.5 n 25.4m, tc
20kbit/s i khi l tc 115kbit/s vi mt s thit b c bit. ngha ca
chun truyn thng ni tip ngha l trong mt thi im ch c mt bit c gi i
dc theo ng truyn.
C hai phin bn RS232 c lu hnh trong thi gian tng i di l
RS232B v RS232C. Nhng cho n nay th phin bn RS232B c th t c dng
cn RS232C hin vn c dng v tn ti thng c gi l tn ngn gn l
chun RS232
Cc my tnh thng c 1 hoc 2 cng ni tip theo chun RS232C c gi
l cng Com. Chng c dng ghp ni cho chut, modem, thit b o
lng...Trn main my tnh c loi 9 chn hoc li 25 chn ty vo i my v
main ca my tnh. Vic thit k giao tip vi cng RS232 cng tng i d dng,
c bit khi chn ch hot ng l khng ng b v tc truyn d liu thp.
u im ca giao din ni tip Rs232.
Kh nng chng nhiu ca cc cng ni tip cao
Thit b ngoi vi c th tho lp ngay c khi my tnh ang c cp
in
Cc mch in n gin c th nhn c in p ngun nui qua cng
ni tip
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Nhng c im cn lu trong chun Rs232
Trong chun RS232 c mc gii hn trn v di( logic 0 v 1) l +-12V.
Hin nay ang c c nh tr khng ti trong phm vi t 3000 m - 7000 m.
Mc logic 1 c in p nm trong khong -3V n -12V, mc logic 0 t +-3V
n 12V.
Tc truyn nhn d liu cc i l 100kbps( ngy nay c th ln hn) Cc
li vo phi c in dung nh hn 2500pF.
Tr khng ti phi ln hn 3000 m nhng phi nh hn 7000 m.
di ca cp ni gia my tnh v thit b ngoi vi ghp ni qua cng ni
tip RS232 khng vt qua 15m nu chng ta khng s model.
Cc gi tr tc truyn d liu chun : 50, 75, 110, 750, 300, 600, 1200,
2400, 4800, 9600, 19200, 28800, 38400....56600, 115200 bps.
Cc mc in p ng truyn
RS 232 s dng phng thc truyn thng khng i xng, tc l s dng tn
hiu in p chnh lch gia mt dy dn v t. Do ngay t u tin ra i n
mang v li thi ca chun TTL, n vn s dng cc mc in p tng thch
TTL m t cc mc logic 0 v 1. Ngoi mc in p tiu chun cng c nh cc
gi tr tr khng ti c u vo bus ca b phn v cc tr khng ra ca b pht.
Mc in p ca tiu chun RS232C( chun thng dng by gi) c m t
nh sau:
Mc logic 0 : +3V , +12V
Mc logic 1 : -12V, -3V
Cc mc in p trong phm vi t -3V n 3V l trng thi chuyn tuyn.
Chnh v t - 3V ti 3V l phm vi khng c nh ngha, trong trng hp thay
i gi tr logic t thp ln cao hoc t cao xung thp, mt tn hiu phi vt qua
qung qu trong mt th gian ngn hp l. iu ny dn n vic phi hn ch
v in dung ca cc thit b tham gia v ca c ng truyn. Tc truyn dn
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41

ti a ph thuc vo chiu di ca dy dn. a s cc h thng hin nay ch h tr
vi tc 19,2 kBd .
Cng Rs232.

Hnh 2-30: Rs232 Pin table
Chc nng ca cc chn nh sau:
- Chn 1 : Data Carrier Detect( DCD) : Pht tn hiu mang d liu
- Chn 2: Receive Data( RxD) : Nhn d liu
- Chn 3 : Transmit Data( TxD) : Truyn d liu
- Chn 4 : Data Termial Ready( DTR) : u cui d liu sn sng c kch
hot bi b phn khi mun truyn d liu
- Chn 5 : Singal Ground( SG) : Mass ca tn hiu
- Chn 6 : Data Set Ready( DSR) : D liu sn sng, c kch hot bi b
truyn khi n sn sng nhn d liu
- Chn 7 : Request to Send : yu cu gi,b truyn t ng ny ln mc
hot ng khi sn sng truyn d liu
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- Chn 8 : Clear To Send( CTS) : Xa gi ,b nhn t ng ny ln
mc kch hot ng thng bo cho b truyn l n sn sng nhn tn
hiu
- Chn 9 : Ring Indicate( RI) : Bo chung cho bit l b nhn ang nhn tn
hiu rung chung
Qu trnh truyn d liu
Truyn d liu qua cng ni tip RS232 c thc hin khng ng b. Do
vy nn ti mt thi im ch c mt bit c truyn( 1 k t). B truyn gi mt bit
bt u( bit start) thng bo cho b nhn bit mt k t s c gi n trong ln
truyn bit tip the . Bit ny lun bt u bng mc 0.. Tip theo l cc bit d
liu( bits data) c gi di dng m ASCII( c th l 5,6,7 hay 8 bit d liu) Sau
l mt Parity bit( Kim tra bit chn, l hay khng) v cui cng l bit dng - bit
stop c th l 1, 1,5 hay 2 bit dng.
Tc Baud
y l mt tham s c trng ca RS232. Tham s ny chnh l c trng cho
qu trnh truyn d liu qua cng ni tip RS232 l tc truyn nhn d liu hay
cn gi l tc bit. Tc bit c nh ngha l s bit truyn c trong thi
gian 1 giy hay s bit truyn c trong thi gian 1 giy. Tc bit ny phi c
thit lp bn pht v bn nhn u phi c tc nh nhau( Tc gia vi iu
khin v my tnh phi chung nhau 1 tc truyn bit)
Ngoi tc bit cn mt tham s m t tc truyn l tc Baud. Tc
Baud lin quan n tc m phn t m ha d liu c s dng din t
bit c truyn cn tc bit th phn nh tc thc t m cc bit c truyn.V
mt phn t bo hiu s m ha mt bit nn khi hai tc bit v tc baud l
phi ng nht
Mt s tc Baud thng dng: 50, 75, 110, 150, 300, 600, 1200, 2400,
4800, 9600, 19200, 28800, 38400, 56000, 115200 Trong thit b h thng dng
tc l 19200
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Khi s dng chun ni tip RS232 th yu cu khi s dng chun l thi gian
chuyn mc logic khng vt qu 4% thi gian truyn 1 bit. Do vy, nu tc bit
cng cao th thi gian truyn 1 bit cng nh th thi gian chuyn mc logic cng
phi nh. iu ny lm gii hn tc Baud v khong cch truyn.
Parity bit
y l bit kim tra li trn ng truyn. Thc cht ca qu trnh kim tra li
khi truyn d liu l b xung thm d liu c truyn tm ra hoc sa mt s li
trong qu trnh truyn . Do trong chun RS232 s dng mt k thut kim tra
chn l.
Mt bit chn l c b sung vo d liu c truyn cho thy s lng
cc bit "1" c gi trong mt khung truyn l chn hay l.
Mt Parity bit ch c th tm ra mt s l cc li ch hn nh 1,3,,5,7,9... Nu
nh mt bit chn c mc li th Parity bit s trng gi tr vi trng hp khng
mc li v th khng pht hin ra li. Do trong k thut m ha li ny khng
c s dng trong trng hp c kh nng mt vi bit b mc li.
2.6. Avalon Bus
Avalon bus l mt kin trc bus gin n, c thit k kt ni cc vi x l
nhng v cc thit b ngoi vi trong mt h-thng-trn-chip-kh-trnh( SOPC).
Avalon bus l mt giao tip m c t cc kt ni cng gia cc thit b master v
slave, ng thi c t thi gian lin lc gia cc thit b.
Mc ch thit k chnh ca Avalon bus l:n gin: cung cp mt giao thc
d hiu, d s dng. Ti u ha vic s dng ti nguyn cho cc bus logic: bo ton
cc yu t logic( loigic element) bn trong thit b logic kh trnh( PLD).
ng b ha cc qu trnh hot ng: va tch hp tt vi cc logic ca ngi
dng cng tn ti trn mt PLD, li va trnh c cc vn phn tch thi gian
phc tp.
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Avalon bus h tr bus a ch. Cc kin trc a ch ny to ra mt s linh hot
rt ln trong vic xy dng cc h thng SOPC, v to iu kin cho cc thit b
ngoi vi c bng thng rng. V d: mt thit b ngoi vi ch c th thc hin mt
qu trnh truyn truy-xut-b-nh-trc-tip( DMA) truyn d liu t thit b
ngoi vi vo b nh m khng cn mt vi x l trong ng truyn d liu.
Cc master v slave giao tip vi nhau da trn mt k thut gi l tha hip
pha slave( slave-side arbitration). K thut ny xc nh master no c nm
quyn giao tip vi slave trong trng hp nhiu master cng truy cp n mt
slave.
Chi tit v s tha hip ny c gi gn bn trong Avalon bus. Do , cc
giao tip master v slave rt chc, bt chp s lng cc master v slave c trn bus.
Mi bus master s giao tip vi Avalon bus nh th n l master duy nht trn
ng Avalon bus.
Cc master c th thc hin qu trnh truyn bt k lc no, min l chng
khng truy cp cng mt slave trong cng mt chu k bus.
Avalon bus c thit k thch nghi vi mi trng SOPC, do n l mt
kin trc bus tch hp( on-chip) rt nng ng, bao gm cc ti nguyn logic v
truyn bn trong mt thit b logic kh trnh. Mt vi nt chnh ca kin trc Avalon
l:
Giao tip vi cc thit b ngoi vi ng b vi xung clock Avalon. Do , s
sp xp cc tn hiu bo v tn hiu bt tay khng ng b v phc tp l iu
khng cn thit. Hot ng ca Avalon bus( v cng l ca ton h thng) c th
c phn tch bng cc k thut phn tch chun v ng b thi gian.
Tt c cc tn hiu u hot ng LOW hoc HIGH, iu ny cho php s
xoay vng ca h thng. Cc b a hp bn trong Avalon bus xc nh tn hiu no
iu khin thit b ngoi vi no. Cc thit b ngoi vi s khng cn phi c ng ra 3-
trng-thi ngay c khi thit b khng c chn hot ng.
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Cc tn hiu a ch, d liu v iu khin s dng cc cng ring bit, iu
ny lm n gin ha thit k ca cc thit b ngoi vi. Mt thit b ngoi vi khng
cn thit phi gii m cc chu k bus d liu v a ch, v cng khng cn phi tt
cc ng ra khi n khng c chn hot ng.
Khng gian a ch ln ti 4Gbyte: cc thit b ngoi vi v b nh c th c
gn bt k ni no trong khng gian a ch 32-bit.
Tch hp b gii m a ch: Avalon bus s t ng to cc tn hiu Chip
Select cho tt c cc thit b ngoi vi, rt thun tin trong vic thit k cc thit b
ngoi vi giao tip vi Avalon.
Avalon bus cng bao gm mt s cc c im v quy c h tr vic to
t ng cc h thng, bus, v thit b bng phn mm SOPC Builder.
2.6.1. Avalon Bus Module
Avalon bus module l xng sng ca mt module h thng. l con ng
chnh giao tip gia cc component trong mt thit k SOPC. Avalon bus
module l mt tp hp cc tn hiu iu khin, d liu, a ch v cc logic tha hip
m kt ni cc thnh phn to nn h thng. Avalon bus module thc hin mt kin
trc bus c th cu hnh c, c ngha l c th thay i ph hp vi nhu cu
kt ni cc thit b ngoi vi ca ngi thit k.
Avalon bus module c to mt cch t ng bi SOPC Builder, v th
ngi thit k h thng c th tit kim thi gian trong vic ni cc thit b vi
nhau. S khi ca mt Avalon bus module in hnh c trnh by trong hnh.
Avalon bus module s cung cp cc h tr sau cho nhng thit b ngoi vi kt
ni ti ng bus ny:
a hp ng d liu: Cc b a hp bn trong module Avalon bus s truyn
d liu t thit b slave c chn n thit b master thch hp.
Gii m a ch: b gii m a ch ca module ny s to ra cc tn hiu chip
select cho mi thit b ngoi vi, nh vy cc thit b ngoi vi khng cn gii m
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ng a ch to ra tn hiu chip select n gin ha cc thit k ca thit b
ngoi vi.
To trng thi ch: b to trng thi ch s m rng thm cc qu trnh
truyn bng mt hay nhiu chu k bus, iu ny cn thit cho mt s thit b hoc
qu trnh i hi s ng b c bit. Trng thi ny c th c to ra dng mt
thit b master trong hp thit b slave khng th p ng trong mt chu k bus.
Phn cng u tin ngt: khi mt hay nhiu thit b slave to ra cc tn hiu
ngt, Avalon bus module s chuyn cc ngt( theo th t u tin) n c thit b
master km theo s yu cu ngt( IRQ number) thch hp.
Kh nng tr hon cc d liu: cc logic cn thc hin vic truyn vi
tr mong mun gia cc cp master-slave c tch hp sn trong Avalon bus
module.

Hnh 2-31: S khi mt Avalon bus module trong thit k
2.6.2. Cc thit b ngoi vi Avalon
Mt thit b ngoi vi Avalon l mt thit b logic, hoc c tch hp sn hoc
nm ri bn ngoi, thc hin mt s chc nng mc h thng v giao tip vi cc
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thnh phn khc trong h thng thng qua Avalon bus. Cc thit b ny c th c
thm vo hoc ly ra khi h thng vo thi im thit k ph hp vi yu cu
ca h thng.
Thit b ngoi vi Avalon c th l cc b nh, vi x l, hay cc thnh phn
thit b ngoi vi truyn thng nh UART, PIO, b nh thi. Bt k logic ngi
dng no cng c th l mt thit b ngoi vi, ch cn cung cp giao tip a ch, d
liu v iu khin cho Avalon bus. Mt thit b ngoi vi s kt ni vi cc cng
ring bit trn Avalon bus module.
Chc nng ca cc thit b ngoi vi Avalon c phn loi thnh master hoc
slave. Mt thit b ngoi vi ch( master) l mt thit b m c th khi to qu trnh
truyn d liu trn Avalon bus. N cn t nht mt cng master ni vi Avalon bus,
v c th c cc cng slave nhn d liu t cc thit b ch khc. Mt thit b
slave l mt thit b ch chp nhn vic truyn d liu t Avalon bus v khng th
khi to qu trnh truyn. Mt s thit b slave in hnh nh b nh hay cng ni
tip s c duy nht mt cng slave ni vi Avalon bus.
Master Port: Mt cng ch l tp hp cc cng trn mt thit b ch m cc
cng ny c s dng khi to cc qu trnh truyn trn Avalon bus. Cng ch
ni trc tip ti Avalon bus module. Trn thc t, mt thit b ngoi vi thng c
mt hoc nhiu cng ch, cng nh cng slave. S ph thuc ln nhau gia cc
cng ny ty vo thit k ca thit b.
Cng slave: Mt cng slave l mt nhm cc cng trn mt thit b ngoi vi
m chp nhn vic truyn d liu qua Avalon bus t mt cng ch.
Cp ch-t( master-slave pair): Mt cp ch-t l s kt hp gia mt cng
slave v mt cng master thng qua Avalon bus module. V mt cu trc, nhng
cng master v slave ny kt ni n cng tng ng trn Avalon bus module v
phi c ch r khi thit k trong SOPC Builder.
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CHNG 3: NI DUNG THC HIN
Chng ny s trnh by ni dung thc hin cng vic ca ti bao gm s
h thng tng qut, chi tit thit k, lu thut ton, s nguyn l v hnh
nh module thc t.
S tng qut h thng 3.1
S tng qut ca h thng nh sau:

Hnh 3-1: S tng qut h thng
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S khi tng qut bao gm nhng thnh phn:
Computer: Dng np chng trnh xung KIT v truyn nhn d liu
iu khin.
NIOS II Processor: Khu x l trung tm ng vai tr truyn nhn v x l d
liu.
JTAG Debug Module: Np chng trnh xung KIT.
Rs232: Kt ni iu khin t my tnh xung KIT thng qua cp ni Rs232.
SRAM on chip: B nh chng trnh.
Avalon Bus: Giao tip gia cc Component trong mt h thng SoPC.
EFAN: Cc tn hiu iu khin hp s ca Qut.
LCD: Cc tn hiu iu khin LCD Character.
LED Controler: iu khin LED.
FAN: Tn hiu kt ni vi Qut.
LCD Character: Hin th trng thi ngoi vi.
Lamp: Tn hiu kt ni vi n.





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Chi tit thit k h thng 3.2
3.2.1. NIOS II Processor nios2_qsys_0
Vi yu cu ca ti, tnh nng ca h thng cn c bn, khng cn nhiu
chc nng nn chn li NIOS II phin bn NIOS II/e nh hnh bn di.

Hnh 3-2: Chn phin bn NIOS II/e
Vi phin bn NIOS II/e ny chng ta c 1 b vi x l 32 bit. Vi Jtag debug
Module l Level 1. Gm cc thnh phn tn hiu c bn sau:
Clk: Clock Input
Reset_n: Reset Input
Data_master: Avalon Memory Mapped Master
Intruction_master: Avalon Memory Mapped Master
Jtag_debug_module_reset: Reset Output
Jtag_debug_module: Avalon Memory Mapped Slave
Custom_intruction_master: Custom Intruction Master



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3.2.2. JTAG Debug Module jtag_uart_0

Hnh 3-3: Component Jtag_uart
Chn mc nh Jtag uart nh trong hnh.
3.2.3. Rs232 UART( Rs232 Serial Port)

Hnh 3-4: Component Rs232
input wire uart_0_rxd, // uart_0.rxd
output wire uart_0_txd, // .txd
Component Uart( uart_0) vi thng s nh sau:
Data bits: 8
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Stop bits: 1
Synchronizer stage: 2
Baud rate: 57600 bps
3.2.4. SRAM On Chip onchip_memory2_0

Hnh 3-5: SRAM On Chip
To ra b nh Ram on Chip vi tng dung lng l 40960 bytes.
3.2.5. EFAN

Hnh 3-6: EFAN
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PIO Efan vi 3 tn hiu chnh l 3 tn hiu iu khin Qut, tng ng vi s 1,
s 2, s 3 ca Qut.
output wire [2:0] efan_export,
3.2.6. LCD
Khi LCD l khi iu khin LCD gm nhng thnh phn sau:
inout wire [7:0] lcd_data, // lcd.data
output wire lcd_E, // .E
output wire lcd_RS, // .RS
output wire lcd_RW, // .RW
Lcd_data pio_3: Gm 8 tn hiu.

Hnh 3-7: Lcd_data
Tm ng ca bus d liu dng trao i thng tin vi MPU. C 2 ch
s dng 8 ng bus ny :
Ch 8 bit : D liu c truyn trn c 8 ng, vi bit MSB l bit DB7.
Ch 4 bit : D liu c truyn trn 4 ng t DB4 ti DB7, bit MSB l
DB7


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Lcd_rw pio_4: Chn chn thanh ghi.

Hnh 3-8: Lcd_rw
Chn chn ch c/ghi( Read/Write). Ni chn R/W vi logic 0 LCD
hot ng ch ghi, hoc ni vi logic 1 LCD ch c.
Lcd_rs pio_5: Chn chn thanh ghi( Register select).

Hnh 3-9: Lcd_rs
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Ni chn RS vi logic 0( GND) hoc logic 1( VCC) chn thanh ghi.
Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR ca LCD( ch
ghi- write) hoc ni vi b m a ch ca LCD( ch c - read)
Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu DR bn trong LCD.
Lcd_e pio_6: Chn cho php( Enable)

Hnh 3-10: Lcd_e
Sau khi cc tn hiu c t ln bus DB0-DB7, cc lnh ch c chp nhn
khi c 1 xung cho php ca chn E.
ch ghi: D liu bus s c LCD chuyn vo( chp nhn) thanh
ghi bn trong n khi pht hin mt xung( high-to-low transition) ca tn
hiu chn E.
ch c: D liu s c LCD xut ra DB0-DB7 khi pht hin cnh
ln( lowto-high transition) chn E v c LCD gi bus n khi no
chn E xung mc thp.


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3.2.7. LED Controler pio_0 led_green

Hnh 3-11: Led control
Led control gm 8 tn hiu iu khin tng ng vi 8 led green c tch hp
trn KIT Altera DE2.
wire [7:0]led_green;
Bng n ngoi vi c iu khin nh vo tn hiu ca led green, t , led
green trn KIT sng th bng n ngoi vi cng sng.
output wire lamp,
assign lamp = ~led_green_export[0];
3.2.8. Avalon Bus
Qu trnh c d liu t cng Slave
Trong sut qu trnh ny chn read_n v chipselect phi c kch hot. Mt
n v d liu s c chuyn t cng slave n Avalon bus module vi kch thc
bng vi rng ti a ca cng slave. Nh vy, trong module giao tip ta phi c
lnh khi Avalon bus thit lp mt qu trnh c t cng slave, thit k ca ta phi
p ng li chnh xc d liu mun truyn ln. C th thc hin vic ny bng cc
lnh sau:
always @(posedge clk) begin
read_cycle <=( !read_n) & chipselect;
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read_data <= data
end
Hnh sau m t cc chn kt ni cn thit gia cng slave t component m ta
thit k vi Avalon bus module.

Hnh 3-12: Giao tip gia cng Slave v Avalon Bus Module trong qu
trnh c t Slave
Qu trnh truyn ny c th gm cc giai on: module Avalon bus nhn a
ch v tn hiu read_n, gii m a ch v to ra tn hiu chipselect, d liu c
cng slave truyn ln. Hnh sau m t chi tit v thi gian trong qu trnh c t
cng slave.

Hnh 3-13: Thi gian trong qu trnh c d liu t cng slave
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Qu trnh m t trn ch l qu trnh c c bn t cc cng slave. Ngoi ra, ta
c th c t cng slave vi nhiu cch( ph thuc vo thit k) nh: c c trng
thi ch, c c thi gian ci t
Qu trnh ghi d liu qua cng Slave
Trong qu trnh ny, tn hiu write_n v chipselect s c kch hot. D liu
s c truyn t Avalon bus module ra cng slave. Trong trng hp cng ny
cha p ng c, th qu trnh truyn phi c trng thi ch. Ta c th n gin
ho thc thi ny bng cc dng lnh sau trong module thit k:
always @(posedge clk) begin
write_cycle <=( !write_n) & chipselect;
data <= write_data;
end
V sau khi module khng p ng kp vi tc truyn d liu t Avalon
bus module ta c th bt tn hiu waitrequest ln. S khi cc tn hiu giao tip
trong qu trnh ghi v thi gian ca qu trnh ny c trnh by trong hnh sau.

Hnh 3-14: Cc tn hiu giao tip v thi gian trong khi ghi d liu ra cng
slave
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Thit k giao din iu khin trn my tnh. 3.3
S dng phn mm Visual Studio 2010 thit k giao din trn my tnh bng
Windows Form Application ca C#. Chng trnh ny c dng kh ph bin, ph
hp thit k giao tip bi giao din thn thin vi ngi dng.
H thng c kt ni vi my tnh thng qua ng Rs232( s dng mch
chuyn USB sang Rs232) vi tc Baud l 57600.
Trn my tnh, c giao din iu khin c vit bng C#, CPU Nios II s
nhn lnh t my tnh iu khin n, qut v hin th thng bo trn LCD ca
kit.
Giao din iu khin c bn gm cc i tng chnh:
2 button dng bt, tt n
3 button tng ng vi 3 ch ca qut v 1 button dng tt qut.
2 button kt ni v ngt kt ni.
1 button thot chng trnh
2 label hin th trng thi ca n v qut.
2 picturebox gip hin th mt cch trc quan cc trng thi.
1 timer hin th trng thi ca qut.
1 SerialPort Com
1 ImageList
3 groupBox
1 ComboBox chn cng kt ni



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Giao din chng trnh:

Hnh 3-15: Giao din chng trnh chnh

Hnh 3-16: Giao din chng trnh iu khin
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Mu xanh hin th trn button cho thy mch ang hot ng chc nng .
V d hnh 3.16 l h thng ang ngt kt ni, n tt, qut tt.
Lu thut ton 3.4
3.4.1. Qu trnh gi

Hnh 3-17: Lu thut ton qu trnh gi d liu
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Chng trnh ca Nios II s c np ln SRAM ON CHIP. Qu trnh hot
ng s c iu khin t trn my tnh bng cch s dng giao din, lnh ny s
c truyn n KIT thng qua ng UART( Rs232 Serial Port)
C th khi button S 1( btnSo1) c nhn, my tnh s gi xung mt k t
1(FAN1)
Tng t khi button S 2( btnSo2) c nhn, my tnh s gi xung mt k
t 2(FAN2).
Khi button S 3( btnSo3) c nhn, my tnh s gi xung mt k t
3(FAN3)
Khi button Tt qut( btnTatQ) c nhn, my tnh s gi xung mt k t
0(FAN_OFF).
Button Bt n( btnBatD) c nhn, my tnh s gi xung mt k t
4(LAMP_ON).
Button Tt n( btnTatD) c nhn, my tnh s gi xung mt k t
5(LAMP_OFF)
3.4.2. Qu trnh nhn
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Hnh 3-18: Lu thut ton qu trnh nhn d liu
Nu nhn c k t 0, efan_off() IOWR(EFAN_BASE, 0, 0x7), khi tt
c cc knh Relay m v qut khng quay.
Nu nhn c k t 1, efan_on(LEVEL1), LEVEL1 = 0x3, knh EN1 ng,
EN2,3 m v qut chy s 1.
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Nu nhn c k t 2, efan_on(LEVEL2), LEVEL2 = 0x5, knh EN2 ng,
knh EN1,3 m v qut chy s 2.
Nu nhn c k t 3, efan_on(LEVEL3), LEVEL3 = 0x6, knh EN3 ng,
EN1,2 m v qut chy s 3.
Nu nhn c k t 4, led_on() IOWR(PIO_0_BASE, 0, 1), knh EN4
ng v n sng.
Nu nhn c k t 5, led_off() IOWR(PIO_0_BASE, 0, 0), knh EN4
m v n tt.
S nguyn l. 3.5
3.5.1. Kt ni chn tn hiu iu khin ngoi vi
ti s dng phng php iu khin Relay 4 knh iu khin cc thit b
ngoi vi. Trong 1 knh iu khin bt tt bng n v ba knh cn li iu
khin 3 mc chy ca qut l s 1, s 2 v s 3.
Kt ni Relay vi KIT thng qua chn m rng ca KIT DE2.

Hnh 3-19: Connect to GPIO1( DE2 KIT)
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Bng 3-1: Chn kt ni tn hiu iu khin GPIO1
Tn tn hiu FPGA Pin M t
efan_export[2] PIN_P24 FAN1
efan_export[1] PIN_R24 FAN2
efan_export[0] PIN_T22 FAN3
lamp PIN_T24 LAMP

3.5.2. S ghp ni Rs232.
KIT Altera DE2 s dng mch chun giao tip Rs232 dng IC Max232.
Max232 l IC chuyn dng cho giao tip gia RS232 v thit b ngoi vi.
Max232 l IC ca hng Maxim. y l IC chay n nh v c s dng ph bin
trong cc mch giao tip chun RS232. Dng tn hiu c thit k cho chun
RS232 . Mi u truyn ra v cng nhn tn hiu u c bo v chng li s
phng tnh in( hnh nh l 15KV). Ngoi ra Max232 cn c thit k vi ngun
+5V cung cp ngun cng sut nh.
Mch giao tip nh sau:

Hnh 3-20: Mch chun giao tip Rs232 dng IC Max232
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Bng 3-2: Rs232 pin assignments
Tn tn hiu PFGA pin M t
Uart_0_txd PIN_B25 UART Transmit
Uart_0_rxd PIN_C25 UART Reciever

3.5.3. S module mn hnh LCD

Hnh 3-21: S module mn hnh LCD

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Bng 3-3: LCD Module pin assignment
Tn tn hiu FPGA pin M t
LCD_DATA[0] PIN_J1 LCD DATA[0]
LCD_DATA[1] PIN_J2 LCD DATA[1]
LCD_DATA[2] PIN_H1 LCD DATA[2]
LCD_DATA[3] PIN_H2 LCD DATA[3]
LCD_DATA[4] PIN_J4 LCD DATA[4]
LCD_DATA[5] PIN_J3 LCD DATA[5]
LCD_DATA[6] PIN_H4 LCD DATA[6]
LCD_DATA[7] PIN_H3 LCD DATA[7]
LCD_RW PIN_K4 LCD Read/Write Select, 0 = Write,
1 = Read
LCD_EN PIN_K3 LCD Enable
LCD_RS PIN_K1 LCD Command/Data Select, 0 =
Command, 1 = Data
LCD_ON PIN_L4 LCD Power ON/OFF
LCD_BLON PIN_K2 LCD Back Light ON/OFF

3.5.4. S nguyn l Relay 4 knh
Module Relay s dng 6 u vo l Vcc, GND nui ngun, 4 u vo ENB
iu khin Module. PC 817 ng vai tr dung cch l gia hai khi in p
chnh lch. Relay ng vai tr l mt kho ng m, dng ng ct nhng ngun
in p lp( 12V-220V/10A).

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Trong Vcc v GND c ni vi 2 chn m rng Vcc, GND ca KIT DE2.
4 u vo EN1,2,3,4 chnh l 4 tn hiu iu khin ngoi vi: 3 tn hiu iu
khin 3 s ca qut v 1 tn hiu iu khin n.

Hnh 3-22: S nguyn l Module Relay 4 knh

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Hnh nh module thc t 3.6
Hnh nh Module Relay 4 knh 5V-220V/10A

Hnh 3-23: Module Relay 4 knh - 5V-220V/10A



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CHNG 4: KT LUN
Chng ny s trnh by kt qu t c ca ti, hn ch v hng pht
trin ca ti trong thi gian ti.
Kt qu t c ca ti 4.1
Sau thi gian nghin cu v thc hin k t khi nhn ti, bng s n lc
ca bn thn, bn cnh nh s hng dn nhit tnh, tn tm ca thy L Trung
Hiu do ti ny c hon thnh ng thi hn v t c yu cu t ra
l thit k h thng nhng trn NIOS v iu khin thit b qua my tnh. Trong qu
trnh thc hin nhm thu c nhng kt qu sau:
Gii thiu v FPGA, ng dng trong rt nhiu cc lnh vc cng ngh, sn
xut, qun s, cc thit b iu khin thng minh v trong nhiu ngnh cng
nghip khc
Nm c tng quan, cu trc ca FPGA v quy trnh thit k FPGA.
Thit k c h thng nhng trn NIOS bng cch xy dng phn cng
cng nh phn mm, c ch gi v nhn tn hiu. iu khin hot ng
ca h thng sao cho ti u v n nh, an ton. H thng c xy dng
hon chnh t nhng khi nh. Giao tip c gia my tnh v thit b iu
khin, xy dng giao din iu khin thnh cng trn Visual Studio.
Qu trnh chy th nghim cho thy tnh n inh, phn mm c xy dng
n gin, d s dng v em li hiu qu hot ng cao.
thc hin c ti ny Em thc hin tm hiu, nghin cu cc vn
c lin quan n ti nh: Cch thit k phn cng v phn mm cho
KIT thng qua Quartus II v tool SoPC( Qsys) trn Quartus II, phn mm lp
trnh nhng NIOS, giao tip gia my tnh v KIT DE2 thng qua UART-
JTAG v RS232. Xy dng h thng vi ngoi vi c sn trn KIT(LCD
Display, LED) v ngoi vi m rng( GIPO). Ngn ng lp trnh Verilog, C.
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Hn ch ca ti 4.2
H thng nhng trn NIOS iu khin thit b ngoi vi l mt ng dng nhng
c bn trn KIT Altera DE2, nn sn phm ch mang tnh DEMO cha c tnh
thng mi, cha c tnh cng ngh cao. Cc ng dng iu khin cn n gin,
cha ng dng nhiu module t ng ha.
Hng pht trin ca ti 4.3
Trong thi gian nghin cu v thc hin ti, tc gi vch ra c hng
pht trin tip theo ca ti nh sau:
Xy dng thm cc Control lm phong ph trn vic ty bin giao
din iu khin.
B sung cc Module t ng ha mang tnh cng ngh cao, c th
ng dng trong vic sn xut c th ng dng trong thng mi.
Nghin cu v trin khai s dng cc ngoi vi khc trn Kit lm
phong ph thm chc nng, cng ngh s dng cao hn cho ti.
iu khin thit b qua mng LAN, INTERNET,
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TI LIU THAM KHO
[1] TS V c Lung, Gio trnh ngn ng m t phn cng Verilog, i hc
bch khoa thnh ph H Ch Minh, 2012.
[2] Altera, DE2_Manual User, altera.com.
[3] Dr. Pong P. Chu, Embedded SoPC Design with Nios II Processor and
Verilog Examples, 2012.
[4] Nguyn Th Hong, Th nghim thit k FPGA, Khoa Cng Ngh in T,
H Cng Nghip TP HCM.

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PH LC
1. M Verilog m t h thng.
module de2_top(
output wire [17:0] led_red_export,
output wire dir_export,
input wire reset_n,
input wire phase_zero,
inout wire [7:0] lcd_data,
wire lcd_E,
output wire lcd_RS,
wire lcd_RW,
output wire lcd_ON,
input wire clk,
output wire pwm_export,
output wire lamp,
output wire [7:0] led_green_export,
inout wire [15:0] sram_DQ,
output wire [17:0] sram_ADDR,
output wire sram_LB_N,
output wire sram_UB_N,
output wire sram_CE_N,
output wire sram_OE_N,
output wire sram_WE_N,
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output wire [2:0] efan_export,
output wire [2:0] efan_export_led,
input wire uart_0_rxd, // uart_0.rxd
output wire uart_0_txd, // .txd
output wire [56:0] led_seg // led_green.export
);
wire [2:0] efan_export_sign;
wire [7:0]led_green;
wire [7:0] phase_export;
assign lcd_ON = 1'b1;
assign led_seg ={57{1'b1}};
reg [31:0]counter=0;
reg [8:0] counter_phase;
reg [8:0] counter_phase_store;
assign led_green_export =( led_green == 1)? 8'hff :( (led_green == 2)?
{8{counter[24]}}:8'h00);
assign lamp = ~led_green_export[0];
assign led_red_export[16] = pwm_export;
assign led_red_export[17] = dir_export;
assign led_red_export[15] = !dir_export;
assign led_red_export[0] = !efan_export_sign[2];
assign led_red_export[1] = !efan_export_sign[1];
assign led_red_export[2] = !efan_export_sign[0];
assign efan_export = efan_export_sign;
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assign efan_export_led = efan_export_sign;
reg phase_zero_L1, phase_zero_L2, phase_zero_L3;

always @( posedge clk)begin
phase_zero_L1 <= phase_zero;
phase_zero_L2 <= phase_zero_L1;
phase_zero_L3 <= phase_zero_L2;
end
always @( posedge clk)begin
counter <= counter + 1;
end
always @( posedge clk)begin
if(phase_zero_L3 == 1'b0 | !reset_n)
counter_phase <= 8'b0;
else
counter_phase <= counter_phase + 1'b1;
end
always @( posedge clk)begin
if(reset_n)
counter_phase_store <= 8'b0;
else if( phase_zero_L2 == 1'b0 & phase_zero_L3 == 1'b1)
counter_phase_store <= counter_phase/100;
end
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assign dir_export = (counter_phase_store * phase_export) >
counter_phase;
soc_qsys U(
.reset_reset_n(reset_n), // reset.reset_n
.clk_clk(clk), // clk.clk
.led_red_export(), // led_red.export
.dir_export(), // dir.export.
/*
.sram_DQ(sram_DQ), // sram.DQ
.sram_ADDR(sram_ADDR), // .ADDR
.sram_LB_N(sram_LB_N), // .LB_N
.sram_UB_N(sram_UB_N), // .UB_N
.sram_CE_N(sram_CE_N), // .CE_N
.sram_OE_N(sram_OE_N), // .OE_N
.sram_WE_N(sram_WE_N), // .WE_N
*/
.phase_export(phase_export),
.efan_export(efan_export_sign),
.uart_0_rxd(uart_0_rxd),
.uart_0_txd(uart_0_txd),
.lcd_data_export(lcd_data), // lcd.data
.lcd_e_export(lcd_E), // .E
.lcd_rs_export(lcd_RS), // .RS
.lcd_rw_export(lcd_RW), // .RW
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.pwm_export(pwm_export), // pwm.export
.led_green_export(led_green) // led_green.export
);
endmodule

2. Th vin ca LCD display
#ifndef _LCD_H_
#define _LCD_H_
#define row1 1
#define row2 2
#define col1 0
#define col2 1
#define col3 2
#define col4 3
#define col5 4
#define col6 5
#define col7 6
#define col8 7
#define col9 8
#define col10 9
#define col11 10
#define col12 11
#define col13 12
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#define col14 13
#define col15 14
#define col16 15

// define for nios II
#define LCD_data PIO_3_BASE
#define RW PIO_4_BASE
#define RS PIO_5_BASE
#define E PIO_6_BASE

#define output_low(base) IOWR(base, 0, 0)
#define output_high(base) IOWR(base, 0, 1)
#define output_b(data) IOWR(LCD_data, 0, data)
#define delay_ms( n ) usleep(1000*n)

#define int8 char
#define int16 short

unsigned char buff[100];
void lcd_init( void );
void LCD_nibble(unsigned int8 n);
void LCD_write(unsigned int8 address, unsigned int8 n);
void lcd_gotoxy( unsigned int8 col, unsigned int8 row );
void lcd_clear( unsigned int8 row );
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void lcd_menu_init( void );
void lcd_puts( unsigned int8 *string );
void lcd_putc( unsigned int8 c );
void lcd_display_string( unsigned int8 *string, unsigned int16 lenght, int16
col, int16 row );
//unsigned int8 lcd_display_page( unsigned int8 *str, unsigned int16 len, INT8
cursor );
//unsigned int8 menu_main( void );
//unsigned int8 first_main( void );
#endif

3. M chng trnh iu khin LCD Display
#include "lcd.h"
#include <string.h>
#include <unistd.h>
#include <io.h>
#include "system.h"
void lcd_init( void )
{
unsigned int8 i;
output_low(RS); // RS = 0 : address, RS = 1 : data
output_low(E); // E = 0 : disable
output_low(RW); // RW = 0 : write
//LCD_nibble(0x00); // 0x0E : screen and cursor is display on
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LCD_nibble(0x38);
delay_ms( 10 );
LCD_nibble(0x308);
delay_ms( 1 );
LCD_nibble(0x38);
delay_ms( 1 );
//LCD_nibble(0x00); // 0x0E : screen and cursor is display on
LCD_nibble(0x0C);
delay_ms( 10 );
//LCD_nibble(0x00); // 0x01 : Clear display
LCD_nibble(0x1);
delay_ms( 10 );
//LCD_nibble(0x0); // 0x06 : increased display and no shift
LCD_nibble(0x06);
delay_ms( 10 );
LCD_nibble(0x80); // 0x80 : cursor home
//LCD_nibble(0x0);
delay_ms( 10 );
}
void lcd_clear( unsigned int8 row )
{
switch( row )
{
case row1:
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lcd_gotoxy( col1, row1 );
memset( buff, 0, sizeof buff );
strcpy( buff, " " );
lcd_puts( buff );
lcd_gotoxy( col1, row1 );
break;
case row2:
lcd_gotoxy( col1, row2 );
memset( buff, 0, sizeof buff );
strcpy( buff, " " );
lcd_puts( buff );
lcd_gotoxy( col1, row2 );
break;
default:
LCD_write( 0, 0x01 );
lcd_gotoxy( col1, row1 );
break;
}
}
void LCD_nibble( unsigned int8 n )
{
output_b( n );
//delay_ms( 1 );
output_high( E );
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usleep( 1 );
output_low( E );
delay_ms( 1 );
}
void LCD_write( unsigned int8 style, unsigned int8 n )
{
//set_tris_b(0x00);
//set_tris_a(0x20);
delay_ms( 1 );
//delay_cycles( 100 ); // At 20 mhz a 5us delay
usleep(100);
if( style == 1 ) output_high( RS );
else output_low( RS );
output_low(E);
LCD_nibble(n);
output_low( RS );
output_low(E);
}
void lcd_gotoxy( unsigned int8 col, unsigned int8 row )
{
unsigned int8 address = 0;
if( row == 1 )
address = 0x80;
else
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address = 0xC0;
address += col;
LCD_write( 0, address );
}
void lcd_putc( unsigned int8 c )
{
switch( c )
{
case '\f' : LCD_write( 0,1 ); //0x0C
delay_ms( 2 );
break;
case '\n' : lcd_gotoxy( col1, row2 ); break; //0x0A
case '\b' : LCD_write( 0, 0x10 ); break; //0x08
default : LCD_write( 1, c ); break;
}
}
void lcd_puts( unsigned int8 *string )
{
//dung dong while thi fai co \n de xuong hang duoi
while( *string )
{
lcd_putc( *string );
string++;
}
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}
void lcd_display_string( unsigned int8 *string, unsigned int16 lenght, int16
col, int16 row )
{
//dung dong while thi fai co \n de xuong hang duoi
unsigned int16 len = 0;
while( *string )
{
if( col > col16 )
{
col = col1;
if( row == row1 ) row = row2;
else break;
}
lcd_gotoxy( col, row );
lcd_putc( *string );
string++;
col++;
len++;
if( len > lenght ) break;
}
}
void lcd_menu_init( void )
{
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unsigned int8 i = 2;
memset( buff, 0, sizeof buff );
strcpy( buff, " ALTERA DE2 KIT \nNice To See You " );
while( i > 0 )
{
lcd_gotoxy( col1, row1 );
lcd_puts( buff );
// while( 1);
delay_ms( 1000 );
lcd_clear( 0 );
delay_ms( 300 );
i--;
}
lcd_puts( buff );
delay_ms( 100 );
}
4. M chng trnh iu khin h thng.
#include "sys/alt_stdio.h"
#include "system.h"
#include <stdio.h>
#include <stddef.h>
#include <stdlib.h>
#include <unistd.h>
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#include <string.h>
#include <io.h>
#include "lcd.h"
#define output(base,data) IOWR(base, 0, data)
#define set_duty(data) IOWR(PWM_0_BASE, 0, data)
#define set_cycle(data) IOWR(PWM_0_BASE, 1, data)
#define pwm_on() IOWR(PWM_0_BASE, 2, 0)
#define pwm_off() IOWR(PWM_0_BASE, 2, 1)
#define led_off() IOWR(PIO_0_BASE, 0, 0)
#define led_on() IOWR(PIO_0_BASE, 0, 1)
#define led_blink() IOWR(PIO_0_BASE, 0, 2)
#define LEVEL1 0x3
#define LEVEL2 0x5
#define LEVEL3 0x6
#define efan_off() IOWR(EFAN_BASE, 0, 0x7)
#define efan_on(data) IOWR(EFAN_BASE, 0, data)
#define set_dir(data) IOWR(PIO_2_BASE, 0, data)
#define _CYCLE 1000
#define _DUTY 500
int main()
{
unsigned int task=0;
char i =0;
set_duty(_DUTY);
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set_cycle(_CYCLE);
pwm_on();
set_dir(0);
//printf("PWM_0_BASE: %d\n\r",IORD(PWM_0_BASE,0));
//printf("PWM_0_BASE: %d\n\r",IORD(PWM_0_BASE,1));
//printf("PWM_0_BASE: %x\n\r",IORD(PWM_0_BASE,2));
led_off();
pwm_off();
lcd_init();
lcd_menu_init();
delay_ms(1000);
lcd_clear( 1 );
lcd_clear( 2 );
lcd_gotoxy(0,1);
lcd_puts("Quat: Dang tat");
lcd_gotoxy(0,2);
lcd_puts("Den : Dang tat");
while(1){
printf("\nSelect task below: \n");
printf(" + Press 0 : Tat quat\n\r");
printf(" + Press 1 : Quat quay phai cham\n\r");
printf(" + Press 2 : Quat quay phai vua\n\r");
printf(" + Press 3 : Quat quay phai nhanh\n\r");
printf(" + Press 4 : Led sang\n\r");
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printf(" + Press 5 : Led tat\n\r");
printf(" + Press 6 : Led nhap nhay\n\r");
task = alt_getchar();
//scanf("%d",&task);
printf("\ntask = %c \n\r",task);
task = task - 0x30;
alt_getchar();// get enter key
switch(task)
{
case 0:
pwm_off();
set_dir(0);
efan_off();
alt_printf("Tat Quat\n\r");
lcd_clear( 1 );
lcd_gotoxy(0,1);
lcd_puts("Quat: Dang tat");
break;
case 1:
set_duty(300);
pwm_on();
efan_on(LEVEL1);
set_dir(0);
lcd_clear( 1 );
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lcd_gotoxy(0,1);
lcd_puts("Quat: So 1");
alt_printf("Quat quay phai cham\n\r");
break;
case 2:
set_duty(600);
efan_on(LEVEL2);
pwm_on();
set_dir(0);
lcd_clear( 1 );
lcd_gotoxy(0,1);
lcd_puts("Quat: So 2");
alt_printf("Quat Phai Vua");
break;
case 3:
set_duty(1000);
pwm_on();
efan_on(LEVEL3);
set_dir(0);
lcd_clear( 1 );
lcd_gotoxy(0,1);
lcd_puts("Quat: So 3");
alt_printf("Quat Phai Nhanh");
break;
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case 4:
led_on();
lcd_clear( 2 );
lcd_gotoxy(0,2);
lcd_puts("Den : Dang bat");
alt_printf("Led Xanh Sang");
break;
case 5:
led_off();
lcd_clear( 2 );
lcd_gotoxy(0,2);
lcd_puts("Den : Dang tat");
alt_printf("Led Xanh Tat");
break;
}
}
while(1)
{
output(PIO_0_BASE, 0xff); //led sang
delay_ms(1000); // de lay giua cac lan sang tat
output(PIO_0_BASE, 0x00); // led tat
delay_ms(1000);
}
return 0;
}