Desc r ipc io n d e maq uinas d e est ad o

en vh d l
Una mquina de estados est definida por dos funciones; una que calcula el
estado siguiente en el que se encontrar la mquina y la otra que calcula la
salida.
Mquina de Mealy: la salida depende de las entradas y del estado presente
Maquina de Moore: la salida depnde slo del estado presente.
En VHDL se pueden describir tanto mquinas de Mealy como mquinas de
Moore. Las mquinas de estado se modelan con una parte secuencial y otra
combinacional.
Una mquina de estados en VHDL tiene:
Una lgica que permite pasar de estado.
Una lgica de salida
una memoria
Output
Combinational
Logic
M
e
m
o
r
y
Present
State
Next
State
Primary
Inputs
Primary
Outputs
Mealy Machine Model
Next State
Combinational
Logic
Output
Combinational
Logic
M
e
m
o
r
y
Present
State
Next
State
Primary
Inputs
Moore Machine Model
Next State
Combinational
Logic
Primary
Outputs
Co d if ic ac io n d e est ad o s
Se utiliza el tipo enumerado para codificar los estados
posibles:
TYPE state_type IS (idle,init,test,add,shift);
SIGNAL present_state, next_state : state_type;
Co d if ic ac io n d e l a t r ansic io n d e
est ad o s (MEMORIA)
Signal estado: state_type;
PROCESS(reloj, entradas_asncronas)
BEGIN
IF entradas_asincronas THEN
estado <= estado_inicial;
ELSIF clkevent AND clk = 1 THEN
CASE estado IS
WHEN estado1 =>
Calculo_estado_en _funcin de entradas
WHEN estado2 =>
Calculo_estado_en _funcin de entradas
WHEN estado3 =>
Calculo_estado_en _funcin de entradas
. . .
WHEN estadon =>
Calculo_estado_en _funcin de entradas
END CASE;
END IF;
END PROCESS;
Ejemplo:
clocked : PROCESS(clk, reset)
BEGIN
IF (reset = '0') THEN
present_state <= idle;
ELSIF (clk'EVENT AND clk = '1') THEN
present_state <= next_state;
END IF;
END PROCESS clocked;
nextstate : PROCESS(present_state,start,q0)
BEGIN
CASE present_state IS
WHEN idle =>
IF(start='1') THEN
next_state <= init;
ELSE
next_state <= idle;
END IF;
WHEN init =>
next_state <= test;
WHEN test =>
IF(q0='1') THEN
next_state <= add;
ELSIF(q0='0') THEN
next_state <= shift;
ELSE
next_state <= test;
END IF;
WHEN add =>
next_state <= shift;
WHEN shift =>
next_state <= test;
END CASE;
END PROCESS nextstate;
Co d if ic ac io n d e l a sal id a
El proceso de salida obtiene las salidas basandose en el estado
presente y en las entradas (mquina de Mealy) o slo en el estado
presente (mquina de Moore)
Mealy:PROCESS(estado, entradas)
BEGIN
CASE estado IS
WHEN estado1 =>
Clculo_de_salidas_en_funcin_del_estado;
WHEN estado2 =>
Clculo_de_salidas_en_funcin_del_estado;
WHEN estado3 =>
Clculo_de_salidas_en_funcin_del_estado;
.....
WHEN estadon =>
Clculo_de_salidas_en_funcin_del_estado;
END CASE;
END PROCESS;
Moore:PROCESS(estado)
BEGIN
CASE estado IS
WHEN estado1 =>
Salidas <= valor;
WHEN estado2 =>
Salidas <= valor;
WHEN estado3 =>
Salidas <= valor;
.....
WHEN estadon =>
Salidas <= valor;
END CASE;
END PROCESS;
Ejemplo:
output : PROCESS(present_state,start,q0)
BEGIN
-- Default Assignment
a_enable <= '0' after delay;
a_mode <= '0' after delay;
c_enable <= '0' after delay;
m_enable <= '0' after delay;
-- State Actions
CASE present_state IS
WHEN init =>
a_enable <= '1' after delay;
c_enable <= '1' after delay;
m_enable <= '1' after delay;
WHEN add =>
a_enable <= '1' after delay;
c_enable <= '1' after delay;
m_enable <= '1' after delay;
WHEN shift =>
a_enable <= '1' after delay;
a_mode <= '1' after delay;
m_enable <= '1' after delay;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output;
La mquina completa es:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY control_unit IS
PORT(clk : IN std_logic;
q0 : IN std_logic;
reset : IN std_logic;
start : IN std_logic;
a_enable : OUT std_logic;
a_mode : OUT std_logic;
c_enable : OUT std_logic;
m_enable : OUT std_logic);
END control_unit;
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY control_unit IS
PORT(clk : IN std_logic;
q0 : IN std_logic;
reset : IN std_logic;
start : IN std_logic;
a_enable : OUT std_logic;
a_mode : OUT std_logic;
c_enable : OUT std_logic;
m_enable : OUT std_logic);
END control_unit;
ARCHITECTURE fsm OF control_unit IS
CONSTANT delay : time := 5 ns ;
TYPE state_type IS ( idle, init, test, add, shift);
SIGNAL present_state, next_state : state_type ;
BEGIN
clocked : PROCESS(clk, reset)
BEGIN
IF (reset = '0') THEN
present_state <= idle;
ELSIF (clk'EVENT AND clk = '1') THEN
present_state <= next_state;
END IF;
END PROCESS clocked;
ARCHITECTURE fsm OF control_unit IS
CONSTANT delay : time := 5 ns ;
TYPE state_type IS ( idle, init, test, add, shift);
SIGNAL present_state, next_state : state_type ;
BEGIN
clocked : PROCESS(clk, reset)
BEGIN
IF (reset = '0') THEN
present_state <= idle;
ELSIF (clk'EVENT AND clk = '1') THEN
present_state <= next_state;
END IF;
END PROCESS clocked;
nextstate :
PROCESS(present_state,start,q0)
BEGIN
CASE present_state IS
WHEN idle =>
IF(start='1') THEN
next_state <= init;
ELSE
next_state <= idle;
END IF;
WHEN init =>
next_state <= test;
WHEN test =>
IF(q0='1') THEN
next_state <= add;
ELSIF(q0='0') THEN
next_state <= shift;
ELSE
next_state <= test;
END IF;
WHEN add =>
next_state <= shift;
WHEN shift =>
next_state <= test;
END CASE;
END PROCESS nextstate;
nextstate :
PROCESS(present_state,start,q0)
BEGIN
CASE present_state IS
WHEN idle =>
IF(start='1') THEN
next_state <= init;
ELSE
next_state <= idle;
END IF;
WHEN init =>
next_state <= test;
WHEN test =>
IF(q0='1') THEN
next_state <= add;
ELSIF(q0='0') THEN
next_state <= shift;
ELSE
next_state <= test;
END IF;
WHEN add =>
next_state <= shift;
WHEN shift =>
next_state <= test;
END CASE;
END PROCESS nextstate;
output : PROCESS(present_state,start,q0)
BEGIN
-- Default Assignment
a_enable <= '0' after delay;
a_mode <= '0' after delay;
c_enable <= '0' after delay;
m_enable <= '0' after delay;
-- State Actions
CASE present_state IS
WHEN init =>
a_enable <= '1' after delay;
c_enable <= '1' after delay;
m_enable <= '1' after delay;
WHEN add =>
a_enable <= '1' after delay;
c_enable <= '1' after delay;
m_enable <= '1' after delay;
WHEN shift =>
a_enable <= '1' after delay;
a_mode <= '1' after delay;
m_enable <= '1' after delay;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output;
END fsm;
output : PROCESS(present_state,start,q0)
BEGIN
-- Default Assignment
a_enable <= '0' after delay;
a_mode <= '0' after delay;
c_enable <= '0' after delay;
m_enable <= '0' after delay;
-- State Actions
CASE present_state IS
WHEN init =>
a_enable <= '1' after delay;
c_enable <= '1' after delay;
m_enable <= '1' after delay;
WHEN add =>
a_enable <= '1' after delay;
c_enable <= '1' after delay;
m_enable <= '1' after delay;
WHEN shift =>
a_enable <= '1' after delay;
a_mode <= '1' after delay;
m_enable <= '1' after delay;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output;
END fsm;
Ejemplo de una mquina de Moore
entity MOORE is -- Moore machine
port(X, CLOCK: in BIT;
Z: out BIT);
end MOORE;
architecture BEHAVIOR of MOORE is
type STATE_TYPE is (S0, S1, S2, S3);
signal CURRENT_STATE, NEXT_STATE:
STATE_TYPE;
begin
-- Process to hold synchronous elements (flip-flops)
SYNCH: process
begin
wait until CLOCKevent and CLOCK = 1;
CURRENT_STATE <= NEXT_STATE;
end process SYNCH;
-- Process to hold combinational
logic
COMBIN:
process(CURRENT_STATE, X)
begin
case CURRENT_STATE is
when S0 =>
Z <= 0;
if X = 0 then
NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
when S1 =>
Z <= 1;
if X = 0 then
NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
when S2 =>
Z <= 1;
if X = 0 then
NEXT_STATE <= S2;
else
NEXT_STATE <= S3;
end if;
when S3 =>
Z <= 0;
if X = 0 then
NEXT_STATE <= S3;
else
NEXT_STATE <= S1;
end if;
end case;
end process COMBIN;
end BEHAVIOR;
Mquina de Mealy
entity MEALY is -- Mealy machine
port(X, CLOCK: in BIT;
Z: out BIT);
end MEALY;
architecture BEHAVIOR of MEALY is
type STATE_TYPE is (S0, S1, S2, S3);
signal CURRENT_STATE,
NEXT_STATE: STATE_TYPE;
begin
-- Process to hold combinational logic.
COMBIN: process(CURRENT_STATE,
X)
begin
case CURRENT_STATE is
when S0 =>
if X = 0 then
Z <= 0;
NEXT_STATE <= S0;
else
Z <= 1;
NEXT_STATE <= S2;
end if;
when S1 =>
if X = 0 then
Z <= 0;
NEXT_STATE <= S0;
else
Z <= 0;
NEXT_STATE <= S2;
end if;
when S2 =>
if X = 0 then
Z <= 1;
NEXT_STATE <= S2;
else
Z <= 0;
NEXT_STATE <= S3;
end if;
when S3 =>
if X = 0 then
Z <= 0;
NEXT_STATE <= S3;
else
Z <= 1;
NEXT_STATE <= S1;
end if;
end case;
end process COMBIN;
-- Process to hold synchronous elements (flip-flops)
SYNCH: process
begin
wait until CLOCKevent and CLOCK = 1;
CURRENT_STATE <= NEXT_STATE;
end process SYNCH;
end BEHAVIOR;