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PROJECT1:AND GATE
----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:46:50 01/20/2014
-- Module Name: andgate- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andgate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end andgate;
architecture Behavioral of andgate is
begin
process (A,B)
begin
C<=A and B;
end process;
end Behavioral;

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PROJECT2:NAND GATE
----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:47:58 01/20/2014
-- Module Name: nandgate- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nandgate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
End nandgate;
architecture Behavioral of nandgate is
begin
process (A,B)
begin
C<=A nand B;
end process;
end Behavioral;
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PROJECT3:OR GATE
----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:48:30 01/20/2014
-- Module Name: orgate- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity orgate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
End orgate ;
architecture Behavioral of orgate is
begin
process (A,B)
begin
C<=A or B;
end process;
end Behavioral;
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PROJECT4:NOR GATE
----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:50:01 01/20/2014
-- Module Name: norgate- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity norgate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
End norgate;
architecture Behavioral of norgate is
begin
process (A,B)
begin
C<=A nor B;
end process;
end Behavioral;

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PROJECT5:XOR GATE
----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:52:48 01/20/2014
-- Module Name: xorgate- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xorgate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end xorgate;
architecture Behavioral of xorgate is
begin
process (A,B)
begin
C<=A xor B;
end process;
end Behavioral;
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PROJECT6:XNOR GATE
----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:52:22 01/20/2014
-- Module Name: xnorgate- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xnorgate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end xnorgate;
architecture Behavioral of xnorgate is
begin
process (A,B)
begin
C<=A xnor B;
end process;
end Behavioral;
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PROJECT7: You go home every Sunday or holiday but if there is no exam.

----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:58:01 01/20/2014
-- Module Name: project7 - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity project7 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Y : out STD_LOGIC);
end project7;
architecture Behavioral of project7 is
begin
process (A,B,C)
begin
Y<=A or (B and(not C));
end process;
end Behavioral;
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Project 8: Half Adder

----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:57:01 01/20/2014
-- Module Name: halfadder- Behavioral
--------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
process(A,B)
begin
S<=(A xor B);
C<=(A and B);
end process;
end Behavioral;
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Project 8: Full Adder

----------------------------------------------------------------------------------- Company: DBCET
-- Engineer: Santanu Nath
-- ID:DC2011BTE0059
-- Create Date: 21:59:01 01/20/2014
-- Module Name: fulladder- Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fullader is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end fullader;
architecture Behavioral of fullader is
begin
process(A,B,Cin)
begin
S<=A xor B xor Cin;
C<=(A and B) or (B and Cin) or (a and Cin);
end process;
end Behavioral;
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