Aiwa 4zg-1 1a 1b 1z 09-965-128-10t

awa a 4ZG-1 4ZG-1A 4ZG-1B 4ZG-1Z Sees ngy BASIC NAME DERIVATION NAME 7 -. | wa 4zG-1 z2|s6l|ojr |ral- |valw[vw 4ZG-1A G do | - -|- el ele 426-15 e{o[-|-[-[-]|[-|[- 426-12 of-|— ~ = (@*1,'2, have the same BASIC NAME but the board structures are different. ‘The CD BLOCK,VCD BLOCK of the WR are shown on the SERVICE MANUAL of each DERIVATION NAME . SERVICE MANUAL ‘@This mechanism has various derivation. Derivation name is indicated by the Service Manual for eath model. (@For different version of mechanism that may be introduced since the issue of this manual, only the new or modified points be discussed.- TABLE OF CONTENTS PROTECTION OF EYES FROM LASER BEAM DURING SERVICING 3 SUFFIX NOTE 4 How to Adjust Rotting Phase ofthe Gear, Main Gam 6 ‘TRANSISTOR ILLUSTRATION. 5 4ZG-1 ELECTRICAL MAIN PARTS LIST ——s a 6-9 IC BLOCK DIAGRAM : 10 BLOCK DIAGRAW-1 (VSL: MAIN VCD / CO MECHA) tha BLOCK DIAGRAM-2 (VL: VCD) .. : 13,14 BLOGK DIAGRAM (Val: MAIN VED CD MEGHA) _ 15,16 BLOCK DIAGRAM-4 (VAL: VCD) . 17,18 BLOCK DIAGRAMS (VS) : : — 19,20 WIRING-1 (VOL: MAIN VCD / CD MECHA) swsnsnsnsnsnnannnnnsinnssnnnninsnnn cnn an,22 ‘SCHEMATIC DIAGRAM-1 (Vat: CD MECHA), son 88, 24 [SCHEMATIC DIAGRAM2 (V3L: MAIN VCD) wc. : 25,26 ‘SCHEMATIC DIAGRAM (Val: VCD) soe 27, 28 WIRING-2 (Val: CO) 29,30 WAVE FORM : 3 WIRING-S (WR). 2 SCHEMATIC DIAGRAMS (WR} 82 WIRING-4 (Val: MAIN VCD / CD MECHA). 3,98 ‘SCHEMATIC DIAGRAMS (Val: CD MECHA) 35,36 ‘SCHEMATIC DIAGRAM (VaL: MAIN VCD) .. 97,38 ‘SCHEMATIC DIAGRAM (val: VCD 1/2) 38, 40 SCHEMATIC DIAGRAM. (VAL: VCD 2/2) 41,42 WAVE FORM + WIRING-5 (Vat: VCD), 43-45 WIRING. (V5: MAIN VOD) 2. 48~48 ‘SCHEMATIC DIAGRAM (V5: MAIN VCD 172). 49,50 ‘SCHEMATIC DIAGRAM-10 (VS: MAIN VCD 2/2) 51,52 WAVE FORM 53, 54 ‘SCHEMATIC DIAGRAM: (V5: GD MECHA) 55, 56 \WIRING.7 (Vs: CD MECHA). S 57 IC DESCRIPTION : ‘5800 TEST MODE : . ot ELECTRICAL ADJUSTMENT... 2-04 MECHANICAL EXPLODED VIEW 171 95, MECHANICAL PARTS LIST 1/1 96 (CD MECHANISM EXPLODED VIEW, LIST 1/1 (626-2 CSN ) ae 97 (GD MECHANISM EXPLODED VIEW, LIST 1 / 1 (526-2 GIN ) 98 AIGA ELECTRICAL MAIN PARTS LIST 99, 100 BLOCK DIAGRAM ve vunnnnninnnninninnnnnnnnannnnne AOY 12 WIRING... ei = 108, 104 ‘SCHEMATIC DIAGRAM . 105, 108 WAVE FORM 107 IC BLOCK DIAGRAM eee eee ee : 107 IC DESCRIPTION... 108, 108 TEST MODE 110 ELECTRICAL ADJUSTMENT . 7 Vas (CD MECHANISM EXPLODED VIEW, LIST 1/1 (KSM-21S1BAM ELECTRICAL MAIN PARTS LIST 115,116 BLOCK DIAGRAM a : 117,118 WIRING ' ee ———s tess 118, 120 SCHEMATIC DIAGRAM nn ee cvs W122 WAVE FORM sessnsnnsnnrn vo 123 IC BLOCK DIAGRAM. 123 IC DESCRIPTION 24128 TEST MODE on os 129 ELECTRICAL ADIUSTMENT.. 1180, 131 4ZG-1 ELECTRICAL MAIN PARTS LIST... 192, 133 BLOCK DIAGRAM : : Sea WAVE FORM sen 196 IC BLOCK DIAGRAM, 136 SCHEMATIC DIAGRAM 17, 138, WIRING... : : : : 139, 140 IC DESCRIPTION . nnn ssnnnnnnnnnnnnnnnnnnnnnsn TNS: TEST MODE ... . oe ene 148 ELECTAICAL ADJUSTMENT. 147, 148 CDMEGHANISM EXPLODED VW LIST 1/1 (262 GaN <>) = 149 USE MODEL UST. vn 460 REFERENCE NAME LIST : cee : 181PROTECTION OF EYES FROM LASER BEAM DURING SERVICING ‘Tris set employs laser. Therefore, be sure to folow caretuly the Instructions below when senicing, WARNING! WHEN SERVICING, 00 NOT APPROACH THE LASER EXIT WITH THE EVE TOO CLOSELY. IN CASE IT IS NECESSARY ‘TO CONFIRM LASER BEAM EMISSION. BE SURE TO (OBSERVE FROM A DISTANCE OF MORE THAN socm FROM ‘THE SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL PICK-UP BLOCK. 1 Caution: Invisible laser radiation when open and interlocks defeated avoid expo-sure to eam, 1m Advarsel: Usynilglaserstding ved abning, nr sikkerhedsaforydore or ude af funkton Und udsettlee for sting vaRortus! Latgen Kaytaminen muula kuin tassa kayttOohjeessa mainte tavala saattan alistaa Kayt tan turvalisuusluokan 1 yt valle nkymattémale lasersatelyle, VARNING! (Om apparaten envands pa annat sat n vad som specificeras denna bruksanvsing kan anvandaren utsatas for osyning laserstrlring, som Gverskridergransenf6rlasarklass 1 ‘CAUTION Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure. ATTENTION LLutlisaton de commande, réglages ou procédures autres que ‘ceux spécifiés peut entrainer une dangereuse exposition aux radiations, ADVARSEL! Usynliglaserstling ved abring, nd sikkerhedsatbrydereer ude af funkton. Undga udsattlse for etréing ‘This Compact Dise player is classified as a CLASS 1 LASER product ‘The CLASS 1 LASER PRODUCT label i located on the rear exter. LASER PRODUCT LASER PRODUKT LASER LATTE: LASER APPARATThis is the SERVICE MANUAL for the BASIC CD.MECHANISM of BASIC NAME: 4ZG- 1. This BASIC NAME includes the following models as shown under the SUFFIX name: DERIVATION NAME. Please use this manual with the separate SERVICE MANUAL for DERIVATION NAME. BASIC CD MECHANISM: | 4ZG-1 AGD. ‘SUFFIX (DERIVATION NAME) BASIC NAME: 4ZG-1 (ORIGINAL MODEL) 4ZG-1A (SONY IC MODEL) 4ZG-1B (TOSHIBA IC MODEL) 42G-1Z (SANYO IC MODEL) [BASIC NAME ‘DERIVATION NAME | a[-[-[-[-][[-|[-|- oe 2 G6 D F R — | vst | vat | vs [aza-ta @ De a ee le | 426-18 G D — = — - — = were SSS SS NOTE: + "1 and2 have the same BASIC NAME bit the boaré suture ate aeon. "The BLOCK, VED BLOCK othe WA fs shown on the SERVICE MANUAL ofeach DERIVATION awe + Model 426-1 A, Band Zhas ‘Fas the standard stalation BOARD NaN WOTOR WAIN VEO] CD MECHA] DAIVE sevea| tepce| t-1¢8 veoes asic naw ce | cs | ce cs wae “| -|-fof[-[-][-—-1f-]|o ” O O O 0 426-1 2 = oO oO - o °° events) - azG-tA ° ° ° fe) - _ - _ 4ZG-1B ° Oo ° oO - - - _ 4ZG-1Z O° oO oO _ = al a ° DERIVATION NAME G: Supporting the CD graphic feature D: Digital output function F: CD WINDOW Flash function (LED: AMBER/GREEN) R: Round Tray WR: With out Video CD and CD graphic board, VSL: Supporting the video CD function PAL VAL: Supporting the video CD function PAL V5: Supporting the video CD functionHow to Adjust the Rotating Phase of the Gear, Main Cam 1) Push down the hooking catch of the CHAS. MECH, and remove the TRAY. 2) Align the arow mark of the Gear, Main Cam with the black ‘ound mark of the CHAS, MECHA as shown below. 3) Confirm thatthe Slide, Mech Cam is located in the right position, then inser the TRAY gently. Caution: IFthe rotating phase of the Gear, Main Cam is incorrectly adjusted, the chucking operation and tray ‘movement will have malfunction. GEAR, TRAY RELAY NK2 GEAR, TRAY TRANSISTOR ILLUSTRATION i EcB 28A933 G Be £2 Bt BCE os 2802005 I ECB 2SA1296 2SA1318 28C1815 2802001 280655 2802172 HN1C03, GEAR, WAIN CAH SLIDE, MECHA CAN é 2SA1037 2SA1162 2SA1362 2SA1576 2sc2712 28C3326 2804081 2801383 ‘Align the arrow D mark with the black round ® mar, DTA123JK DTA144TK DTC114TK DTC123JK DTC124xk DTC143TK RN14414ZG-1 ELECTRICAL MAIN PARTS LIST DESCRIPTION Tilif © 2 GUHE “REFERENCE NAMELIST ©SMLT CHEN, If can't understand for Description please kindly refer to “REFERENCE NAME LIST™. No, PATIO. a) ESCRPTIN FER.NO. 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No, coca 3 c-cie, oi ccae,s 0.1025 P econ CocotucaTe euesze con, ¢0H FuCs2e (econ um Fuesze cou, 160 cot, atu Fucsze com, 3.208 com, 2-70H (econ, um rucsze come eeu noroe,_#e-50093 ‘4, 2oss goes 61 SK, 20SH S28 1 Sst 1-1-3 5ssu ‘ib, ea, abet 1008 ip,xtab 13.592 Sapa vistay 16.33¢0ar. 10p-so cheemceet 5s 12P-50 Chet 0.0828 Pee 3500850 bezxcaen vse 6.01-25 pezicart vi> geese 6.056-25045> 0103-25 Petxcern vis 0.0se.28¢¥5> 0.0135 & 0101-25 Bevs> 22008-50 BesxcueT ¥5> isle 1008-50 cH s 0.022-25 aesncern v5 oro5e25e¥5= gees eeees & 1090-50 cH outsasF ovoicas's 0.1.25 Peencaen vss 0:22°16 Pave zine-so's Or 1-25 Pebaoaer v5> O2asie reve 33 38898 eaebe a8888 gpece 5 BEXCEPT VS 6.30 ey go79 a8 258 3-25 Fave e fe i te ” fre rroan0-e05-088 ‘7-000-176-109 7-010-205-088 asmpr-ctt-i3 97-045-256-019 045-388-013 7-022-368-008 7-000-363-089 7-002-363-0089 97-002-363-099 7-002-363-089 s7-022-364-099 7-024-175-0889 e7-024-176-099 o7-020-175-009 87-0960340-018 cor a7-019-216-098 Feud B4-zal-e1e-19 wal 6-b4s 968-018 BoHO1 g7-096-573-015 ap c.3er> apion 67-070-200-028 teD102 87-017-350-080 teD103 #7-017-980-020 epiod 87-00-200-088 veo c.Bevate 2 wr-no-s7e-010 3 groioca7e-01b ee atcono-dne-ti0 cS erooarete © aroto-s7e-ti0 co ar-o1o-s78-03 cit ar-010-378-010 ez s7-010-378-019 fs ar-oi03n cry groin cz sr-oso-sne-es arora cae e700 ced 7-10-24 cs ersoaoan cee er-0x0-a4 ero 7-o10-37 EL Si-AL0-aah-100 ta Suoauo-am-a7e al SscHva-05N-000 x2 ss-xya-wto-000 3 seavicass-si6 en c.Bevit> 1s 67-010-367-080 33 er-o10-aT5-040 eo er-o1a-su3-030 ci e7-010-549-010 ca} g7-010-543-010 chs a7-o10-s49-010 es er-o10-st9-010 Cs4 gr-o10-s48-010 css er-0i0-076-810 £58 eT-O10-076-810 cal s7-016-155-010 e128 0548-010, e113 §7-020-053-810 2150 €7-010-075.040 ——DESCRETION CaP S 0.01-25 B cvcae,s Iter Cone, S 10002-50 B LER S TANGPARECEET V5 Fe-chBe 268-1.0 or nP-3108 A 30 yor ar 3108 A 33 (CoRES,S825-1/ 100 ones, = 6oK-1/100 (CRESS 68K/L0W cos, s 68K-1/104 F nS 654-/ 10M (CS, 5829-1) 100 Srncie DTV SFR, 100K DIRE ¥ sa,e7e IV Siear 15-1121 car rev 0.1450 F (aoue Fre 5é-1.25, oroe, (boxset) StS, GP1S53¥ 180, sueesec-ai-s-rher> ab, seuissoouer> ao) seLLssoquer> ab, SLeesae~s1-e-n1ep> oo!e 10-16 cane 0 oe 210 CAME 1016 cap.e 10-16 cae. 10-16 cae. 0-10 cate 10-16 Ca,E 720-10 cape 47-29 cae.8 220-10 (caP,8 10-16 orb, 1008 com, 4-70 wi AD. a, ame "AL deeS26Li2 2-25¢(s808C1) sasvisaeeet! 6. 3u\serEcb) §3y(sacecd) 5, 3U(SEEBCD) 6.3 (SE0800) 6. 30SECBCO) 6.3u(SEEBCO) 6.3 (SEEBCD) 6. 30(SE=8C9) ne, B 2000-6, avSBCHRO) Gabe Ane 3v(sErBEO) (ne, F 1-500 SEB) (aE 10-167(Se08C1)EEN, PATO. Az) ——_—ESCAPTON cist et-o10-se9-c10 cag 47-6. 30(5B2BC0) C12 $Y-016-155-010 CaP. = 1000-E.3v8ecend) C157 e7-910-075-060 cP. B 10-16V(SBCHCL) ert s2-130-007-020 cap Taine 200P( ECW} SL St-0G3--108—C-COTL, aTURISELQEH HL 0-120-003-0108 x-maL,12.osoomma send) HD SOC1TP-343-010 HoRAL 17.7344 SEO sue c.pevab> s7-045-356-019 yor,ae-s10Ta a3 310A 30 SEAR HSK 17319 00 OF vite A: — ¥/CHIIP RESISTOR PART CODE TL tmz Faue stu Van of extn $y Fit Cap resistor a oe HeRE F FEZ RRR TD BAS=F ox Warage Type Tolrmnce_| Sym BE Zfom | LW | Revisor code 8 171687 1608 5% c L is [os [oss] 08 Aw 3216 25% a War [ ie [oss 128IC BLOCK DIAGRAM IC, NUM2244L. @ND Vout v* ving (Mute) |swi|swe] OUTPUT SIGNAL Ge Vint He ving UH] H Ving Vint swt vine swe IC, LA6530 5 = 2 + z 3 = 2 2 £ 3 a z 5 g 2 gs § 3 & & 3 5 5 4] 5] ra] 3] [| rt fio 5 At ‘amps + Thermal Shutdown “ ‘Ampe vee [>] MuTE [8 out [a] eno [= np [a outa [a] vint- vint+ [o> 10(wHOaW G9 / GOA NIV IEA) LWWHDVIG xOOTEg°9 GOAa) (aon -7en) z-wywo¥I 40018(HON G0 ,/ GOA NIV “IrA) EWvHOVIG HOOTE.BLOCK DIAGRAM-4 (VAL: VOD) (Fiveo ¢.8oye O14 oe Saag ind a ‘ovat \ e-8| eT Ee aL watoraa 9344 wo z x =a eho t TET LI Moa = ar36904 I aaa ‘ozat bcc Eel “|semnenm ossI00d TROIS. OMS oo (LEE bere aeiz-wsx gf >0La (sn) snyuovia O01{a9 woan ao [a (vHOaW Go "eA) -WWHOVIG OLYWaHOSWears (GOA NW “"en) ZWwHOVIG OLLWINaHOS:i laae (Gon "TeA) ewvHOVIG OUYWHOSWIRING-2 (VSL: VOD)WAVE FORM D umaecarovn — vormpwiiv TIMEADIV: 100s \ U8 Pin @ (OSC2) VOLTIDIV: 1V TIME/DIV: 100ns ® usm vounw:1v TIME/DIV: 1000s ® vurne Vout: 1v TIMEDDIV: 1000S atWIRING-3 (WR) 1 1 [D) DRIVE c.B ( CH igrres = | ea | *7 tae (WHOM G9,/00A NIV =TPA) -ONTUIM,(WHOAW G9 WA) S-WYYDVIO OLYWSHOS1 i ann im fm Piper itty (Gon NIWn “Wwa) 9-WwHOVIG UWW3HOS‘SCHEMATIC DIAGRAM-7 (VAL: VCD 1/2) | | aGaRSB STARE oie O20 Breese) peoal snecuanssnssezenesty‘SCHEMATIC DIAGRAM-8 (VAL: VCD 2/2)99099600: Ts Ske 9 SER an@°9)@3)SCHEMATIC DIAGRAM-® (VS: MAIN VCD 1/2) idlwain veo e-6 072 aSCHEMATIC DIAGRAM-10 (V5: MAIN VCD 212) cy lave se infant isha) (ijsleaaah = ayWAVE FORM D cx: Pinto cacxy vou: 1v fostic TIMEIDIV: 10ns Veo PLay TVMODE: «NTSC “Pal {PAL AUTO ® carne verw vounpwv: 1v 27M 350K TIMEIDIV: 100s VoD PLAY TV MODE: «NTSC ‘Pat {PAL AUTO 0 28.37SMHz VOLTIDIv: 1v ‘CDGPLAY TIME/DIV: 1008 TV MODE: «PAL + PAL AUTO 10301 Pin (V SYNC) VCD, CDG PLAY VOLTIDIV: 1V TIME/DIV: 10nS VCD, CDG PLAY 34v SoHe 34v1€301 Pin $ (H SYNC) VCD, CDG PLAY TV MODE: + NTSC PAL AUTO. G3.50US 15.734KH2 a 34v VCD, CDG PLAY TVMODE: PAL aus 15.625kH2 3av VIDEO OUT VOLTIDIV: 200m¥ C401 © side TIMBDDIV: 10yS CDG PLAY: CD-T03 TRACK? TV MODE NTSC VCD PLAY: CD-T0STRACK4 VOLTDIV: 200mV TV MODE NISC TIME/DIV: 10uSa°9 vHOan 09 (8) (vHOaW G9 :SA) L1-WwwoVIa OUVWSHOSWIRING-7 (V5: CD MECHA) 1 2 7IC DESCRIPTION IC, CXD2500BQ Fox | PaNane [10 Daina 1 FOK | 1] Peas OK pt omit Ued ir SENS oupu andere at squnce 2 FSW [0 | Spine mor ouput fe selon opt 3 MON | 0 Shinde moterONOFF ent op 4 MDP |_| Sine motor sono cont 5 MDS | 0 | Sine motor seo cou ; voce |g | Haintuhen GF is emnshs dO He amiG EH Lespawhn Lis continuous 8 nes 7 Be ea Yeo | 0 | Oselanr cient or amlog EMPL Yoo! | 1 | Ontor ieutinpt Trang EFMPLL, LOCK = 86 wo test [1 | TEST emi, Neraly OND. if POO |__| Chars pup ott for alg EFM PLL a as |= ox r ne | = [ne a Sse 5 Ne = [renee 16 veco | 0 | Chae up ony fora pick PLL i vert [1 | lek apt fom oneal VCO forvatichfeconar= 1634 We 7 FLO | | iteroupormaxer PL sve = il PLL 9 Fur ieee 20 PCO. oO Charge pump output for 21 WSs | = | amiog cn. 2 GET. | 1 | VCO contol vag inptoemaner B ‘Avo | — | Anion perso. 65) ra eS ieee 2s BIAS | 1 | Asymmey ces conan coentapat 5 sev ema oe 2 nsvO | 0 | BPM al sning ouput = Vs = DD) 2 TASYE__|1_| Leasymmaty ceat OFF. Hasna sik ON B ne | =p Neuse 0 Bast [1 [Aa a aetpt ne seston ng Sen ope aL ee apr er 31 wOcK || VA nec fr distor. Wordlokf=2 Fs 2 LRCK | 0 | DiAimere ota ERclsk 33 VDD Power supply. (+3.5 V) 2 comma | o | BAISO1S) cup wicnPSSL=H, @-Bicaeh da win PSSL=L COMP.MSB fs). a BCLK | 0] DAIS ouput when PSSL=H Ase dock when FOBL = - we |g | Palos when FSSL=H. GL slaseal dan when PSL=I. G's COMP 38) 7 KE] 0 | DAIS ouput when SSL =H Geisler cnt wien PSE Fy NC | 0 | DA?2ouputwhenPSSL=H. 64OLIo ER cok wien PSSL= 58Pin No. Pin Name vO Description 9 ‘GTOP (0 | _DAIT output when PSL =H. GTOP output when PSSL = 40 XUGF © | ALO output when PSSL =H. XUGF output when PSSL = L. 41 XPLCK © | _DA09 output when PSSL =H. XPLCK output when PSSL = L- 2 Fs (© | DAOS output when PSSL =H. GFS output when PSSL. a RFCK (| DAO7 output when PSSL = H. RFCK output when PSL. “4 2P0 © | _DA06 output when PSSL =H. C2PO output when PSSL = L. 6 XRAOF, ‘© | AOS output when PSSL =H. XRAOFoutput when PSSL=L. 46 MNT3 © | DAO# output when PSSL =H. MNT3 output when PSSL: a7 MNT2 © | DAO3 output when PSSL =H. MNT2 output when PSSL: 8 MNTI (© | _DA02 output when PSSL=H. MNTI output when PSSL- ° MNTO (© | DAO! output when PSSL=H. MNTO output when PSSL- 50 APTR, (© | _ Aperture correction control ouput. H when R channel SI APTL. (© | Aperture correction control output. H when L. channel 2 vss — | ann. 3 XTAL 1 | Input to 16.9344 MHz X°tal oscillator circuit. or 33.8688 MHZ input. 4 XTAO © | 169344 Miz Xtal oscillator output, 3 XTSL. 1_| Xtal selection input_L when Xtal is 16.9344 MHz. H when 33.8688 MHz, 56 FSTT © | 2 divider output of the pins $3 and 54. Does not change with var-pitch. 37 CaM © | 4.2336 MHz ouput. When vari-pitch is performed, it changes too. 58 Clem © | 16.2336 MHz output. When var-pitch is performed, it changes too. 9 MD2 1_| Digital-out ON/OFF control. ON at H, OFF at L. 0 bout © | Digitat-out terminal, oi EMPH ‘0 | Houtput when the playback dise has emphasis. L output without emphasis. a WFCK (0 | _WFCK (Write Frame Clock) output a SCOR © | Hoowiput when $0 oF $1 ofthe subcode sync is detected, a ‘SBSO ‘© | Serial oupot of Sub P to W. 6 EXCK 1_| Clock input for SBSO read out 6 S80, (© | SubQ bit and PCM peak level data. 16-bit output, a sQcK 1 | Clock input for SQSO readout 8 MUTE 1 | Mute at H, Release at. @ ‘SENS © | SENS output. Output wo CPU. 70 XRST 1_| System reset. Reset at L. 7 DATA 1_[ Serial data input from CPU. n XLAT 1_| Latch input from CPU. Latches serial data at fall-down edge. B vp> = | Power supply (3.5 V). 74 LOK 1 | Serial data transfer clock input from CPU. 5 SEIN 1_| Sensor input from SSP. 16 NIN 1 | Track jump number counted signal input 7 DATO (© | Serial data output to SSP. 8 XLTO © | Serial data latch output to SSP. Latches at fall-down edge ~ ‘cLKO. (© | _ Serial data transfer clock output to SSP. 30 MIRR I signal input, Used for jump of 128 tack or more at auto sequencer. EyIC, wPD78044BGF Pin No PinNane | UO Description 1 DOON © | Digital ouput, ONOFF ouput 27 NC = |_Notused ® vp —_| PWR. +5 V powersupply 9 MCLK | UO | Serial ciock UO. 10 CDATA © | _seviat data ouput fn MDATA T_[__ Seria data input 2 O-cLK ©__| _ DSP sera clock ouput 8 O-XxLT 0 | DsP sera latch output i Os0cLK | 0 | DsPsub Qreadout clock output 15 ODATA (© | DSP erat data ouput 6 ESQDATA _|_1_| _DSPsub Q data input 7 RESET i ‘System reset input. ® SENS 1_[_DSPSENS input » XRST (© | CDaystem reset output. 20 AVS —_[ PWR. GND potential of A/D converte input 21 1FOK 1 [_ASPFOK input 2 Lars 1_[_ DSPGFS inpu. 2 = — | Connected GND. 24 LILSW 1_| Pickup timic nite input 25 Focsw 1_| Tray OPEN/CLOSE switch inpot 26~28 = — | _Comected GND. 2 AVDD, —_|_ PWR, Analog power supply of A/D converter input 30 AVREF 1_| PWR. Reference voltage it of A/D converter input 31 = — | Connected GND. 32, NC coe Open terminal. 33 vss — [PWR GND potential 34 xi 1_[_ CLK. Terminal ford.19 Miz clock oslo. 35 x2 © | CLK. Terminal ford.19 Miz clock osilator. 36-38 NC. — | Novused 2 CHUSY (© | MPEG status output 40 MSTBY T_[ _ Main microprocessor stats input a Lock (© | Main microprocessor serial clock output. 2 DATA (© | Main microprocessor serial data output @ DREQ (© _| Main microprocessor status output. 4 TKEY | _ Main microprocessor serial data inpot ro SCOR 1 | _DSPSCOR input. 4 BUSY 1 _[_ MPEG staus signal input a7 = — | Connected GND. 8 1c —_|_ PWR. Connected to Vs. ® MUTEL (© | _Lechannel analog mute output 30 MUTER (© | _Rechannel analog mute output 60PiaNo PinName | 10 Desriton i DSENS 1 _| Tuma sensor input. 2 vp — [PWR +5 poner supply. sa NC — | Novosea ‘5 o-ropN | 0 | Tray OPEN output « ois © | Tray CLOSE ouput a O-DFWD | _O | Tumble forward eoaion output « O-DRVS _|_O | Tumble revere rotation output. 6.70 NC = | Nowwsed 7 VLOAD | — | PWR. -27V power supply for FL pulldown, R= 76 NC — | Norusea 7 veo © | _ VIDEO CD setecion ouput 78 ‘CD FUNC o CD function selection output, ~ GMuT ° 2 con ° 6IC, LC7872E Pin Nol Pinname | WO Description 12 S182 =| DSP select pin for CD. (Connected io VDD) 3 ‘SBCK (© | Subcode read/write clock 4 SSY T_|__Subeode fame syne signal 5 Pw 1 | Subcode read/write data. 6 SBSY 1_| _Subeode Block syne signal 7 YDDI —_| Power supply for digial block, (Connected vo +5¥) 8 cE 1_| Control pin when serial input or serial output, (Conected to GND) 9 Do (0 | Serial dato output. (Connected to GND) 10 Di 1_| Serial data inp. (Connected to GND) 0 a 1_| Clock when inputting/outputing serial data, (Connected to GND) 2B MUTE 1 [Control signal disabling the subcode, B VSsi —_|_ GND for digital block 4 WE © |_DRAM conto pin. 15 RAS (0_| DRAM contol pin 16=23 AO~AT (©_| DRAM adres pin Py DBO WO | DRAM data pin, 25 TAS (© | DRAM contol pin. 26 DBI WO | DRAM data pin, 2 DE © | DRAM contol pin 28 DB2 WO | DRAM datapin 2 DBS vO | DRAM data pin 30 ce 1_| “L":Nonmal mode "H": Color bar output (Not used) 31 CDGM. (© | “TP output when CDG disk (Not wed) 322 "TRANSO (© | Transparency digital ouput (Noc used) 33 ‘TRANS! (© | Transparency digital ouput (Not used) a ‘TRANS? © | Transparency digital ouput (Not used) 35 TRANS3 © | Transparency digital ouput (Not used) 36 TRANS © | Transparency digital output. (Not used) 37 "TRANS © | Transparency digital output. (Not used) 38 vss2 — | Composite video DAC GND pin 39 vop2 —_| Composite video DAC power supply pin. (Connected 45V) 0 BIAS (© | Capacitor connecting pin for eliminating ripple at VIDEO © | Composite video output pin (bi DAC outpd. 2 ‘TEST 1 [Test pin, Seto “L” normaly: (Connected to GND) ‘a ne 1 | Wien NP2pinis“HPs Hi 2630 L: 260 ‘When NP2 pins “L": H:312H L: 14H (Not used) 4 FSCIN 1_[ "Sbearier clock input pn, (feedback resistors built i) (Connected to GND) 45 SYNC © | Verical syne signal ouput pin. (Not used) 46 TESTI 1_|_Testpin, Seto "L" normally. (Connected vo GND) a7 Ys (© | Superimpose control ouipat. (Not used) 8 SINE (© _| Composite syne signal output. (Not sed) 6Pin No, Pin name vO Description 0 GND — |_ ano. 50 EFLG © | Error status monitor pin. (Not used) 31 FSX © | _Forerror status monitor trigger. (Not used) 2 DEN 1_| Disk information display enable. H: BGC L: Enable (Connected to GND) 3 PaLID | Extra! consol pin when superimposing with PAL (plrup resistors built (ot used) 4 vbb3 = | Digital power supply (45¥) _ _ (o | Sutsarierctock output, NTSC mode: 3.579585 MHz PAL mode: 4.433619 MHz (Not used) 56 ‘ypp+ — | Digital power supply @5¥) 37 RESET 1_[_ Reset input pin 38 NBL 1_| NTSC/PAL selection pin. (RGB encoder) “H”: NTSC “L”: PAL 39 NPD 1_| _NTSCIPAL selection pin, (CD-G decoder) “H”: NTSC “L”: PAL © SON. 1 _| _Superimpose ON/OFF pin. (Connected to GND) 61 XIN2, 1_ | _Ceystal oscillator 17.734476 MHz. (for PAL) a xOUT2 (© | Crystal oscillator 17.734476 MH. (for PAL) 6 XINI 1_| Crystal oscillator connection 14.31818 MHz. (for NTSC) 4 xouTL © | _ Crystal oscillator connection 14.31818 MH (for NTSC) 63IC, CXA1782BQ Pin No. Pin name vo Description 1 reo ‘9. | Foes emor amplifier ouput pn. This pin is conneted othe FZ2C comparator input internally. 2 FEL 1_| Focus error input pin 3 FDECT 1_| Capacitor connection pin fr time constant used when there is defect. B a 1 | Tibi is connected to GND via capacitor when high frequency gain ofthe focus servo is attenuated, 2 ory 1 | Bisisapin where the tine constants extmally comected oie the low frequeney sain ofthe focus servo. FEO. © | Focus drive output FEM 1_| Focus amplifier inverted input pin. : seen 1 | Tisispin whee te time consis exermally connected to generate he focus search waveform. > rou | Tisisapin where the sleton tie constant is extemally connected to set the {racking servo the high frequency gain. i" ro 1 | Tisiva pin where te seestion te constant is extermally connected fo et the tacking high frequency gain, ML FSET. 1__| Pin for setting peak of the phase compensstor ofthe focus tracking, 2 TAM 1_| Tracking amplifier inverted input pin. B TAO 0 | Tracking drive output 14 SP 1_[ Sted amplifier noninverted input pin. 15 SLM 1_[ Sled amplifier inverted input pin 16 SLO © | Sted drive output ” ser {| Teseurent which determines height ofthe fous Search, ack jump and led ick s input 18 vec — | +5 ¥ power supply pin. 19 cK 1_| Seria data transfer clock input from CPU. 20 XLT 1 | Laten input from CPU. 21 DATA 1_| Seria data input from CPU 2 XRST. 1 | Resetinput pin. Reset at L. 2 ‘cour (© | Signal ourpat to count the number of tracks. m4 ‘SENS (0. | _FZC, DFCT, TZC, Gain or BAL is output depending on the command from CPU 25 FOK © | Output pin of the focus OK comparator. 26 cee (© _|__ Input pin where the DEFECT bottom hold output is capacitance coupled. 21 cl 1_[ DEFECT bottom hold output pi Ey cB 1_| This is a pin where the DEFECT bottom hold capacitor is connected, » o {| Tisisa pin where the MIRR hold capactor is conneted and MIRR comparator noninverted signal is input 30 RFI 1__| Input pin where the RF summing amplifier output is capacitance coupled. 3r RFO. (©_| _ RF summing amplifier output pin. ye patter check point) a 1 | RF summing amplifier invened input pin, Gain of RF amplifier is determined by the resistor connected between RFO and this pin 64Pin No, Pin name Description 3 LD ‘APC amplifier output pin. 4 PHD APC amplifier inpot pin, as36 pupi~2 RF I-V amplifier inverted input pin. “These pins are connected tothe A+C and B+D pins ofthe optical pickup. 37 FEBIAS Bias adjustment pin of the focus error amplifier. 36-39 Re F and E IV amplifier non-inverted input pins “These pins are connected to the F and E ofthe optical pickup. 40 EI ‘Gain adjustment pin ofthe I-V amplifier E. 41 VEE “GND connection pin 2 ‘TEO “Tracking errr amplifier output pin. E-F signal is output. 2 LPEL BAL adjustment comparator input pin. 4 TEL “Tracking eror input pin 45 ATSC ‘Window comparator input pin for detecting ATSC. 46 Tec “Tracking zero-cross comparator input pin, a7 ‘TDFCT ‘Capacitor connection pin forthe time constant used when there is defect 48 ve ‘DC voltage ourput pin of VREF. (VDD/2)IC, CL480 Pin No PinName | ‘UO Description 1 SEL? 1 | Host address bus 2 DS 1 | Datastobe 3 RW 1 | Readiwrite 4 CFLEVEL | © | Coded data FIFO level status. Open dean, 3 “DACK (© | Host data acknowledge. Open drain, 6 DO vO | Host data bus, 7 yobs = _| Powersupply pin. Used in 3.3 V. 59 DI,HD2 | VO | Hostdatabus 10 vss — | cnn. 115 HD3~HD7 | UO | Host databus 16 Ss — | enn. 0 “Test 1_| Testierminal, Normally fixed to High 18 vss — |_ np. 19 XTLIN 1 | Gtobal clock. 40.5 Mie 20 XTLOUT | O | Global clock. 40:5 Miz 21,2 ‘ybD3 —_[ Power supply pin. Used in 3.3 V. 23~28 MDo~MDs__| U0 | Memory data bus 29 ‘yobs —_[ Powersupply pin. Used in 3.3 V. 30,31 MD6.MD7__| VO | Memory data bus. 32,33 | -MCEO,-McEI_| O | Chipenabe 3437 MDS=MDIT__| VO | Memory data bus. 38 vss — | ono. 3942 | MDI2=MDI5__| UO | Memory data bus 8 VDDMAX | — | Powersupply pin. Used in 5.0 V. “4 “LEAS ©_| Lower digit, column address strobe 4 -LCASIN 1 | Lower digit, data latch enable. 46 vss — | ono. a “MWE, © | Write enable 8 UCAS © | Higher digi, column address strobe ® ‘yobs — | Power supply pin. Used in 3.3 V. 30 “UCASIN 1_| Higher digi, data latch enable. 51,52 RASO,RAS! | O | Loweraddres strobe 53-57 MA9~MAS |__| Memory address bus 8 vss — [_ex. 9-68 MAd—Ma0 | 0 | Memory address bus. 4 RESERVED | — | Reserved 6 7) =| Power supply pin, Used in 3.3 V. 66-2 ‘ybo~vp6 | 0 | Pixel databus. RGB or YCHCr forma B vss GND. 7476 ‘yo7~vb9 | _O_| Pixel data bus. RGB or YCbCr format. 7 yobs = | Powersupply pin, Used in 3.3 V. 66Pin No. PinName | 10 Description 78-80 | VDIO-VDI2__|_O | Pinel date bus. ROB or YCACr format 8 Ypb3 Power supply pin. Used in3.3V. 32-84 | vpis~vpts | © | Pixel data bus. RGB oF YCOCé format. fo VSS = [| enp. a6-89_ | vpie~vo19_| 0 | Pixel databus. RGB or YCHCr format 90 vss — | ono. 91-94 | vb20—vp23_|_O | Pixeldata bus. RGB or YCHCr format 95 CVSYNC orcsY_| VO | Vertical syne signal. 96 SHSYNC VO | Horizontal syne signal 7 “OE 1 | Video ouput enable 98 ‘vop3 — [Power suppiy pin, Used in 3.3V. » VCLK WO | Video lock. 100 vss — | ono. 101 “RESET 1 | Hardware reset. 102 vss — | eno. 103 D.c2P0 1 | Dataecror. Used during CD-ROM data input. 108 CDLRCK 1 | tRciock 105 CD-DATA 1_| Serial data input from CD-DSP. 106 CD-BCK 1_| Bit clock from CD decoder. 107 DALRCK | O | LRelock 108 DADATA | _O | _Bitserial audio sample signal 109 DABCK © | Audio bit clock. 110 pps — | Power supply pin. Usedin 33 V. m1 DA-XCLK 1 | Extemal audio frequency clock 112 vpp3 — | Power supply pin. Used in 33 V. 113 INT © | interrupt request. 14 RESERVED | — | Reserved 115 HOSTENA | 1 | Hostensble 116 RAM_ENA 1_| Boot ROM enable 17 RESERVED | — | Reserved 18 DAC_EMP | 0. | Output emphasis fag. 119 cppaemp | 1 | tepuremphasis fag. 120 RESERVED | — | Reserved. 121 “FMV_DET | _O. | FMV detection. L: FMV deteced 122 eppavep | 0 | Inputdata identification. H: CDA. L: video CD. 123 ‘YDDMAX 1_| Powersupply pin. Used in 50 V. 124 RESERVED | — | Reserved. 125 vss — | ono. 126 RESERVED | — | Reserved. 127,128 | HSELOHSELI_ | 1 | Host address bus. orIC, CXD1178Q Pin No. Pin Name vo Description 1-8 RO-R7 916 Go~G7 1 | Digital input. 17-24 B0~B7 Ey BLK 1_[ Blanking pin. No signal at “H” (Output OV). Output condition at “L. 26 cE 1_[ Chip enable pin, No signal (Output OV) at “H” and minimizes power consumption. 2 RCK Ey GCK {| Clock pin. Moreover al input pins are TTL-CMOS compatible, 2» BCK 30,31 Dvss — | Digital Gp. 2 vB © | Connect a capacitor of about 0.1KF. 3 AVS. = | Anatog GND. 4 ‘VREF 1_| Set ful seale output value. 35 IREF 1_| Connect resistance 16 times “16R” that of output resistance value“ 36 RO (© | Inverted current output pin. Normally dropped to analog GND. 3 RO (© | Current output pin. Voltage output can be obtained by connecting a resistance. 38 ic (© | _Iavered current output pin. Normally dropped to analog GND. 39 Go ‘© | Current output pin. Voltage output can be obtained by connecting a resistance. 40 BO (© | Inverted current output pin, Normally dropped to analog GND. a BO ‘© | Current output pin. Voltage output can be obtained by connecting a resistance. a VG 1 | Connect a capacitor of about 0.14. 5-46 ‘VDD. — | Anatog vob. 47,48 DYDD — | Digital vob.IC, MC68HC705 Piao PinNene | 00 Deseipton 1 RST 1 | Reet 2 IRQ 1_|__ MPEG DECODER request signal 3 ver: — | ROM write power. an PAT=PAO__| UO | MPEG DECODER data bus 7~0. 118 PB0-PB2 | O | MPEG DECODER register selon 0~2 5 3 (©. | MPEG DECODER data RAW selec. 16 Ps (0. | MPEG DECODER date srabe " PBS 1._|_ MPEG DECODER data acknowiedse 1 P86 1 | cba bic seam detect. 9 PB? 1 | eDDANCO select 20 vss — | Power ground 21 PCT 1_|_ MPEG DECODER FIFO suas. 22,23 pos.pcs | — | Novus 2 Poa (© | MPEG DECODER reset signal 25.26 pospc2 | — | _Nocosed 27,28 peipco | 0 | Keyscanout 0 za ROL - ‘Not used. 30 DO 3mm pp2=PDS__ |__| Key scaninputO~3. 8 TCM (© | Remote data ou 36 P7 = | Noted 7 car 1_| Remote datain ze39 | oscnoscr | 1 | Xia 0 vob = | Pomeesv, cyIC, wPD6376 Pin Name Desesiption Pin No. 10 ‘As this terminal is “Low” or open, Loch data and R-ch data are inputted for serial data 1 FSSE 1 | by the pin 15, As this terminalis “High”, Lch datas inputted by the pin 15, Rc data is inputed by the pin 14, Pllsdowned by the 100k resistance in IC) 2 D.GND —_| Ground terminal forthe logic cect _ 3 NC = 4 D.vDD —_| Power supply terminal forthe logic circuit 5 ‘GND — | Ground terminal forthe analog circuit 6 ROUT (© | Output terminal forthe igh analog signal 78 | __A.voD __| — | Powersupply terminal for the analog circuit = o.10 | ReRER ner | ~ | OP*lonal Amplieretenc is erninal, Normally connect toAGND via a [capacitor nu | Lour (© | Output terminal forte left analog signal _ 2 ‘A. GND —_ [Ground terminal For the analog iui. ‘As the pin 1 is "Low" or open this is input terminal for leigh identification signal 8 LRCK 1 | Asthe pin 1 is “High”, tis is input terminal for word identification signal of input ac _ ] "As the pn 1 is“Low” or open, this is lefuright selection terminal for LRCK signal. At uo | tess | High” OFLRCK signal, set LRSEL. pin at “Low” for Lech DATA input, At“Low” of [LRCK signal, set LRSEL pin at “High” for L-ch DAT input. As the pin 1 is “High”, {hiss input terminal for Rc serial dat, s = 1 | ABtepin 1s "Low or open, his input terminal for Lsh and Rh serial data. As | the pim 1 is “High”, this is inpot terminal for Lch serial data 16 BCK 1_| Input terminal for read clock of serial input data. 70IC, CXA1645M 1 meee =a fa - - Saw] 1 | amlog ns npr emia a | BIN | x | [nc «| Suber ipa al (oe NISC, PAL node ow emia NISC Ven PALGND | 3 Ouiput terminal o monitor the BF pulse. Unable to drive 75 8 Wad | 3 eral ine conn fr ial can come os email | : Compose se sigal ap emia lg TL | SiNC peed L($08¥ H(E20%) | i NC _— Tne i 2 vee — | Power supply eminal 1 6 REF Terni emis al laces ane ri VREF | =] Tena tes alge en 5 cour [0 | caren sia ouput teria ” sama) 4) Tiitlio tecnico wai gay op nd Ysieut pr sag eer Gee " ro 1 | GxD pening upon NTSCor PAL mae NTSC: 2040 (18) PAL: 16K) Woe | | over spn an Ce — mnIC, HD6433042F06F Pin No PinName vO Description 1 vec 1_|_ Power supply. 2 (CDG DIN © | CDG decoder serial data signal. 3 CDG XLT © | CDG decoder latch signal 4 CDG CLK © | CDG decoder clock signal. so capspo~2 | 0 | Gate array DSP format 0~2, 8 DRQCDI 1_| CD-ROM decoder data request signal 9 ‘DROMPEG 1_| MPEG decoder data request signal, 10 ‘RESO, (| Extermal reset output. W GND 1_|_ GND. 2 ‘TxDO (© | Serial imertace (RXD). B TXDI 0 | cxfortest 4 RXDO 1_| Serial imerface (RXD), 15 RXDI 1 [RxD fortest 16 CKO Uo | Serial imerface (SCK). 7 “MPRST (© | _ Peripheral reset. L: RESET ON. 18~21 Do~D3 UO | Data bus o~3. 2 GND. 1 [_ ovo. 234 Dé~Dis WO | Databus 4~15 35 vec 1_|_ Powersupply. 36~43 A0~AT (© | Address bus 0~7. “4 GND 1 | ono. 45~36 AS~AI9 (0 | Address bus 8~19. 7 ‘GND 1 | ono. 38 WAIT 1_| External wait signal, 9 GLUE ON (© | DMA glue circuit enable 0: OFF. 1: ON. 0 M_EMPH (0. | _ MPEG AUDIO emphasis 0: OFF. I: ON. 6 FAL © | System clock output. a ‘STBY 1_| Standby. Hardware standby mode at low level). 3 RES 1 [Reset input. Reset at ow. oo NMI 1_[__Non-maskable interrupt, (Non-maskable interrupt is requested). 6 GND, 1 [| ono. 6 EXTAL {| External erystal is connected to this pin 7 XTAL 1_| External erystal is connected to this pin oe vec 1_| Power supply. o as © | Address strobe signal 70 Dd (© | External address read enable signal. 1 WR (© _| External address high write enable signal n WR © | External address low write enable signal 73~75__| MODO~MOD2 | 1 | Mode terminal. Operating mode is set using this terminal 16 Avec 1_| Power supply terminal of A/D converter and D/A converter. 7 VREF 1_|_ Reference voltage input to A/D converter and DVA converter. 72Pin No. Pin Name uO Description 78,79 P70,PT1 T_[_ IN pon 0,1 fortest. 80 PALINTSC 1_|_PALINTSC status 0: NTSC.1: PAL. 81 REQCD, 1_| Seria interface (REQ._CD). a8 Pr4~PT7 1 | Reserve 86 ‘AGND 1_| GND terminal of A/D converter and D/A converter 87 TRTCDDRY [1 | Serial imerface iterupt. 8 SNTCDDEC [1 | CD-ROM decoder interupt, » INT MPEG 1 | _ MPEG decoder interrupt 30 TRO 1 | Reserve, 31 P84 1 | Reserve. 2 GND 1 | ono. 8 DONECDDEC | 0 | CD-ROM decoder DONE signal oa DONEMPEG | © | MPEG decoder DONE signal 95 DGVOFF | 0 | CD-G decoder video OFF signal. 1: VOFF, 96 SYSMUTEI | _O | Audio mute | signal. 1: mute ON. 7 INTFLDO 1_|_EVEN/OFF input signal. 0: EVEN. |: ODD. 98 SWAUDIO | 0 |) Audio select signal. 0: CD-G/DA, 1: MPEG.” 9 SYSMUTED | © | AudiomuteO signal. 0: mute on. 100 REQMPEG | 0 | Serial interfvce (REQ MPEG)IC, wPD65622GF-239-3B9 Pin No. PinName | WO Description 1 iRcKcD | -O 2 SPATACP {© | sain data signal 0 CXD1186, 3 ‘BCKCD ° 4 capoco ° 5 CSROMA | 0 | _ Chip seect signal to CXDIIR6 (box side) 6 TSROMC | O | _Chipsetece signal vo CXDIISG (CPU side) 7 DACKROM | O | DMA acknowledge signal to CXDIIS6, @ DRO 1_| Data wanster quest signal from CXDII86. This signal i active high 9 ROMIRD (© | _Read/write signal 9 CXDIT86 10 ROMWR © | _Readwrte signa to CXDIIR6. in EMPHI 1_| Tis signal allows inputting she main data from the CD dive 2 GND — |_ ono. B SDATAL 1 ad — "| ris signal allows inputing the main dat from the CD dive 5 LRCKI 1 16 Garo 1 7 ‘GND =| eno. 18 169M 1 | 169344 Metz oxsilator circuit input signa » 169F (© [169344 Miz oscilator circuit ouput signal. 20 ‘GND — | ono. zi GsFSY 1 _| _ Write frame clock signal wed o input the sub data fom CD dive. 2 EMPO (© | Main data signal co CXDII86 B LRCKO (© | Adio data signal w andio DAC 2 SDATAO | 0 | Autodata signal to audio DAC. a RESET (© | Active igh reset signal. 26 ‘GND — | ono. a BCKCO (© | Audio data signal vo andio DAC 8 COLE 1_| ‘The np signal which makes the glue cteit valid from GSFSY input 2 Cassy [0 | Nosed 30 spatama | 1 31 BCKMA T_| Audio data signa fom uPD61010 2 LRCKMA 1 2 ‘GND — | ono. 4 vec — | vee 3 Teom (© | 169344 Me ouput signal. 36 GND — | ono. a ws © | Control signal 19 uPDSION. 3% CSMPEC [0 | Chip sete signa to CXDII86. 9 TW © | Control signal uPD6IONO. 0 INT 1_| _verupt request signal rom HPDGIOIO, ‘This signal is active high a DAK 1_| Data seknowledge signal from uPD61010. 74Pin No PiaName | UO Desevipiion a DRED T_|_ DRAM dita wansfer request signal from uPD61O10. ny DACKMP |_| DMA acknowiedge signal wPD6IOI0. 4 DAK 1 | Bitstream data wansfer request signa fom uPD6IOIO. 5 CSC |__| Chip setecrsignal wo standard cel 4% ‘GND — | ono. a RESET. 1 | _ System est signal. Dy GND — | np. 0 CSRAM © | Chip stecsignal tothe system RAM. 30 WR 1 | Lower data write signal from CPU: 31 HWE 1_|_ Upper data write signal from CPU. 2 RD 1 | _ Data ead signal fom CPU. 3 GND — | eno, 34 aS, 1 | Address strobe signal from CPU. 35 CIO © | Optional chip select signal 56-83 ‘AI9~A12__| 1_| Address signal from CPU. o ‘GND — | Gnp. a war © | Wait signal o CPU. 7” GLUON {| Thssenal makes the gle loi valid inorder to prevent CPU DMAC rom wouble ‘This circuits made vali at high a “SELTE | _tnput signal to select 12 MHz or 16 MHz CPU clock a EMPMA 1 [Audio daa signal from uPD61010. ® ‘GND = | oxo. 70 FAL T_ [Basic clock signal (12 MH) from CPU. n ‘GND — | onp. BA vec — | Yew 3 GND = | enn. 4 TINTMPEG | _O- | _Incerupt request signal to CXDII86, 78 SWAUDIO |__| Selection signal between MPEG audio and CD-DA audio signals 76 DRT © |_DMA transfer eques signal to uPD61O0. 7 DRO, (© | DMA transfer request signal fo CXDII86. 7e—80 | _GaDSP2~0 | 1 | Formatselect signal to conver format of the main dats from CD drive. 75IC, CXD1186CR Pin Name vo Description AO~A3 1 | CPU address signal 3 MDs 1 | Host mode select signa 67 HAO, HAL 1 | Host address signal. 8 XHCS: 1_| Chip select negative logic signal from the host. 9 HINT 0 _| Interrupt request negative logic signal tothe host. 10 ‘GND — | oxo. 1 XHRD WO | Data read strobe signal from the host orto the SCSI control IC. 2 XHWR VO | Data write swobe signal from the host or to the SCSI control IC. 13~20 | HpBo~HDB7 | VO | Host data bus. 2 GND, — | oo. 2 DBP VO | Error flag. Host data bus 2 XRST 1_| Reset negative logic signal. a ‘oats Fequest positive lope signal othe host, Or DMA acknowledge negative logic signal tothe SCSI contol IC. as xHAC 1. | DMA acknowledge negative lopic signal from the host Or data request positive logic signal from the SCSI control 26 XTC 1_[ Terminal count negative logic signal. 2 ‘ADRQ 1_| DMA request positive logic signal from ADP. 28 XAAC © | DMA acknowledge negative logic signal to ADP. 29,30 BAO, BAL © | Butter memory address. 3 ‘vpD = _| Power supply (+5 V) terminal 32-39 BA2~BA9 0 | Buffer memory address 40 ‘GND — | enn. 4146 BAI0~BAIS | 0 | Buffermemory address, 4 XMOE © | Buffer memory output enable negative loge signal. 48 XMWR © | Buffer memory write negative logic signal 9 ‘BDBO WO | Butler memory data bus. 50 ‘GND, — [ ano. si~s7_| _BpBI~BDB7 | VO | Butter memory data bus 38 BDBP WO | Buffer memory pointer data bus. 9 XTL2 © | _X°TAL oscillator cieuit output terminal 0 XILI 1 | X°TAL oscillator input terminal. 6 GND) — | ono. a HCLK © | X°TAL 1 divided-by-2 clock signal 6 LRCK 1_[_ LR clock from CD player. o DATA 1_| "Serial data from CD player. 6 BCLK 1 | Bit clock from CD player. 66 c2P0) 1 | C2pointer from CD player. 70 pgo~p3 | vo | CPU databus a voD_ — | Power supply (+5 V) terminal nas pBi~DB7 | vO | CPU databus, 7%Pin No. Pin Name Description 76 xcs Chip select negative loge signal from CPU. 7 XRD Cinema register read-out strobe negative logic signal from CPU. 8 XWR) IC iniemal register write strobe negative logic signal fom CPU, p INT Interrupt request signal to CPU. 0 GND GND. IC, TLC29321PW Pin No. Pin Name Description 1 vb ‘Powersupply terminal to the intemal logic circuit > ae ‘¥CO output frequency divide-by-2 divider select terminal. ‘The VCO output fequency can be divided by 2 and outpat as this terminal i controlled by external logic. 3 ed ‘¥CO output terminal. Goes to low level during inhibit. 2 inpot terminal for edge difference datetion between the reference frequency (REF- 4s ANAT |N) and the frequency from extemal counter. "The AREF-IN is input othe FINA terminal normally, and the divided or multiplied frequency from external counter is ngut othe FIN-B termina. 6 PEDO PPD output terminal 7 ‘GND Tniernal logic circuit GND terminal. 8 NC NG 8 FDI PED inhibit function control terminal 10 cour ‘¥CO inhibit function control terminal. ul AGND CO GND, 2 veo! '¥CO contol voltage input. The VCO escillator control voltage is input from an external low-pass fle to form PLL. Extemal resistor is connected to this terminal for setting the VCO oscillation Bb Blas frequency. A bias resistor is connected between this terminal and power supply line to supply bias fr intemal VCO oscillation and for setting and adjusting the oscillating frequency. 14 AYDD '¥CO power supply voltage terminalIC, HD49307 Pin No. Pin No. Description 15 G8 Digital input terminal. 6 BI NC. 7 NC Digital input terminal. sR B2~B6 Digital input terminal B15 NC NC. 16,17 87, BS Digital input terminal 18 NC NC 19 RCLK IK channel clock input. 20 GCLK G channel clock input 21 BCLK B channel clock input. 2 Dvss Digital GND. 2B vpD Digital power supply. a NC N.C. 25 cau External phase compensation capacitance connection terminal 26 cB [Bypass capacitance connection terminal 2~D NC N.C. 30 VRREF Reference voltage input termina. 31 VSS. ‘Analog GND. 32 ‘AYDD Analog power supply. 3 BouT BB channel analog signal output terminal ‘AVDD ‘Analog power supply 35 NC N.C. 36 cour G channel analog signal ourput terminal 7 ‘AVDD ‘Analog power supply. 38 ROUT R channel analog signal output terminal, Ey ASS. ‘Analog GND. 40 ‘AVDD ‘Analog power supply. 41 VDD Digital power supply 2 RI Digital input terminal, aaa NC NC. 45~51 RO~RB Digital input terminal 254 Gi~@ Digital input terminal. 55,56 NC NC. 78IC, wPD61010 Pin No, PinName vO Description 1 p> — | +5 V power supply. 26 HD9~5) VO | Hostdata bus. 1 i) — | 45V power supply. 8 GND) — | op. ~13 HDs~0 VO | Host data bos. 4 vpp = |_ +5 V power supply. 15 ‘GND, — |_ ono. 16 ‘DRE © | DMA request signal 7 ‘ACK 1_| DMA acknowledge signal 18 SEL 1_[ Signal to select the host CPU access method. 9 DRQ 1 _| Data input request for bitstream input from CD-ROM decoder. 20 pp = | +5 V power supply. 2 GND, — | ono. » = fo | Da inpoc sponse for bitstream input from CD-ROM decoder, of DMA input request for code input. 2 ‘DED | Bitstream input approval signal. 24,25 NC — [Ne 26~33 cD0~7, 1._| Data bus for bit stream input from CD-ROM decoder. 4 bp — | SV power supply. 35 ‘GND — | ono. 36~39 MD7~4 WO | DRAM data bus 40 vpp — | +5 V power supply. 41,42 GND — |_onp. B~46 MD3~0 VO | DRAM data bus 47,48 MDIS, 14 WO | DRAM data bus 0 yop. — | +5V power supply. EY GND — | xp. 51~36 MDI3~8 vO | DRAM data bus. 37 yop = | +5 V power supply. 38 GND — | ono. 59~64 MA0~5, © | DRAM address bus. 6 yop — | 45 V power supply. 665, ‘GND. — | ono. 1-0 MAG~8: © | DRAM address bus. 0 RAST. © | DRAM RAS signal. 7 RASO, © | _DRAMRAS signal, R CAS © | DRAMCAS signal. B oD, = _|_+5-Vpower supply. 4 WE © | Write enable ty DRAM. 3s~71 NC — [xe 18 OE 1] Video data ouput enable, 79Pin No. Pin Name vO Description 79,80 GND — [_ann. 8 yop — | +8 V power supply. 2 NC — [xe 3 FLDI 1_| Field signa (od/even) 4 HDI 1_[_ Horizontal syne signal 85 VDI 1 _Venical syne signal 86 YDCLK 1_[__ Video data output clock (13.5 MHZ). 7 co) — | _+5V power supply. se~o1 | vDATA2~20 | 0 | Video data ouput bus 2 ‘GND, — | eno) 3 DD, — | 45 V power supply. os~97 | vpaTato~16 | 0 | Video data output bus. 98,99 VDATAIS, 14 | © | Video data output bus 109 yop — | +5V power supply. 101 GND — | ann. 102~105 | VDATAIS~10 | © | Video data output bus 106 vp — | 48 power supply. 107 GND, — | ono. tos~112 | _VDATA9~S | © | Video data output bus 113 VoD — | +5V power supply. na GND, — | ono. us~19 [| voaTas~o | 0 | Video data output bus. 120 i) — | 45 Vpower supply. 121, 122, GND — | ono. 123 bo © | Video data outpot bus. 124 BCK © | Video data outpat clock. 125 LRCK © | LR channel identification signal. 126 ‘MCLK © | Audio master clock. 127 NC — [ne 128 AUCLK 1 _[Imemat audio decoder system clock, 129 ry) — | +5 Vpower supply. 130~ 132 NC — [xe 13 cc) = | +5V power supply. 134 “RESET 1 [_ Reset signal. 135 CuK 1_| _ System clock (27 MHz) 136 ‘GND — | np. 137 DS 1 | Data suobe signal 138 RW 1_[_Read/write select, 139 S 1 | Chip select 140~ 145 HADRO~S 1 | Host address bus 146, 147 GND — [_onp.Pino PiaName | WO Description 168 INT (© | _Tnerrpe sana 149) HDAK co Bus cycle response signal. 150 yoo) = | 45 V power supply 151 ‘GND — | eno. 152157 | HDIS~10__| WO | Hostdaa bus 158 yoo — | 45 V power supp 159, 160 ‘GND = | eno. IC, wPD632106T PiaNo Pin Name Description H SEL T_| Test selection input 2 RST 1_| Reset input 3 xTO © | External etal oscilatoris connected to this pin a xt _| Excel etl osiltor is connected otis pin 5 MCKO © _| Master clock ouput 6 cKSEL 1_| Chock stection input 7 ck 1_| Bit coek input = si 1_| Daca inpat 9 LRCK T | ER clock input 0 DEFSI 1_| _Deemphasis selection input 1. u DEFS2 I Deemphasis selection input 2 12 DSEL I Double speed playback selection input. B SMUTE T_| Soft mut selection input if BSEL T_| Data it length selection ipa 15 GND — | Dita Gn, 16 ‘GND = | Analog GND. 7 RO. (© | BVA convener output (channel, 8 AOR (© _| Fitter amplifier ouput ( channel). 9 ANIR _| iter amplifier input chan. 20 APIR 1_| Fier amplifier input channe. 21 REF — | Reference ® chamed. 2 LREF — | Reference (L chan. B PIL 1_| Fier amplifier (9) impu L channed) 6 ANIL i 35 AOL (© | Fiterampliier output (Lchanne 26 10 © | DIA converter output (channel 2 ‘AVDD =| Anatog power suppiy. 28 DvDD =| Distal power supply. atIC, TC170C100AF Pin No. Pin Name vo Description <5 YINI=0 1_| _Ysignal from MPEG chip. 6 GND — | ono. m4 uIN7~0 1_[__Usignal from MPEG chip. Is GND — | ono. 16,17 VIN7.6 1_[__V signa from MPEG chip. 18 vec = _|_ Power supply terminal 19~24 VINS~0 1_[__V signal from MPEG chip. 25 ‘GND, — | ono. 26 FLDO © | _Odedieven signal ourput ofa field 27 DO © | _HSYNC signal wo MPEG chip. 28 ‘DO © | _VSYNC signal to MPEG chip. » PCP, © | Clamp signal output. 30 ‘CBLK © | _ Blanking signal output (used depending upon type of DAC). 31 ‘GND, — | ono. 2 FSC, © | Sub carrier output (Divided-by-four of NTSC: 1431818 MHz, PAL: 17.734475 MHz), 3 eGMPEG | 0 | CD-GorMPEG play selector signal to external RGB video selector, 4 ‘TESTO 1 | Operation mode setting terminal. 35 ‘GND, — | ono. 36 135M © | 13.5 MHz output. 37 ‘ND, — | ono. 3843 ROUTI~2 |__| YMRsignal output (Output format can be selectable in Y/R). “4 ‘GND — | ano. 45,46 ROUTI,O © | _¥iR signal output (Output format can be selectable in Y/R). 41~54 GouTr~o | 0 | WG signal output (Output format can be selectable in VIG). 3 vec — | Power supply terminal, 56~ 68 BOUTT~0 | © | WB signal outpot (Output format can be selectable in V/B), of ‘GND, — | on. 6 2M 1 [27 Miz input 6 ‘Testi 1_| Operation mode siting terminal oa SHSYNC © _| Comparison clock for PLL synchronizing CLK. 6 MHSYNC (| Reference clock for PLL synchronizing CLK. o vec = _|_ Power supply terminal 0 sci 1_| 1431818 Metz input por (crystal oscillation) when supporting NTSC. 1 oscz © | _NTSC:14.31818 MHz crystal oscillation output terminal RB GND — | onp. “ oscs 1_[ _17.734475 MHz input por (crystal oscillation) when supporting PAL. 5 osc | 17:734475 Miz erystal oscillation output terminal. 16 vee — _|_ Power supply terminal 78 ‘TEST2,3 1_[ Operation mode setting terminal p FMOD 1_[__FLD0 output HL inversion selection signal. 80 PMOD 1_[__ PCP output HL inversion selection signal. 82Fano | PaNane [00] Deception 81 exp — | oN. 2=85 | Tis | 1 | RAM dun inpt terminals 15-12 during RAM check ‘OUT port emia 3-0 des 4), RAM datainpu erminals 118 daring BAM 86, ‘THOP3 vo Lad c : dos : | check. ‘OUT port erminals 3-O adress 4, RAM daa inp terminals 118 ding RAM 87 TIOOP2, vo booed : a be . beck ‘OUT pot erminal 3-0 adres). RAM daa input trials 118 ding RAM beck ‘OUT pot terminals 3 -O adress), RAM dainp terminals 11-8 during RAM 89 ‘TSOPO vo a . ed . check, 30 vee — | Power sappy min 31 GHSYNC | _1 | _HSYNC sina tom CDG decoder 2 ‘GVSYNC | _1_| _VSYNC signa om CDG decoer 93. GCSYNT I CSYNC signal from CD-G decoder. 38 oxo | — | ono. 35-98 4 TRAM data iepatrmia 7 -daing BAM Sho TN pot terminal 3 (adress 5), RAM data input rmial 3 -O dung RAM 9 ‘T3IP3 1 a : 2 a nd check, TN pow erminals 30 fades 5). RAM da inp erinals 30 ding RAM 100 ‘T2P2 1 aa Ms 2 a a check TN port erinals 3-0 ads 3), RAM daa input erinals 3-0 ding RAM | 101 Tut 1 po ‘ : a check [pont texminls = dress), RAM data input rials 3-O daring RAM 102 rors | per z ms a check 103 ox —Tewo, 108 se © | 04 NTSC: 1431816 Mile PAL 1775075 Mi ater ouput 105 GND = [eno, Chip enable signa for checking intemal RAM and ROM check. (Fedo low 106 Race | ermal). Read writ sgal for checking itenal RAM and ROM check, (Fixed low 107 raww | | | sormaty 108 xn [x2 input sed for HYNC DL dl, 108 xD — [exo no er |Top poof ies ipa rm GND — Teno, m2 PALNTSE | 1 | PALATSCmiccorpon 13 HSYNCIN [0 | loved ouput of FYNSCIN 4 HSYNCIN I SYNC signal from VST (only when supporting FMV engine). is_[__-WSYNCIN” | 1_| _VSYNC trom VSC. ony when spporing FMV engin) 16 GND GND, | i718 [70 | v0 | CPU cams inaPin No. Pin Name vO Description 125 vec — | Power supply terminal 126 ‘MOD 1_[_ CLBK output HL inversion selection signal 127 voD. 1_| Video output cisabie, 18 veo/FMV 1_[_ VIDEO CDIDMY engine selection port 129 ws 1 Chip select signal 130 ‘RDILDS, 1_[_ READ signal from CPURD (when supporting H8). LD (when supporting 680009). 13 WRRW 1_| WRITE signal from CPU WR (when supporting H8). R/W (when supporting 680009). 132134 A2~0 1 | Address signal from CPU. 135 86 1_| CPU H8-325/68000 selection port. 136 ‘GND, — | ono. 137 HSYNCO © | Horizontal syne output 138 ‘VSYNCO © | Vertical syne output 139 ‘CSYNCO ‘© | _ Composite syne output. CSYNC signal from video encoder. 13.5 MHz { | selection of SYNC signal output. Selection is possible atthe final uo son | 88° of HDO, VDO, HSYNCO, VSYNCO, CSYNCO, SHYNC, PCP, CBLK, FLDO. (However, HSYNCO, VSYNCO, CSYNCO ate supported during SYNC output of the CDG decoder) 141 vec — _|_ Power supply terminal. a= 148 YIN7~S 1_|_Y¥ signal from MPEG chip.IC, MB89627 Pin No, PinName | U0 Description 1 CCLK (©_| _S8b, DSP Contol Clock 2 DATA, (© | Sb, DSP Control Data 3 SENS 1_| SSP, DSP Stats. 4 XLAT (© | SSP, DSP Command Latch. 3 XRST (© | _ SSP, DSP Reset 6 TyMSW (© | OFFINTSCIPAL/PALSO/PAL AUTO/AUTOVTEST. *NOTE 7 DMUTE © | Digital Mure 8 AMUTE © | Analog Mute, 9 LDON (© | Servo PCB Power on. 10 ‘vepRsT © | Video CD Reset ny OPTON © | Optical Digital Output ON. 2 voc — | AD Convener VEC. 8 voc —_|_AlD Convener VREF. 4 vss — | Ap Convener vss. 15 HOSTIRQ | Host CPU Interupt Request. 16 SCOR 1_ | Subeode Syne0. (Subeode IRQ) n 1s 1 | IaterLimit Switch 18 YCDIRQ 1_| Video Cb Decoder Interupt Request. 9 NC 1 | Notused. 20 RST 1 | CPUReset 2 MODEO 1_| CPU MODE. (Pll-down) 2 MODE! 1_| CPU MODE. (Pull-down) B CLKIN © | sete System Cock. 4 cLKOUT 1_ | sMiz System Clock. 25 ss — | eno. 26 ALE (© | Address Latch Strobe. 2 RD (© | Data Read Strobe. 2% wR (© | Data Write Strobe. 2 CuK © | Clock out 30 READY 1_ | Video CD Decoder Ready 31 osbes © | ospcEnabie 322 ‘OSDCLK (© | OsDCData Clock 3 ‘OSDSIN © | ospcDaa saat ASMAIS © | Address Bus 815 a9 ‘ADO~AD? | VO | AddresyData Bus 0~7 30 vss — | enn. 3 veorcns | _0 | Video CD/CDG Switch. 32 HOLK 1 | Hos CPU Control Clock. 33 ST (© | Host CPU Control Send Data st RT 1 | Hos CPU Contol Reseive Data 35 "TRACK 1_ | Travase Counter.PinNo. | _PinName WO. a Description 56 ENCRST. © | Video Encoder Reset. __ ‘7 Dyce — | pvec. : - Loss PALPAL6) | O | PALPALGOSwitch 9 XNTSC 0 | PALINTSC Switch 7 © | SOCK | 0 | subcode QRead Clock él $950 1_ | Subcode @ Serial Data - @ BUSY WO | Host CPU UF Busy Signal. 8 FOK 1_| Focus Servo OK Detet. 64 Grs 1 | Frame Syne Detect, Note Analog input (TVMSW: 6 pin) of the microprocessor is divided into 7, then controlled. ‘The output are the command setting (Set Video Format) to the two ports of PAL/PAL60 (58 pin), XNTSC (59 pin) and 1301 (CL484), ies) DISC eco Pa 3 THMSW Goin) | DSCRROIE Loy csrarmagy | PAPAL ] ANRC Vauiyy | Mode sysem cssrion | 9 pin) Sp OFF = __| Noroied @FFSC opt mode Fase NISC = NISC H : NISC 39s PAL : PAL 8 H PAL. ce : 4 4 PALA . PALGO L u NISC L { : a NTSC PAL60 L H NTSC PAL AUTO - PAL PAL. 5 # PAL 128 NTSC NTSC H L NTSC Avro i PAL. PAL o | oH PAL Fos Test — [Forse cri asnient (TSC ouput made F000 “4 2 8 As to identification of the disc encoding system, itis identified from the V_SIZE (1A h/word) of the MPEG data, “For servo circuit adjustment” is the process during adjustment (when variable resistor is operated by service engineer) that the microprocessor enters the emergency process routine if the servo system goes extremely out of the servo range. {In addition to the above, ENCRST (56 pin) isthe reset signal for TV encoder, issues the active “L” pulse when each of the input port of CDGSW, NTB, CVSY, HSY, PIXCLK, GCLK, PAL6OB and VCLK of IC401 (BUL417AK) has changed as follows: @ When the power is supplied to the circuit boards of the CD block, ® When starting to reach TOC ® The modes have changed as follows: + TYMSW is switched. ‘+ Switching of encoding system owing to exchange of video CD dise + Exchange of video CD disc with the CD-DA or CD-G. 86IC, CL484 Pin No, PinName | WO) Description 1 HSEL2 1 | Host address bas 2 Ds 1 | Daa stobe, 3 RW 1 | Readrwrte 4 CALEVEL | | Coded data FIFO love status. Open dain, 5 “ACK © | Host data acknowledge. Open dain. 6 DO WO | Host data bus 7 yoD3 =| Power supply pin. Used in 33 V. 89 HDI.HD2 | WO | Host data bus. 10 vss — [_eno. 115 Hps~HD7 | vo | Hos daabus. 16 vss — | ono. n “TEST 1_ | Testterminal, Normally fixed to High 18 vss. — | ono. 9 XILIN| 1_| Global clock 405 Mite 20 XTLOUT © | Global cock. 40:5 Mile. 2,2 ‘ypp3 —_| Power supply pin. Used in 3.3 V. 2~28 MDO~MDS | UO | Memory data bus 2 vDD3 —_| Power supply pin. Used in 3.3 V. 30,31 MD6,MD7_| UO | Memory data bus 32.33 | -mceo-mcer_[ 0 | Chipenable 3437 | Mps~Mpi1__| vo | Memory data bus 38 vss — | oxo. zo~2_ | Mpiz=Mpis__ | vo | Memory databus 8 YDDMAX | — | Powersupply pin. Usedin 5.0V. “4 -Lcas (© | Lower digit, column address strobe. 45 -LCASIN 1_| Lower digit, data latch enable. 46 vss — | oxo. a7 -MWE © | Weiteenabe. 8 “UCAS © | Higher digit, column address strobe. 0 VDp3 —_| Power supply pin, Used in 33 V. 50 JUCASIN 1_| Higher dai, dat'aeh enable, 31,52 RASORASI | O. | Loweraddres strobe, 53-57 MAS=MAS |_| Memory address bus, 38 vss — | ono. 968 MASMAO__|_O | Memory address bus 6 RESERVED | — | Resened 6 vpp3 — | Power supply pin. Usedin 3.3 V. oR, voo~vps | 0 | Pixel data bus. RGB or YCbCr format. B vss — | on. 176 VbT=Vb9 | © | Pixel data bus. RGB or YCBCr fox, 7 yobs — | Power supply pin. Used in3.3 V 7Pin No. PinNeme | ‘0 Description 78-80 | VDIO=VDI2_| © | Pixel databus. RGB or ¥CRCr form: a yobs —_| Power supply pin. Usedin 33 V so~st_ | vis~vpis | 0 | Pixel databus. RGB or YCHC format. 35 vss. — | enn. so-so | voie~vpi9 |__| Pixel databus. RGB or YCBCr format 90 vss — | no. 91-9 | _vp20~vp23 | 0 | Pixel databus. RGB or YCbCr format. 95 key ‘> Normal playback FOCUS SERVO/TRACKING SERVO. ‘© Focus search is continued if TOC] CLV SERVOJSLED SERVO No3 cannot be read *NOTE1 | Check POK/FZC “Traverse mode ‘© During normal dsc playback "TRACKING SERVO ON/OFF Press once; tracking servo OFF ‘Tracking balance (traverse) adjustment Press ewice; tracking servo ON Nos. | = NOTE2 Sted mode | KA key | AllJampstight | ® Pickup moves to the outermost ack | SLED SERVO » ‘© Pickup moves tothe innermost track | Check SLED mechanism operation *=NOTE3 (During playback, machine operates Nos normally.) * NOTE I: There are cases when the tracking servo cannot be locked owing to the protection circuit being operated when heat builds up in the driver IC ifthe focus search is operated continually for more than 10 minutes. In these cases the power supply should be ‘switched off for 10 minutes until eat has been reduced and then re-started. * NOTE 2: Do nat press the 44 or Db keys when the machine is in the [I stats is ative. If they are pressed, playback will not be possible after the If status has been canceled, Ifthe €or Db] keys are pressed inthe IH status, press the Ml Key and return to the start mode (No.1). = NOTE 3: When pressing the [4 or DH Keys take care to avoid damage tothe gears. Because the sled motor is activated when the €or DPI Keys are pressed, even when the pick-up is atthe outermost or innermost wack, 4, Operation Outline ‘The operation of each mode is catied out in the direction ofthe arrows from the tart mode as indicated in the following illustration, Fs Seach node | {5} > fy mate No.1 I) San mole ®) (ans gatap) ‘Sled mode it w[__ Traverse mode Ifthe DISC DIRECT PLAY button is presse, the machine performs the same operation asthe PLAY button is pressed as shown. If the tray is opened by pressing OPEN/CLOSE button during Play mode or Traverse mode, the machine returns tothe Stat mode. a1ELECTRICAL ADJUSTMENT B] CD MECHA C.B 92Note: Connect a probe (10: 1) ofthe oscilloscope or the frequency counter toa test point. 1. Focus Bias Adjustment Make the focus bias adjustment when replacing and repairing the optical block, Oscilloscope (DC range) Rg TPL (RF) e+ ‘TP2 (VREF)o————1 6 1). Connect an oscilloscope to test points TP (RF) and TP2 (REP), 2) Tum on the power switch. 3) Insert test dise TCD-782 (YEDS-18) and play back the second composition 4) Adjust SFRIOI so that RF signal of test point TP (RF) is MAX and CLEARREST. MAX 14 = 0.1 Vpp —— ov EYE PATTERN must he CLEAR and MAX VOLT/DIV : S0mV TIMEPDIV : 05uS [Note:The current ofthe laser signal can be checked withthe voltages on both sides of R127 (100). The difference for the specified value shown on the lavel must be within: 6.0m. KSS.2138 50.2mA 18553 KAS‘ Voltage across R127 Laser current p= Voltage ross R127 _ 108 93 2 2 4 5) 6 ‘Tracking Balance Adjustment Oscilloscope (DC range) [Fa] ‘1P3 (TE)o | + ‘TP2 (VREF) ‘Conneet an oscilloscope to test points TP3 (TE) and TP2 (VRER), ‘Tum on the power switeh, Insert test dise TCD-782 (YEDS-18) and press the PLAY button. ‘Adjust SFR103 to decrease the tracking gai. ‘Adjust SFR1O2 so thatthe waveform on the oscilloscope is vertically symmetrical as shown in the figure below. “After the adjustment is completed, remove the connected lead wires from the terminals 0 VREF VOLT/DIV :20mV TIMEDIV | ims ‘Tracking Gain Adjustment ‘A servo analyzer is necessary in order to perform this, adjustment exacily. However, this gain has a margin, so even if itis slighty of, there is no problem. Therfore, do not perform this adjustment. FFocusytracking gain determines the pick-up follow-up {vertical and horizontal) relative to mechanical noise and ‘mechanical shock when 2-axis device operates. However, as these reciprocate, the adjustment is a the point where both are satisfied,© ‘When gain is ase, the noise ineeases whe the 2-axis device operates. © When gains lowered, tis more susceptible to ‘mechanical shock and skipping occurs more easily ‘When the gain adjustment is of, the symptoms below appear. Gain — (Focus) | Tracking 1) Keep the set horizontal (Ifthe set is not kept horizontally, this adjustment cannot be performed due to the gravity ‘against the 2-axis device.) 2) Insert test disc TCD-782 (YEDS-18) and play back the second composition. 3) Connect an oscilloscope to TPS (TE), TP2 (VREF) ofthe CD MECHA C.B. 4) Adjust SFR10B so thatthe waveform appears as shown inthe figure below. (racking gain adjustment) [@ The time until music stans becomes longer for STOP | PPLAY or automatic low selection (144, Dp buttons pressed.) (Normally takes about 2 seconds.) low or high (© “Music does not start and dise continues to rotate for STOP “+P PLAY or automatic - low selection (144, pp buttons pressed.) (© Disc sops orotate shortly after STOP-*P PLAY. orien | ce (© Sound is interrupted during PLAY. Or time counter low display stops. [@ More noises during the 2-axis device operation oe heh ‘The following is simple adjustment method, ‘Simple adjustment — Note: Since the exact adjustment cannot be pesformesd, remember the positions ofthe controls before the performing the adjustment, Ifthe positions after the simple adjustment are only a litle different, return the controls tothe original position, Procedure: Oscilloscope (DC range) 13 (TE) e ‘72 (VREF)e | VREF ov VOLT/DIV: 50mV TIMEDIV: Im © Incorrect example Low tacking gain ‘The fundamental wave appears as compared with he waveform, adjusted. VREF ov VOLTDIV: 50 mv TIMEDIV: 1S. High racking gain The frequency of the fundamental wave gain igher than that in low _VREF ov VOLT/DIV: 50mVv TIME/DIV: imsMECHANICAL EXPLODED VIEW 1/1 3CD.C.B WAIN WoO C.B CO MECHA C.BMECHANICAL PARTS LIST 1/1 [DESCRIPTION CHIR C ¥ & WAHlE “REFERENCE NAME LIST” @ BHT <7 If can't understand for Description please kindly refer to "REFERENCE NAME LIST’ EEN. PARTI a cesonenon EF.NO._PARTNO wa DesonPnon . We 2 86-261-235-11 PULL, KOR W 20 G4-261-206-118 ean, nena 2 eL-ol-212-01k POLLY, LOAD > 21 Bl-zgi-219-019 FULLY, AELAY BOE 3 si-zei-239-019S-sckig TP 22 e4-201-221-019 GEAR, moN TT 4 etoagi-251-019 Gee TRAY RetaY 103 25 64-2Gi-258-01R Genk, HORM WE 5 Siozei-271-018 SySCHE HRC REAR 24 pecaGl-224-018 Leva tT 6 ei-zol-277-219 moe, anaue » 25 b4-201-225-010 eur, s01.0-63.3 7 ei-z0i-255-119 PLATR, MACY MR 26 67-036-326-010 MAGNET, CLAP 93, 8,2, KH VS> 8 e-ae-213-019 La, si 35 G3.258-g02-010 Ran aAGevSE, vaI> 3 s6-2G1-003-219 TRAY NO2-B 2 eo-cos-218-019 GUSH CO A 10 BI-GUS-S64-018 Moto, (acaBaLe) 28 64-2G1-248-019 SPR-c, KOR HL S4-g01-005-119roRanLE.not 29 B2-DML-220-019 SPACER, DIA 3.6-8-0.24eV319 42 Be-zoi-030-019 —1wp,cD neV3E, Utne ‘A 87-067-703-018 BYEDV3-10 (W/O SLORI axCRET > 12 B4-aeL-0L1-019 RaPLBCTOR, COCA, B,2,V5> 587-251-0704 O62.6-3 13 ad-agi-2i2-119 He sew 02 © e7-342-096-219 | UA2UD-BeVIL, VEL, VE 14 e4-acl-208-019 Laven, cue D 87-067-579-019 BYE 2e5-8 W/O SLORSL, iL 1S 2¢-201-209-010 apn, 5Q2.8-117.7. 2 en-s57-590-010 urmeg-5 cvrmeeuiL> 16 B4-zol-21-018Spe-t cas F 87-067-767-019 eyET¥2.6-6cV3L> YP 84-261-235-219 GERR,SRIN CaM BUS G 89-067-058-018 1a B4-261-216-219 SLIDE, MECHA CAM YEL 19 B4-zl-205-19 Geng, Hae 96CD MECHANISM EXPLODED VIEW 1 / 1 (8ZG-2 C5N ) CD MECHANISM PARTS LIST 1 / 1 (8ZG-2 C5N ) DESCRIPTION CHF © & O41 “REFERENCE NAME LIST” SMUT (HSU, If can't understand for Description please kindly refer to “REFERENCE NAME LIST". ENO. PARTI, wa esornon EF.NO_PARTNO, ro) No, 6, 1 83-202-202-71K o-suer § ASST. 6 ar-070-445-010 2 §3-202-208-419 GEAR. 8 gscren- 22-00 3g: 213 GEAR, A a7-261-032-219, 4 0-01 GEAR MOTOR 2 5 35-262-200-119 Suny, SLIDE 97 ‘esoRPTION ProK- UP, KSS-2138, a ScHEN 12-3CD MECHANISM EXPLODED VIEW 1 / 1 (3ZG-2 C1N ) CD MECHANISM PARTS LIST 1 / 1 (3ZG-2 C1N ) DESCRIPTION CHiif © VW ik “REFERENCE NAME LIST @8RL< (HEU, If can’t understand for Description please kindly refer to "REFERENCE NAME LIST”. EF.NO PARTNO. ro ‘eSoRPTON EF.NO_ PART, ro DESORPTION ra 0. 1 3-202-202-71K onseRT § assv.s 6 sr-0T0-445-o10 prcK-uP, 455-2138 2 83-202-200-019 GeARA B g3-702-233-019 TUN MLB, AS ae ERR. 9 m1-065-358-019 SOTA 4 (Gean' nono 2 1b @7-045-396-019 a3 5 SHAFT, SLIDE 7» 67-261-032.219,ELECTRICAL MAIN PARTS LIST 4ZG-1A DESCRIPTION THIF C & @UHIE “REFERENCE NAMELIST” # SNL TCHS 1 can’t understand for Description please kindly refer to "REFERENCE NAME LIST” EF.NO, PARTHO, ie e7-070-284-019 ey-017-745-018, f7-017-266-088 512070-305-018 erongscoea ns 97-017-802-010 87-017-805-010 ‘ansistoR se c.8 cut 02 cies cies 2105 cus at ioe hos ens an cue us ei20 cia east e182 cst esa 15s iss easy else cot) 1s aa case cise ches cuss cies ast as s7-026-239-069 9-110-373-089 83-420-052-083 a5-ant-rz2-388 89-320-011-093, er-026-223-009 sous ae7-089 7-026-608-089 83-406-555-089 97-920-038-000 57-020-465-089 87-020-330-089 e7-n10-184-089 s7-010-160-088 s7-o1e-132-039 87-012 156-098 57-015-638-045 sr-010-60-048 sr-on0-as7-089 7-016-461-088 sr-0i0-i97-088 sr-0i0-310-088 a7-o10-218-089 ar-o1ocis7-088 87-010-260-003 sro ase 72018-2094 7-010-186-089 7-010-186-0889 87-010-136-089 s7-010-404-089 eroan0"19-088 7-030-189-089 ‘010-401-088 0382-088 s7-010-219-088 Eroms-isd-085 s1-110-263-088 7-010-197-089 37-10-195-089 s7-010-197-088 5r-010-92-085, s7-010-97-088 sroaigciso-na8 DESCRIPTION No re,cxaasoang se,cxat78709 revnmassen TevaAsaos Tevraraais 1e,nersTaBco> Te Lea2AGPeOes> come orcas ote, 2681037 5 ‘25020039 121051 1m, 2602172 vu sm, 2sc200zK come, orenssen ‘me 2eui3ter cota.one 123 oe sm, 25005582 cof, 2501385405 rove, 185133 ote, oAP2028 cars 0.000-25 F RPS 1508-80 2 ae, Te-0 0.0116 ¥ che, § 2237-50 ch cap. 6.7250 7 99 FEFNO. PATHOL 29 ESCRPTON 70 e1-010-263-088 caP,e 190-10 sa sun CU wr-o1o-176-083 c-cke,§ 10don-30 72 w7-010-196-089 cuean’s 0,022.25 8 CTS wr-o10ei96-089 cocapls 013-25. care sv-ouocigtong9 cueap’s 001-25 8 6375 s7-010-263-089 caP,E 300-10 awe tt 76 87-010-245-089 Capi a 220-10 Se cam gr-o10-197-009 cvehe,S t.01-25 8 e178 s7-010-260-089 Gaye 47-25 OE 179 wr-o1oei96-089 Ceap,$ 012-28 F ceo er-030-196-089 c-chP,s 01-25 F aol ay-LO-8ia-oss | Goeas 47e-50 Gt cqo2a7-010-318-088 Evean.s #7P-50 ce e203 B7-010-32i-089 Sota S #2P-50 cH 20g s7-010-325-089-eAe,S 92>. 50 GH 20s 67-030-221-089 c-cne,s 829-50 cH 206 w7-010-321-083 GEARY 620-30 Ht e207 §7-032-155-099 Cuenp\$ 1902-30 cH e20B £7-012-153-089 Coeam,$ 1200-30 GH aos ay-L2-185-089 GleaS 120-30 co cei s7-012-188-099 _c-cao,s 1200-50 oF 2a 67-010-405-088 Cape 10-90 Se 212 §7-010-408-009 CRP, 10-50 e213 s7-0i0-186-099 c-che,g {7002-50 2 cals 87-010-186-089 Coca 47002-30 can at-oue-132-089 capa 200-26 11h 232° B7-010-060-049 Capi 100-36 7 CoOL Br-010-196-085 Cnche, 6 0.1625 F 302 sr-010-260-089 apse 47-35 oe S01 s7-0i0-221-03 caD,B 470-10 oe e502 a7-010-197-089 c-car.9 0.01-25 8 503 87-010-263-089 capys 100-10 gi Se11 50¢B7-010-136-089 cnche,8 0,]-25 F 505 87-010-196-085 C-cae,s O.1-28 F 506 67-010-196-089 cueabls 011-28 F cso ar-ni0-196-089 c-cap.s 0.1-25 F 508 87-010-271-049 Gap, 470-10. te 509 B7-00-186-089 Guche, 8 011-25 F e510 s7-110-186-089 C-c4e,§ 011.28 F SLL 87-010-185-008 cueae es S8000-50 B son 97-010-287-089 soe 87-040-361-093 e503 a7-010-196-089 e604 87-010-137-080 rol BT-010-322-088 Cuca 8 100-50 co moa s7-o10-322-089 ¢-cae,s 100p-50 oF ros g7-010-336-055 C-cAp.s 47P-50 cH 704 sr-o10-178-0a9C-cap’s L0ceP-30 8 705 g7-010-178-089 Cuca s Lo0tP-30 8 c2wT-010-982-049 CAP 2 33-25 GAS cto g7-o10-197-088 c-car,s 0.01-25 Bese ce02 87-010-260-085 capyE 47-75 antco> 803 57-010-194-099 Cnche,$ €.047° 25 Peo> coe 7-010-260-0988 Ghove 47-35 meas ©805 BT-018-136-089 caP,TC~U 01-16 Yeas 9808 87-030-260-089 cAR,R 47-25 ste 607 87-010-485-085 cap. 10-50 ames ou0s87-010-197-088 Evehp,5 0.01635 Beo> 09 87-010-405-083 chose 10-50 epee elo wr-010-313-089 CHEAP, 169-80 caco> cain s7-0:0-316-089 c-caP,s 229-50 cHco> cela g7-010-315-069 Goeaels 188-50 cmcee cos sr-010-3i5-069 Eanes 71-50 cHeaefeb MTN. ZY oescRPTON EF.NO, PART, cad 97-010-197-088c-tae, 0.01-25 Beo> sot 97-036-108-019 15 g7-010-260-089 cab, 7-35 cameos sy? #7-036-109-019 e816 H7-010-404-085 CARY 4.750 sos mor 97-030-407-089 car sr-aio-zai-oag Caen {0-10ce> Heol atavueceb2-099 ais 97-010-196-099 P8015 Fea waa a0-rue-s01-099 cay a7-010-321-088 c-cap,s 70-80 cHeo> e820 87-010-178-089 C-caP, 3 1000P~50 Bc~> up cB G21 g7-040-196-489 Cents 8 611-25 Peo> 822 97-010-187-083 CoCAP,S 01-25 Bco> ‘aoro1 67-070-200-089 e301 87-010-260-089 CaP, B' 47-25 SNRed> teoi02 s7-017-350-080 tun0s e7-017-350-080 902 97-010-196-089 c-ca9,$ 0.1-25 Fem» tapos £7-070-200-089 faa cczel-ele-0:9 eck ASSY BP ‘Burdn1 87-003-474-085 F-aHaD, AML BLO2eNDE> S802. £7-003-474-089F-AEAD, aM BLOzANICGD merce Pel es-arI-6 Pr-casis,16P-1.0 coor a7-018-226-009 ret caous, wee 5-21.25, Mot 977045-368-018 ‘Toon 87-009-502-080 Shek, BEN PY BATRCC> redo, a70026. 572-009 Lepgon s7-adQ-i25-019 Lap, Sla-elzan-ot-BeD> NGOL—87-065-305-019 MOTOR, F-50078 RTT 87-022-365-089 C-RAS 8 100K" 1/108 F sor0e .8 278 €-R8S.8 66R-1/100 F v2 ox-262-513-210 id c-RaS)§ ean 1/100 F Pop $1-564-720-110 Riso 67-022-363-009 C-RES,S 668-1/108 F sul 55-872-085-110 RisL —87-022-963-089 CURBS, GOR-L/ION F Risa W7-022-265.083 CuRaS 8 LOOR-A/S00 F RAL 97-022-186-009 coms, 821/60 Bu0337-022-186-089 | C-RES,82-1/49 J SrRisi §7-026-175-089 SER, ATK DIAG Y SPRIS2. e7-024-176.089 SER,IOUK DIAG V SPRISS. §7-024-176-089 SFR, I00K DIAG V ay io, DeSORETION 3%, RSH S05 6 SH, FSH $798 61 344 1a visywmay 7 79mmnecs visyemar 1 Sena ao, suPesee-s-¢-21 wa sei1ss0cx zo, seutssoce ao, suP636e-21-6-01 cate 0 0.3-50 F wotor,(scH88:4) P-BNS8,OPI8530 ‘SUED woven assy commector ea? 5 OF» Tisha /CHIP RESISTOR PART CODE Fo Pith RA— KORY LS Chip Resistor Par Coding f@@-O00 000 goo oo HR waits § Figure ees mer ha eran eae aE co ese Ee SPIE Dimeantona (aay Was F ca oe | fe | ee ee Bod | ee tebe a 1738w 3216, £5% a if 32 [16 [oss 128 Refer to the following pages for the 4ZG-1 and the common sections. IC DESCRIPTION CXAI78280 LC7872E... (MECHANICAL EXPLODED VIEW 1/1 See page 95 MECHANICAL PARTS LIST 1/1 See page 96 See page 64 ‘See page 62 100wywovia HooTeq0 0378) J " ONIUIMso = Ga, 3 028 | wyuovig OLWAaHOSWAVE FORM @ systemcuocx voutry: 2v ‘racking TIMEDIV: Ins IC101 Pin 7 (XTAO) TIME/DIV: 0.18 ‘TP2 (TE) ieee mn vl i i va l LA m ANNAN ; mney | | Jaav FonusSeush ICISI Pin © (FE-0) VOLT/DIV: $00mV TIMEDIV: 05uS el ® teas You DW: 20m ICIS Pin © (FE-O) TIME/DIV: 2mS_ IC BLOCK DIAGRAM IC, TA7291 vee Vrete [e--—=< pan CONTROL CIRCUIT PROTECTOR circuIT 73a) 3) ourz one Mr ne ove ier onPoy t woos ier [ana burr [out ope |e) « | se vf. pet. pe of. pupa | ew ee aie ©: HI IMPEDANCE NOTE : INPUT “HT ACTIVE 107IC DESCRIPTION IC, CXD2508AQ Pin No. Pin name i) Description 1 ‘SCOR (O_| _1H when the subcode syne $0 or SI is detected, 2 SBSO | _SUBP—W serial output 3 EXCK 1_| Clock input for SBSO read out. 4 'sgso © | SUBQ80-bit serial output. 5 SQCK 1_| Clock input for SQSO read out. 6 MUTE 1 | Hromute. L to cancel T SENS | _SENS signal output to CPU. 8 XRST 1_| System reset. L to reset. 9 DATA 1_| Serial data input from CPU. 10 XLAT 1 | Latch input from CPU. Latching serial data at fall down. u CLOK 1_| Clock input from CPU to transfer serial data. 2 vss — | Gxp. 13 SEIN 1_| SENS input from SSP. 4 CNIN 1_| Numbers of track jump are counted and input. 15 DATO © | Serial data output to SSP. 16 XLTO. © | Serial data latched output to SSP. Latched at fall down edge. 7 CLKO. © | Clock input from SSP to transfer serial date. 18,20 SPOA,C 1_| Microprocessor expansion interface. 19 XTSL. 1_ | X’tal selection input terminal. “L” at 16.9344MHz X'tal, “H” at 33,86888MHz, 2 XLON 0 | _ Microprocessor expansion interface. 2B FOK 1_| Focus OK input pin, Used for SENS output and servo auto sequencer. 4 ‘MON 0 | Spindle motor ON/OFF control output 25 MDP © _| Spindle motor servo control output. 26 ‘MDS © | Spindle motor servo control output. 7 oe o | SFSis sampled by 4sriz. 1 ouput when GFS is H. L output when GFS i L for 8 consecutive times. 28 TEST 1_| TEST. (Connected to GND) 29 FILO ©_| Filter output co master PLL. (slave=digital PLL) 30 FILL 1_|__ Filter input to master PLL. 31 PCO. | Charge-pump output to master PLL. 32 bb —_|_ Power supply input. (+5V) 33 AVSSL — | on. 34 LTV 1_| VCO comtroi voltage input to master PLL. 35 AVDDI = _|_ Powersupply input. (+5V) 36 RF 1_ | BEM signal input. 37 BIAS 1 | Constant current input to asymmetry correction circuit 38 ASYL 1 | Comparate voltage input to asymmetry correction circuit 39 ASYO. O_| _EFM full swing output, (L=VSS, H=VDD) 40 ASYE 1_| _Liasymmety correction OFF. H: asymmetry comection ON at wock © _| DIA interface, word clock (2Fs) for 48-bit slot. 42 LRCK © _| DIA interface, LR clock (Fs) for 48-bit slot. 108,Pin No. Pin name vO Description a LRCKI 1_| LR clock input to DAC. (48-bit slot) “4 CMD © | DIA interface, serial data. (2°s complement, MSB first) 5 PCMDI 1_| Audio data input to DAC. (48-bit slot) 46 BCK © | DIA interface, bit clock. a BCKI 1_|Bitclock input to DAC. (48-bit slot) 48 ‘TOP © | GroP ouput 9 XUGF 0 | _XUFG output 30 XPCK © | XPLCK output St rs © | GFS output 32 RFCK © | RFCK output. 33 vss — | ono. 54 (©2P0 © | C2PO ouput 35 XROF © | XRAOF output, 56 MNTS (© | MNTS output 7 MNTI © | MNTI output. 38 MNTO © | MNTO output. 9 FSTT. © | Pins-73 and-74 divided-by 2 output. o cM © | $2336MHz output ol OUT (| Digital Out connector output signal a EMPH (0 | _Hwhen the playback dise has emphasis. L when it does not, a EMPHI 1_| _DACemphasis ON/OFF. H when ON. L when OFF a WrCK (©_| _WFCK (WRITE FRAME CLOCK) output. 65 ‘ZEROL ‘© | _Nosound data detection output. H (L-ch) when no sound data is detected 66 ZEROR ‘0 | _Nosound data detection output. H (R-ch) when no sound daa is detected, a DIS! 1_| TEST for DAC. (Normally “L”) 6 yop — | Power supply input. (+5V) oe NLPWM (0 |_L-ch PWM output. (reversed polarity) 0 LPwM © | Lech PWM output. (normal polarity) 7 AVDD2, — | Power supply input wo L-ch PWM driver. (Connected to +5V) n AVDD3 — | Power supply input to Xtal. (Connected to +5V) B XTAL 1 _| Xtal input to 33.8688MH2 oscillator circuit 4 XTAO 0 | 33.8688MFHz X’ta oscillator circuit output. 5 AVSSI — | GND input io Xtal. Connected GND) 76 AVSS2 = | GND input io PWM driver. (Connected to GND) 7 NRPWM (© | Rech PWM output, (reversed phase) 8 RPWM (© | Rech PWM output. (normal phase) p prs2 1_|_TEST-2 for DAC. (Normally “L”) 80 DTS3 1_ | TEST-3 for DAC. (Normally “L”) 109TEST MODE 1, How to Activate CD Test Mode Insert the AC plug while pressing the function CD button, ALFL display tubes wil light up, ad the test mode will be sctvated, 3, CD Test Mode Functions mode, ‘© Press the funetion button How to Cancel CD Test Mode Either one ofthe following operations will cancel the CD test ‘Press the power switch button. (except CD function button) # Disconnect the AC plug ‘When test mode is activated, the following mode functions from No.1 to No.S can be used by pressing the operation keys, Wak Cpe | FL Apy Open Cone stat mods [asain | Allan ih |» Tetande is aca Taig cick (Al Spl # Laser diode tums aways ON fg AbCeteuitcheck Se meee Laser curtent control. Across & seaccosand ses citer wos Suen Search mode | Mil key © Continual focus search FOCUS SERVO: _ Checkup la eges te fat | © Chek ors ceuch waver [TE = |, snetnsoen maton) * Check ea ener wt L «Rot na echeshta or |" FORE aot mantra he oa tvetan iOminaes "ROTEL | _ sete Payne [ah |p) fe Normal ace FOCUS SERVOMTRACKING SERVO [TT {| tosicnisconmasieroc | CLV SevOISLED SERVO 03 L motions eNorEs | chee FOKIRZC Tenens [Hey |__| © During mal dic pgbck | TRACKING SERVO ONORT | i I Press once; tracking servo OFF ‘Tracking balance (traverse) adjustment oa Press twice; tracking servo ON os sores Sled mode | € key | Alltamps ight | © Pickup moves to the outermost track | SLED SERVO * + Pelupmovertoteemosttack| Check SLED mechanism persion *horE (Duingplptck, mine gee wes vomaly) * NOTE I: Tee ae ca when he ckng ave canot be ke ovng toe pon ct sng opened when eat ul p inthe driver IC ifthe focus search is operated continually for more than 10 minutes. In these eases the power supply should be switebed off for 10 minutes until heat has been reduced and then re-started. * NOTE 2: ‘Do not press the H4 or Db] Keys when the machine is inthe status is active. If they are pressed, playback will nat be possible after the If status has been canceled, If the [4 or DA Keys are pressed in the ff status, press the Ii key and reeurn to the start mode (No.1). * NOTE 3: When pressing the K4 or DH keys, take care to avoid damage to the gears. Because the sled motors activated when the HA or DW keys are pressed, even when the pick-up is at the outermost or innermost track. 4. Operation Outline The operation of each mode is carried out in the direction ofthe arows from the stat mode as indicated in the following illustration No YNe3 Search mode {09} Play mode RQ wt WF Start mode (AIIFLs light up) No.5 | No.4 Sled mode Oy >| Traverse mode If the DISC DIRECT PLAY button is pressed, the machine performs the same operation asthe PLAY button is pressed as shown. If the tray is opened by pressing OPEN/CLOSE button during Play mode or Traverse mode, the machine returns to the Start mode. 110ELECTRICAL ADJUSTMENT [A] 3CD C.B (PATTERN SIDE) Sr C16 Te3 cre) Re seR153 6 |Note: + Connect a probe (10: 1) ofthe oscilloscope or the frequency counter to a test point. + Doring adjustment, connect (S) pin of an oscilloscope to TP2 (VRP, 1. Focus Bias Adjustment “Make the focus bias adjustment when replacing and repairing the optical block, Oscilloscope (@Crange) TPL He "TP2 (VREF) eo} ‘Connect an oscilloscope to test points TPI (RF) and TP2 (VREF). ‘Tum on the power switeh, Insert text dise TCD-782 (YEDS-18) and play back the second composition. ‘Adjust SFRISI so that RF signal of test point TP (RF) is MAX and CLEARREST. 2 3 9 Max eal XXX EEK RXR XRAY) We HOGI) ov EYE PATTERN must be CLEAR and MAX, VOLTDIV: 05 V TIMEDDIV: 0.5uS Note: ‘The curent of the laser signal can be checked with the voltages on both sides of RI67 (100). The difference for the specified value shown on the avel must be ‘within. Oma, ks8-2138 15165 ‘oma scare] Laser canent op = —_YvtHe acr88 R167 108 12 2 2 » 5) ‘Tracking Balance Adjustment Oscilloscope (DC range) 7P3 (TE) | # ‘TP? (VREF) ‘Connect an oscilloscope to test points TPS (TE) and TP2 (REP), ‘Tum on the power switch, Insert test dise TCD-782 (YEDS-18) and press the PLAY Dutton, ‘Adjust SFR1S3 to reduce the tracking gain. ‘Adjust SFRIS2 so that the traverse waveform on an oscilloscope is vertically symmetrical as shown inthe figure | ITs vREF ; ie ‘Tracking Gain Adjustment A servo analyzer is necessary in order to perform this adjustment exactly. However, this gain has a margin, so even if itis slightly off, thee is no problem. Therfore, do not perform this adjustment, Focusfiracking gain determines the pick-up follow-up (vertical and horizontal) relative to mechanical noise and ‘mechanical shock when 2-axis device operates. However, as these reciprocate, the adjustment is atthe point where both are satisfied. ‘When gain is raised, the noise increases when the 2-axis sevice operates. ‘When gain is lowered, itis more susceptible to mechanical shock and skipping occurs more easly ‘When the gnin adjustment is off, che symptoms below appear.Gain] Symptoms | [© The time unl mane wats becomes longer for STOP PLAY or automatic selection (44 PH buttons pressed) (Normally takes about 2 seconds) (© Music doesnot tart and ise continues to rotate for STOP-»PPLAY ot automat section (44 PA boutons pressed) Disc sops to rotate shortly alter STOP» PLAY. }® Sound is interrupted during PLAY, Or time counter display stops [© More noises dung the | _ z-axis device operation (Focus) | Tracking low or high low orhigh high high ‘The following is simple adjustment method. Simple adjustment — Note: Since the exact adjustment cannot be performed, remember the positions of the controls before the performing the adjustment. Ifthe positions after the simple adjustment are only a litle different, return the controls to the original position. Procedure: Oscilloscope (DC range) ‘1P3 (TE) 1+ TP? (VREF) Le 113 1). Keep the set horizontal. (If the set isnot kept horizontally, this adjustment cannot be performed due to the gravity against the 2-axis device.) Insert test disc TCD-782 (YEDS-18) and play back the second composition Connect an oscilloscope to TP3 (TE), TP2 (VREF) of the CD cB. Adjust SFRIS3 so that the waveform appears as shown in the figure below. (tracking gain adjustment) a 2 4 VREF ov. VOLTIDIY: SomV TIMEDIV: ImS Incorrect example Low tracking gain (The fundamental wave appears as compared with the waveform adjusted.) VREF ov YVOLTIDIV: SOmV TIMEDIV: Ins High tracking gain (The frequency of the fundamental wave is higher than that in low gain.) VREF ov VOLTIDIV: SOmV TIMEDIV: Ins.CD MECHANISM EXPLODED VIEW 1 / 1 (KSM-2131BAM ) SPINDLE KOTOR (wa) WOTOR C.8 CD MECHANISM PARTS LIST 1 / 1 (KSM-2131BAM ) [DESCRIPTION CHiih-C 8 % WHE “REFERENCE NAME LIST? £ BRL < if can’t understand for Description please kindly refer to “REFERENCE NAME LIST REE NO PARTNO, wy DESCRIPTION EEN. PARTI, i WoTOR CuRSsIS ASSY iMG comTeR ¢ SPRING CONPRESSICN 114.4ZG-1B ELECTRICAL MAIN PARTS LIST DESCRIPTION CHIN C S GUWIE “REFERENCE NAMELIST” SML << REO. Ii can’t understand for Description please kindly refer to “REFERENCE NAME LIST". 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Fo Fists KOMI (Chip Resistor Part Coding @@-000 ooo Lo wes et evan axa 7 iis EaRE ee “FIE7 Dimensions (im) Wha F oA Wattage Type Tolerance Symbol FUE Form TT WT t | Resistor Code: A vaer—[ ese | A fost in Refer to the following pages for the 4ZG-1 and the common sections. MIC DESCRIPTION LOTE72E ens IE MECHANICAL EXPLODED VIEW 1/1 ‘See page 95 MIMECHANICAL PARTS LIST 1/1 See page 96 MCD MECHANISM EXPLODED VIEW 1/1 See page 114 NCD MECHANISM PARTS LIST 1/1 See page 114 ‘See page 62 116BLOCK DIAGRAM | «oerwe €@°3 @30 [gl @ 2 HOLOW |G 71-7za ke Wyuovid OWWNaHOSWAVE FORM ® SYSTEM CLOCK VOLTIDIV: 2¥ @ Tracking TIME/DIV: ImS IC101 Pin ® (XO) TIMEMDIV: 0.118 PTE) 169344 MHz HAD A at ATA a ieee hy ee | RY aay ° Focus Search ICIS1 Pin B (FSO) ® w VoLT/DW: som TPL RA TIMEDIV: 0518 rm ved ® rea YouTDIv: 200m ICIS1 Pin B (FSO) TIMEDIV: 2m IC BLOCK DIAGRAM Ic, TA7291 vee vat OO Onn es. || —@ our CONTROL CIRCUIT PROTECTOR CiRcuIT 3) our2 so aC 6 INT IN C.) INPUT ourPur none int_[ inz_| our | outa o[o | «| | sto ‘fo fale ow of; fetla cow se 00: HI IMPEDANCE NOTE : INPUT “HT ACTIVE 123IC DESCRIPTION IC, TC9284BF [Pin No. Pin name wo Description 1 ‘GNDA —_[_ DIA converter R-channel analog GND. 2 RO © | Rechannel data postive ouput a a RO (© | Rechannel data inverted output _| 4 VDA — | Did converter power supply. 3 ra (© | _Lechannel data inverted output - 6 Lo. (© | Lechannet data postive ourpt. ~ 7 GNDA —_|_DIA converter L-channel analog GND, : 810 | TesTs~Tests [1 | Testpin. Normally “A or open 1 SBOK (© | Subcode Q data CRCC judament eesult output. Judgment result OK: H | 2 vopp — | Digital power supply. (+5 V) 13 ‘GNDD — [Digital ond. - 1=17_ | BuSO~BUSS | VO | uprocessor interface, data inpuvouput __| ce | wprocessor interface, chip enable signal input. When “L” ; BUS 3~0 are active Buck processor interface clock i PECK PB frame syne ouput. 21 RST 1 | Reset signal input L" at reset. z| 2 SUBSYC (© | Subcode block syne ouput, When sub code is dtecod"H" at SI postion B SUBD © | subcode P—Wouput _ Pn cuck 1_[_ Subcode P—W daa ead clock input, 5 ppp —_ | Digitat power supply. 63 V) _ 26 "GNDD — | Digital Gnb. ‘| a DECT |__| Defect detcetion signal ouput. When defects detected: “VREF", normaly “HIZ" 28 TEL? (© | Tracking gain adjustment analog swith output. "VREF" of “HZ” 2» TELI (© | Tracking gain adjustment analog switch output. “"VREF” oF “Hi —__| 0 Toul fo | Analogswitch ouput for acking srw gain up, Polat in gnp mode nd nocmal mode canbe selected by command, 31 TOUH? (© | Analog switch output for tacking servo gain up. “HZ” for gain-up, normally “VREF" 2 Tuain (© | _TGUH during normal playback. TOUH2: not used Tracking actuator Kick signal output. NKICx and CKICK are used for kick during 3 TKI © | tacking gain adjustment. “VREF" for outermost track."O" for moving toward inner |_ tack, Normally “HiZ" 7 Mow fo | Atalog itch ouput totum ON/OFF the fed sr, “HIZ" tora ON servo, | “VREF to turn OFF servo. 35 TESTI 1_| TEST pin, Normally “H" o open 16 eB | estmtor FWDIBWD direction contol inal ouput"2VREF” for utmost tack | 0" for moving toward inner tack, Normally “HiZ” 37 TEST 1 | TEST pin. Normally “H" or open. a Me buon fo. | Aiiloesitch ouput select gain ofthe disc motor driv cre. "HZ" for CLV servo OFF, “HZ” or “VREF" canbe selected by command 124Pin No, Pin name vo Description ise motor CLV servo AFC signal output, Operation ‘Command DMEC output Motor acceleration | DMFK “2VREP” 3 DMPC ° CLV servo ON DMsv AEC signal (PWM) Motor brake DMBK_ cB CLY servo OFF | DMOFF “VREF 40 DMPC. © | _Dise motor CLV servo APC signal output 41 2VREF = _| Analog power supply. (wice the “VREF" voltage) Servo mode select output. It tums ON/OFF the laser diode (LD) and focus servo, SEL output LD | Foeusservo | __ Operating mode 2 SEL or lalet OFF OFF LD OFF HZ” oN (OFF Focus search we oN ON Focus ON (normal play) a a (o | Foss stustr dive signal ouput daring foes search made. “VDA” to move the lens far from dise. “L” to move the lens loser to disc. Nosmally “HiZ". “ KIC fo | Forusactuator dive signa output during fous adjustment mode-AgVDDAANvo move the lens far from dis. “LL” to move the lens closer to dise, Normally “HiZ”, 45,46 FELI,FEL2 | | Focus gain adjustment analog switch output. °VREF” or “HZ” 4 FEL 1_| Focus eror signal input 48 ‘TESH 1_[ Analog switch input to ack error signal sample-and-hold 9 ‘TEOF © | Focus gain adjustment analog switch output "VREF" when tacking servo off. 50 ‘SBAD 1_[ Sub beam added signal input SL RFRP 1_| RF ripple signal input 2 REF — | Analog power supply. 8 REL 1 | RPsignal input 4 GNDA — | Analog GND. 35 prsc2 (© | Data slice control EFM signal inverted output. a oe ‘9. | Ise signal monitored ouput. EFMO, PLCK or LOCK signals canbe selected by command. Can be muted. (Not used) 7 DISC! © | _ Data slice control EFM signal postive polarity output 8 VDDA. — | Anatog power supply 9 PDCNT 1_|_ PDO output control signal input. "L” to fx to “HZ” forcibly. “H : normal output. 0 PDO (© | _ Phase error signal between EPM and PLCK signals is output. ‘TMAX detected result output. TTMAX detected result TMAX output a TMAX © | | Longer than specified cycle | “L" ‘Shorter than specified cyele | “VREF" Within specified cycle “Hiz” 2 LPEN 1_|__Low-pass filter amplifier inverted inp. 125Pin No. Pin name vO Description a LPFO (0 | _Low-pass filter amplifier output. 4 ‘VCOF (0 | YO fitter output. 6 ‘TESTX 1 | TEST pin, Normally “H” or “L” (Connected to +5 V) 6 HS | Double speed mode output, “HI : normal speed, “L : double speed o ‘GNDD — | Digital GND. a SPDA (© | Processor status signal output COFS, (© | Conection circuit frame clock (7.35 kHz) output woek ‘o| Wordelock (88.2 kHz) output, SUBQ, BUPOV or IPF can be selected by the Luprocessor command, (Not used) 7 CHEK (0 | Channel clock (44.1 kHz) output. “L"for L-channel.“H” for R-channel n BCK | Bitclock (1.4112 MHz) output B ‘AOUT © | Audio data output. (Not used) ” EMPH 0 _| Emphasis ON/OFF select signal. “H” : emphasis ON. “L” for emphasis OFF 15 our. © | DIGITAL SIGNAL output 16 ‘TEST? 1_| TEST pin, Normally “H", 7 VDDx — | _Ceystaloseilator circuit power supply. 78 xt 1_[ External erystal oscillator is connected. (Crystal oscillator frequency 16.9344 MHz) 0 xO | External crystal oscillator is connected. (Crystal oscillator frequency 16.9344 MHz) 80 ‘GNDX = | Crystal oscilator GND. 126IC, TA8191F Pin No. PinName | vO Description 1 | © | Sulbbeam EV amplifier (TA Amp) output tenninal 2 ‘Te 1_| Sub beam I-V amplifier (TA Amp) input terminal. 3 TN 1_| Sub beam I-V amplifier (TA Amp) input terminal Main beam I-V amplifies (FN Amp) input terminal Main beam I-V amplifier (FP Amp) input terminal © | sede npr LD Amp upteial i I Monitor photo diode amplifier (MD Amp) input termi [ [ar empl ever pass int terminal : _ [© _|_ RF amplifier urput erinal | 1 [RF ripple signal generator circuit input terminal - © | Reference voltage output terminal (+2.1 V). (© [RP aioe sgl op ema — oO ‘Scar detection signal output terminal. ~ T [Foss oor lessen pu ina 1 LO [0 | Fea ror apie Ang cup erin is ee [ves | — | Power spy tein. CTABISOR, 5 V, TAGIDIFVGND) 8 TSN [1] Foss apr anptie 5 Anp) evened ase Ip ein r 150. [0 | Foes oupt apie Anp) uel tein | osct {| Bstemal input to contol he ulin power supply o generate focus search signal i comes nhs ominl 2 oo [ow 3B vor] 1] Povernappir emit 3 m4 pMEP [1 | Disemoranptie OM Ang pave slp erin 25 DMEN I Disc motor amplifier (DM Amp) reversed phase input terminal. 2% DMEO || Dic mor ampli (OM Anp) ouput erin 2 DFO | 0 | Discord npr (DMP An uate, Ce wal 8 PYR Drive amplifier reference voltage input terminal. = PAPO Fes ator dive ane MP Amp ou ean Wass). 30 a) Fea mor anplfer FM Amp) open 3 PMEN [1 | [Res maorampifiar FM Anp vend pase opera 2 FMEP | 0 | Restor ample FM Ang) postive pencil 3 FARO | 0 | Fess acuar dive amp AP Anp) ut trminl (Nosed Fy BVO | 1 | 2 RBFampiier 2 V REF Anp) oupu emia | | 35 ‘2VRP 1 2. REF amplifier (2 V REF Amp) positive phase input terminal. | 36 2VRN I 2. REF amplifier (2 V REF Amp) reversed phase input terminal. 3 1520 [0 | Taig sr pti? (5? Ang ouput emi TS2N 1 ‘Tracking servo amplifier 2 (TS2 Amp) reversed phase input terminal. 1S2P | 1] Tracking evo anplfer2 CS Amp) postive se pt emia © 1310 [ | Tecking se mpi CS Amp oem 1287in No. Pin Name Description 41 ‘TSIN “Tracking servo amplifier | (TS1 Amp) reversed phase input terminal. 2 ‘TsiP “Tracking servo amplifier 1 (TS1 Amp) positive phase input terminal 8 Tso. “Tracking output amplifier (TS Amp) output terminal 4 TSN ‘Tracking output amplifier (TS Amp) reversed phase input terminal. 128TEST MODE 1, How to Activate CD Test Mode 2. How to Cancel CD Test Mode Insert the AC plug while pressing the function CD button. Either one ofthe following operations will cancel the CD test AILFL display tubes will light up, and the test mode will be mode, activated, ‘© Press the function button, —_* Press the power switch button (except CD function button) # Disconnect the AC plug 3, CD Test Mode Functions When test mode is activated, the following mode functions from No.1 to No.5 can be used by pressing the operation keys, Maco. | Operation [Fi day Operon Contents Stat mode | Aaivaion | Alllamps igh | © Test mode's activated © FL display check (Al displays Hight) Not | Search mode | Il key | © Laser diode mms always ON. APC circuit check fom ters eens ig ry JE = | Tropic en repent fr an GND) * | CL ‘swing up-down motion.) FOCUS SERVO * Avoid continual searches that last for | Check focus search waveform oie meer + Gheck fous enor waveform eee eseneee (FOK/FZC are not monitored in the Noa *NOTEI | _ search mode} Play mode | <> key © Normal playback FOCUS SERVO/TRACKING SERVO | [ETL | Remgistiscminirroc | cuy seavosiep senvo LLI 1 | cannot be rea. Check FOKIFZC No3 + NOTE | Traverse mode | HD Key * During normal dise payback ‘TRACKING SERVO ON/OFF CTD [| rssomssmcinsero OFF | Trackin anes eave) amen Hse Pres twice; tacking servo ON Noa + NOTE2 Sled mode | 44 key | Alltampstight | * Pickup moves tothe outermost rack | SLED SERVO » ‘© Pickup moves tothe innermost wack | Check SLED mechanism operation * NOTES (During playback, machine operates Nos normaly.) * NOTE I: ‘There are cases when the tracking servo cannot be locked owing to the protection circuit being operated when heat builds up in the driver IC ifthe focus search i operated continually for more than 10 minutes. In these cases the power supply should be switched off for 10 minutes until heat has been reduced and then re-started. * NOTE 2: Do not press the [4 or Dbl keys when the machine is in the If status is active, If they are pressed, playback will not be possible afte the ff status has been canceled. Ifthe [4 or Db| keys are pressed inthe I status, press the Ml Key and return to the start mode (No.1). “NOTE 3: When pressing the I@ or DW keys, take care to avoid damage tothe gears, Because the sled motor is activated when the Kor DP keys are pressed, even when the pick-up is a the outermost or innermost track, 4. Operation Outline The operation of each mode is carried out in the direction ofthe arrows from the start mode as indicated in the following illustration, [Nez SSS ‘Search mode_ |} {9} Play mode No.1 co | ) Start mode ® (AILFLs light up) in No. No.4 Sled mode Ty >| Traverse mode If the DISC DIRECT PLAY button is pressed, the machine performs the same operation asthe PLAY button is pressed as shown. If the tray is opened by pressing OPEN/CLOSE button during Play mode or Traverse mode, the machine returns to the Start mode. 128ELECTRICAL ADJUSTMENT A] 3CD C.B (PATTERN SIDE) "1P2 (TEO) => g@— |< & a Oem Fy TRLRF)Note: + Connect probe (10: 1 of the oscilloscope or the frequency counts to a est poit. + During adjustment, connect (©) pin of an ‘oscilloscope to TP3 (VREF), 1 Focus Bias Adjustment ‘Make the focus bias adjustment when placing and sepaiting the optical block Oscilloscope (DC range). So ———— ‘TP3 (VREF) eo ‘Connect an oscilloscope to test points TPI (RF) and TP3 (REP. ‘Tur on the power switch Insert test dise TCD-782 (YEDS-18) and play back the second program. ‘Adjust SER1S2 so that RF signal of the test point TP2 (RF) is MAX and CLEAREST. 2 3 4 TRON OOOO IY /\uennt CELE Note: The current ofthe laser signal can be checked with the voltages on both sides of R182 (voltage across 100). The difference forthe specified value shown on the label must be within + 6.0mA. KS$-2138 15165 sG442. Voltage across R182 Laser current lop = ie 131 2. Tracking Balance Adjustment Oscilloscope (DC range) ‘TP2 (TEO) e——-}# ‘TP3 (VREF) os 1). Shoe circuit between TP3 (VREF) end TPA. 2) Connect an oscilloscope to test points TP2 (TEO) and TP3 (REP, 3) Turn on the power switch. 4) Insert test dise TCD-782 (YEDS-18) and press the PLAY (D>) button. $5) Adjust SFRISI so thatthe waveform on the oscilloscope is vertically symmetrical as shown in the figure below. 6) Alter the adjustment is completed, remove the connected lead ‘wire from the test point TP3 (VREF) and TP4, REF. YOLTIDIY: 20mV TIMEDIV: 2ms4ZG-1Z ELECTRICAL MAIN PARTS LIST DESCRIPTION CH CS EVE It.can’t understand for Description please kindly refer to "REFERENCE NAME LIST™, EFERENCE NAME LIST” @ BELT (Hav. EF.NO, PARTNO. -920-165-010 froago-164-010| Erootroasa-cas 97-000-305-018 001-982-018 ‘wausistoR so ce ou oa a ae as as ow aa as a oa a ce as cu a 3 a & ry &s o oe Ss ee cL ca ce cs cus a a 30 St cio. cio 97-026-463-009 89-406-555-009 89-320-011-069 87-026-223-089 89-113-167-088 57-026-470-089 7-026608-088 592327125088 67-020-465-089 e7-016-062-008 e7-0i2-1s1-089 7-016-365-089 Eroo1e-oet-088 57-010-596-088 e7-n10-956-088 eronn0-i62-088 Erotis- 365-088, roti0-2)-088 ero0no-i-088 7-012-29-088| Er-016-068)-088 fro010-199-088 er-010-166-089 7-015-694-089 e7-nn0-322-088 rom15-686-088 brotis-67-089 eromno-e4-088 srom10-146-088 sr-a10-166-088 eronn0-at-08s st-ni6-061-085 fro0n0-196-085| e7-010-408-085| s7-010-263-008 eronn0-is1-088 sroan0-401-088 eronn6-46)-088| 0-130-263-005 sr-ate-134-008 Fronu0-263-188 17-015-684-010 Hono-196-085| sr-m10-197-088 140-263-088 7-006-081-098 7-906-061-0889 42) orscRPTON EF.NO, PARTHO. cues o7-12-149-009 0s Br-oLact96-o88 corey aszam es 87-010-196-088 rte, LeTe630E-7 cos 57-010-184-069 cynimassen fing er-0n0"154-088 TOVBASBSIS| ievransis cut 97-010-196-009 G2 er-Lacdeenoes cid s7-0t0-186-009 le e7-10-263-088 aot erro S1e-068 a, 2549838 1) 1m, 2s06558 cana 67-010-318-088 ‘a, 2scz00%K a3, gr-oa-azi-068 cote, orclasre coe 87-010-321-088 ‘a, 28A2318T0 05 g7-010-321-088 20s 87-010-321-088 sa,amncos F mre 123 9% cao #7-010-356-088 (ome, 25027120%«0> 0a 67-10-316-088 09 87-00-326-089 210 g7-010-336-088 Gait sF-o10-ac5-08s rons, 158133 cai #7-010-403-088 Gis gr-o.o-te6-0es cad 87-010-166-088 Cais e7-010-555-088 Cais 87-010-360-089 coca s 0.3036 ae C-cae, Sitp-s0 cH coon e7-010-196-009 Coca, s 0.083-28 8 x 302 #7-010-260-095 coeae,s 11-18 me sot g7-010-221-009 C-eaP, 5 0.047-16 aK e502 ef-o10-497-083 sod 97-00-196-088 co 50s e7-010-196-009 ech 30s g7-010-196-099 cent 507 87-010-196-089 oot 509 gr-010-196-089 sie er-o1oci96-083 cnt con g7-ou0-197-099 caer 02 ar-o10-se1-093 cot 60) gr-0u0-196.083 ae on gr-on0-920-083 moa an-010-322-083 OnE 703 an-010-322-099 OE reg s7-010-322-099 ele, eros sr-oie-a3i-t93 cae, ont er-oaocze0-ta3 902 g7-010-196-183 coe, cae, re asar-ett-in9 cae, Fea ge-ael-etdoais cane, Fes B4-201-630-019 OnE EL g7-o03-102-089 Heoger aT-AMo125-019 one, x ch § got 97-045-583-19 OEE 1 Rua g7-022-945-089 cvck, 8 so. 87-036-108-019 on 8 S002 87-036-108-019 iol s7-030-402-089 cae to cae, E I che, tap €.8 a. che, ammo. 87-070-200-089 tapreg §7-017-350-080 tapres $7-017-350-080 tire 672070200088 192 fy) OSCRPTON Ne, cocap, s 307-50 ct eveans 0.168 F Cmca S 0.1-25 F coca, s 109-50 cH (rear, § 10P-50 oH cvcar,s 0.1025 F fan 2 4.7550 98 coche, § 0.125 F cape 200-103 (coche, § 470-50 cH c-caz.s 472-50 cH e-ca2,§ 829-50 ce c-eaeis a2e-s0 cH Coens, § 628-50 ce C°eae,§ 420-50 8 cae. $ S 5 cabs 3,3-50 OMB coche, 4700280 c-cae,s «7000-50 B Cab.E 100-10 cas ene'e 100-25 Se cvear,s 0.1.25 F cane a7-35 oe CAPE Monto. 1 e-chp.$ 1001-25 B coeae,§ 021-25 F coca, s 0.1.25 & c-onr,§ 001-25 F cons 6.1.25 F CoeaP,S 011-25 F cncnws 611-25 F (eb, €1268-1-BeD> worse (coms, s Luax-t/200 F Si, 2058 $325 8 ‘54 20S $228 61 EB XOaL 16,9388 maz no, $126360-81-8-F1 1p, seuassoce ap, seuass0ce SUPERSAEF.NO. PARTWO. AZ) —_—DESCRETON uot 9 caP_ TCU 01-50 F mot Noro, (ocr3814) PeuoL o19 Ps cPISs: a worer-stera 43 Sn STASO-NNR=019 SK LEAP MSW 17320 mE OF 9 PAYEE I /CHIP RESISTOR PART CODE @®@-OO00 OOO aE =] Re “FEE Dimensions (mm Wis FA a ee Bes 17aw nese 32 [16 [oss Ds Refer to the following pages for the 4ZG-1 and the common sections. MI MECHANICAL EXPLODED VIEW 1/1 See page 95 MMECHANICAL PARTS LIST 1/1 See page 96 193wvwovia xooT8WAVE FORM D _ tcrrrinaoeesy vorrp:osv @) rcp @eseo) VOLT: 100m TIMENDIV: 1s TIMEDIV: ins Raa KX iat to AANA ‘MAX | EDAX XXX ae t ‘WEEE ee ct EYE PATTERN ‘ust be CLEAR and MAX, ® rcurinteao, YoLTDIV: 100m TIME/DIV: ImS ICH Pin @ (SLD) VOLTIDIV: 200mV ; ; TIMEDDIV: 25 coh nei Me vrer L {itt VREF ® cn vinwero VoLTPW: 100m TIMEDIV: Ins “| vrer TT Tee t IC BLOCK DIAGRAM IC, TA7291 vee veer TNPUT cure woe Ty 3) Ve INt IN2 out | ouT2 0 |0 |» | « | sv Led * aon | 0 HL cw Ce conrmou_ciacuiT PROTECTOR Au ee 3) ovr2 cise" x co + Hi THPEDANCE wote 5 INPUT “HT ACTIVE aC S INT NZ eno 198WywOvIO OLLYW3HOSork @°9 37 (@) Q 9 an1ugi¢ ~7 T t T ‘onruinaIC DESCRIPTION IC, LC78630E Pin No. Pin Name vO Description 1 veDo (0 | Varicpitch PLL charge pamp output pin. This pin must be open when not used. 3 po ‘9 | Bitslock playback PLL charge pump output pin during 2 times and 4 times speed ‘This pin must be open when not used 3 PDO1 © | _Bitclock playback PLL. charge pump ouput pin during normal speed. 4 AVS. — | Analog system GND. Normally OV. 3 FR 1_| Anexteral resistor to set builtin VCO frequeney range is connected to this pin, 6 ‘AVDD — | Analog system GND. 7 ISET, 1_| _Anextemal resistor set PDO! and PDO2 output curent is connected to this pin. 8 TAL 1_[__Test input pin with built-in pulldown resistor. 8 EFMO © | _EFM signal output pin. 10 vss — | Digital system GND. Normally OV. ul EFMI 1_| EFM signal input pin 2 ‘Testi 1__| Test input pin with built-in pull-down resistor. 1B cLv+ | Spindte servo control ouput pin, Acceleration when CLV+ is “H" 4 cLy- (© | _ Deceleration when CLV-is “H". 5 = ‘o. | Roush servofpase contol automatic selection monitoring output pin. Rough servo at ‘SH Phase control mode at “L" 16,17 ‘Test2, Tests | 1 | Test input pin with built-in pull-down resistor. 18 Pe VO | _Inpuvoutput por. 19 FL 1_| Tracking detection signal input pin. Schmit input. 20 ‘TEs 1_[ Tracking error signal input pin. Schmitt input. 1 eK fo. | EFM data payback bit clock monitoring pin. 4.3218 MHz when phase is looked ‘during normal speed playback, a = fo | Sy? signel detection ouput pin. When the syne signal detected from the EFM signal agrees with the internally generated syne signal, “H” output. 2 ‘TOFF © | Tracking OFF output pi 4 TOL. (© | Tracking gai selector output pin, Gain is increased at “L”. 25 THLD (| Tracking hold output pin. 26 ‘TEST 1_[ Test input pin with built-in pull-down resistor. 27 p> — | Digital system GND. “Tracking jump output pin. JP+“H” occurs at acceleration during jump toward outside 28,29 P+, JP. © | ordeceterator toward inside. JP. “H” oceurs at acceleration during jump toward inside or deceleration toward outside, 30, 31 SLD+SLD- | © | Sted output pin. Four different level can beset using commands. 322 EMPH (© | Emphasis monitoring output. “H(” indicates that emphasis dise is being played back, 33 PS VO | Inpuvvoutput 4 LRCKO_ © | Digital Alter outpat. LR clock output pin, a pruro ‘o | Disital itr output. LR data output pin, DF is tumed OFF withthe DROFF command 36 DACKO © | Digital fiter output. Bit clock output pin. 37 CONTI © | Output port. 141Pin No. Pin Name v0 Description 38 PODFCK VO | Inpuvoutput por. The DF bit clock input pin during the ani-shock mode. 9 PUDFIN VO | Inpuvouiput por. The DF data input pin during the ani-shock mode. 0 Py vo | 'puoutput port Deemphasis filter ON/OFF selection input pin during the an-shock ‘mode. Deemphass filter ON at“ 41 PADFLR VO | Inpuvoutput por. The DF LR clock input pin during the anti-shock mode, 2 LRSY (© _| For ROMXA + LR clock output pin, 8 cK2 © | For ROMXA « Bit clock output pin. Polarity inversion by the CK2CON command, “ ROMXA | Fer ROMXA- Interpolation data output pn. The un-nterpolated data is output with the ROMXA command. 45 OF © _| For ROMXA + C2 flat output pin. 46 ‘MUTEL © | For bbit DAC + L-channel mute output pin a7 LVDD. —_| For bit DAC + L-channel power supply. 8 LCHP © | ForI-bitDAC+L-channel P output pin. 0 LCHN © |For I-bit DAC L-channel N output pin, EY Lys. — |For 1-bicDAC + Lchannel GND. Normally OV. 31 Xxvss. — | Crystal oscillator GND. Normally 0 V. 52 XOUT © | Anextemal 16.9344 MHz crystal oscillator is connected to this pin. 3 XIN) 1_| 33.8688 MHz crystal oscillator is connected during 4 time speed playback. 4 XxvDD — | costal oscillator GND, 55 RVSS = it DAC + R-channel GND. Normally 0V. 36 RCHN °. iC DAC + R-channel N output pin, 7 RCHP ° {DAC + R-channel P output pi, 38 RVDD = it DAC + R-channel power supply. 9 ‘MUTER °. it DAC + R-channel mute output pin. o ‘SBSY ‘0 | Subcode block syne signal output pin, a EFLG © | Chand C2 error correction monitoring pi, a Pw © | ubcode P, QR, S,T, U, V and W output pin, e sey ‘9 | Subeode fame syne signal output pin. The level falls down when the subcode is in standby. “ seck | Subeode ead clock input pin. Schmitt input. This pin must be connected GND when not used. 65 bout © | Digital ouput pin 66 FSX © | 7.35 kitz syne signal divided from the crystal oscillator is output to this pin, o wRQ © | Subcode Q output standby output pin 8 RWC 1 | Read/write control input pin. o SQouT © | Subcode Q output pin, 70 ‘COIN 1_| Microprocessor command input pin. 7 CCK 1_| _ Command input read clock or subcode read clock input from SQOUT. Schmitt input R RES 1 | Chip reset input pin. This pin goes to “L" once when the main power is tamed on. B ‘TESTE © | Test output pi. ™ conr2 © | Output por. 142Pin No, Pin Name Description 15 eM 169344 MHz crystal output pia. 33.8688 MHz is output during 4 times speed playback, 16 42M. “4.2336 MHz output pin. 7 ‘TESTS “Test input pin with buil-in pull-down resistor. 8 ws Chip select input pin with builtin pull-down resistor. p DERI Defect detection signal input pin. ‘This pin must be connected GND when not used, 80 yeoe YVari-piteh VCO control input pin. This pin must be connected GND when not used, 143,IC, LA9230M Pin No PinName | vO Deseipton i | FIN? rn Photo diode of pickup is connected to this pin. This signal is added to the FINI pin signa to produce the RF signal and subtracted to produce the FE signa 2 FINI 1_| Photo diode of pickups connected to this pin 5 : 1 | Pree ode Fick s comet ths pin. Thi signals brace om the Fin signal to produce the FE signa 4 F 1_| Photo die of pickup is conectd to this pin 3 3 1_|_DC component ofthe TE signals input this pin. 6 TE. 1_| ‘the TE signa gin adjustment resistors connaced between this pin and the TE pin. 7 Te © | The TE signal oupa pin : est 1 | 8 Cisco ers) comparatoringt pin. The TE sg input er passing hough band-pass file 9 Sct T [Shock sense input signal i connected o this in 0 TH 1_| Tracking gin time constan sein in. in TA © | TA amplifier ouput pin be wD. {| Avesta racking pas compenston const const een te TD a VR pins. B D | _Amesteral tracking phase compensation sting pin 4 D 1__| Tracking jump signal kick pulse) ample seing pin. 5 70 (© | Tracking contol signal output pin 16 D © | Focusing contol signa output pin. 7 D. 1_|__A ocesing phase compensation constant is connected betwean the FD and FA pis 6 FA T_|_A focusing phase compensation constant is connected between the FD- and FA pins. 9 Fa. 1L_|__A focusing phase compensation constant is connected betwesn the FA and FE pins 20 re © | FE signa ouput pin 21 re T._|__Anextemal FE signal ginseng ressors connected beween the TE and this pins 2 AGND — | Analog signal GND. B xe ‘©. | _Singe-ended output ofthe CV and CV- pin input signal 28 SPI 1_[__ Shinde ampifierinpa 25 PG 1_|__Anextemal spindle gun in 12 om mode setting resistors connected to this in. x sp {| Aneta pine has compensation ont tgetier withthe SPD ps connsctedt this pin, n SPD (| Spindle conto signal oupat pin 28 SLEQ 1 _|_Sted phase compensation constant is connected to this pin » SUD (©-_| Sid consol signal output pin 30,31 SL, SLe 1L_|_Sied advance signal input pin rom microprocessor 2,33 IP JP 1_| Tracking jump signal input pin from DSP. M ToL | Tracking gain contol signa input pin from DSP. Gain low when TOL ="H 35 TOF 1 _| Tracking off conrol signal input pin from DSP. ‘Tracking of when TGL = TP 36 TES, (© | The TES signal is output from this pinto DSP o A 1 | TIS CHIGH FREQUENCY LEVEL) i wed wo judge wheter the main beam x poston above the bits oF itor 144Pin No. PinName | UO) Description 38 SLOF T_| Sled servo off control input pin. 39,40 v.CV+ 1 | CLV erocsigaal input pin fom DSP. 4 RESM (© | RF oxtput pin 2 RFS. 1_|__ RF gain seting and 37 compensation constant setting pin together with RESM pin. 6 suc | TH#(SLICE LEVEL CONTROL isthe signal which onl he data ie level of the [RE waveform with DSP. The (SLICE LEVEL CONTROL) i from this pin. “4 su 1_| ‘The input signal which controls the data lie level with DSP, is connected this pin 45 DGND = [Digital system GND. 46 NCIFSC] —_|_No connection. (Output pin for focus search smoothing capacity.) 47,48 NC — | No connection @ DEF (© | Disc detect detection outpt pin 0 CLK 1_| Reference clock input pin. ‘The DSP 4.23 MHz i input to this pin 31 a 1L_| Microprocessor command elock input pin 2 DAT 1_| Microprocessor command data input pin 33 ce 1._| _ Microprocessor command chip enable input pin. 3 DRE (0 | @ETECTRF) RF level detection ourpat. 35 NC = [__Noconnecton 56 voce — [servo system and distal system Vcc pin 7 REFL T_ | _A bypass capacitor fr reference voltage is connected to this pin 8 VR (© | Reference voltage output pin 9 LF T_ | _Anexteral ise defect detection constants connected to this pin. o PHL 1__|__Anextemal RF signal peak holding capacitor is connected to this pin 6 BAL 1_ | _Anextemal RF signal bottom holding capacitor is connected o this pin. a LD (© | APC circuit output pin 3 LDS 1_| APC circuit input pin a voc! — [_ RF system Vec pin 145,TEST MODE 1. How to Activate CD Test Mode Insert the AC plug while pressing the function CD button, AILEL display tubes will light up, andthe test mode will be activated, 3. CD Test Mode Functions 2. How to Cancel CD Test Mode mode, ‘© Press the function button. Either one ofthe following operations will cancel the CD test ‘Press the power switch button. (except CD function button) # Disconnect the AC plug When test made is activated, the following mode functions from No.1 to No.S can be used by pressing the operation keys, Moe. | Operation | _FLdpay Operation Coca ‘Start mode | Activation | All lamps light | © ‘Test mode is activated ‘© FL display check (AI displays light) * CD biock poweris ON No Search mode | Wlkey Laser lode turns always ON “APC cru check * Cootnual focus search ites eument measurement a (The pickup lens repeats tefl GLateseumea compa Acasa [ IT. | ___ swing up-down motion.) ind GND). LL + ‘Avoid continual searches that ast for | FOCUS SERVO more than 10 minutes. ‘Check focus search waveform Ges focuser waveform CFOKIFZC are not monitored in the Noa +xoTe1 | _ search meds) Ply mode | <> Key * Nona playback FOCUS SERVO/TRACKING SERVO Ty 1 | * FocusscuchisconinedifTOC | CLV SERVOVSLED SERVO LIT | cso ex Grek DRE Nos *NoTe 1 Traverse mode | HI Key © During normal dis playback ‘TRACKING SERVO ONOFF CH 1 Press once; tracking servo OFF ‘Tracking balance (traverse) check LI | Pres twice: wacking servo ON Nos NOTE? Siedmose | M4 key | aitlamps tight | © Pickup moves othe outermost ack | SLED SERVO » Pickup moves othe fnnemnost rack | Check SLED mechanism operation * NOTES (During playback, machine operates Nos somal.) “NOTE 1: There ae cases when the tracking servo cannot be locked owing to the protection circuit being operated when heat builds up inthe driver IC ifthe focus search is operated continually for more than 10 minutes. In these cases the power supply should be ‘switched off for 10 minutes until hea has been reduced and then restarted. * NOTE 2: the start mode (No.1). Do not press the H4 or DH Keys when the machine isin the possible after the If satus has been canceled. Ifthe [€or Dp keys ate pressed inthe status is active. If they are pressed, playback will not be IB satus, press te il Key and return to = NOTE 3: When pressing the [4 oF DH keys take care to avoid damage tothe gears. Because the sled motor is activated when the J or >| keys are pressed, even when the pick-up is atthe outermost or innermost track. 4, Operation Outline "The operation of each mode is carried out in the direction ofthe arrows from the start mode as iniceted in the following illustration Wot No.3 Search made |} ——{@} >| Play mods No. 1 is) Sian made (AIIFLs light up) No.$ @ No.4 L[ sted made |} 3 >] Traverse mode If the DISC DIRECT PLAY button is pressed, the machine performs the same operation as the PLAY button is pressed as shown. If the tray is opened by pressing OPEN/CLOSE button during Play mode or Traverse mode, the machine returs tothe Start mode, 146ELECTRICAL ADJUSTMENT [A] 3CD C.B (PATTERN SIDE) ‘TPL (TE) ‘TP3 (VREF) ___1_o@ 147Note: + Connect a probe (10: 1) ofthe oscilloscope or the 2. Tracking Balance Check frequency counter toa test point + During adjustment, connect (©) pin of an Oscilloscope ‘oscilloscope to TP3 (VREF). (DC range) Oscilloscope (DC range) 1) Connect an oscilloscope to test points TPI (TE) and TPS 1P2 (RF cine Cnaae ed "13 (VREF)e 2) Start up the CD test mode. 3) Insert the test dise TCD-782(YEDS-18) and enter the traverse ‘mode of the CD test mode. TPL) # ‘TP3 (VREF) ols andor 4) Confirm thatthe waveform at oscilloscope has amplitude of \ A ‘ OS TERROR asso y a LRN ms LOI VOLTDIV: 20mV VoLnoW: sont Note: The current ofthe laser signal canbe checked with the voltages on both sides of R46 (voltage across 100). ‘The difference for the spécified value shown on the label must be within = 6.0mA, KSS.213B 15165 a so42e-T Laser cutent Top = —Wolae cross R46 100 148CD MECHANISM EXPLODED VIEW 1 / 1 (ZG-2 C2N ) ORIVE.C.8 CD MECHANISM PARTS LIST 1 / 1 (8ZG-2 C2N ) [DESCRIPTION THIF C8 7 OAHIE "REFERENCE NAME LIST’ 2BHL (EU. if can't understand for Description please kindly refer to “REFERENCE NAME LIST” ER NO PARTNO, wa besonPnIon REE.NO. PARTHO, A DesoAPTON No, "0 1 83-202-202-71K ose § asst, 019 PrcK-up,xss-2138 2 cama 019 TURN TASLZ,A5 3 §3-202-205-219, 8 219 S0RH Ve2-3 4 §5-202-220-01k GEAR MovoR 2 5 83-22-200-119 SHAPY SLIDE 149USE MODEL LIST CX-NAV70 (NSX-AV70) CX-NAV700 (NSX-AV700) CX-NAV71 (NSX-AV71) (CX-NAV80 (NSX-AV80) ‘CX-NAV800 (NSX-AV800) CX-NAVg0 (NSX-AV90) CX-NAV900 (NSX-AV900) CX-NK300 (NSX-K300) (CX-NK700 (NSX-K700) CX-NK77 (NSX-K77) CX-NKB0 (NSX-K80) CX-NKS0 (NSX-K90) CX-NV300 (NSX-V300) CX-NV3000 (NSX-V3000) CX-NV3001 (NSX-V3001) CX-NV390 (NSX-V390) CX-NV500 (NSX-V500) CX-NV700 (NSX-V700) X-NV705 (NSX-V705) CX-NV710 (NSX-V710) (X-NV715 (NSX-V715) ‘CX-NV720 (NSX-V720) CX-NV770 (NSX-V770) ‘CX-NV800 (NSX-V800) ‘CX-NV8000 (NSX-VB000) ‘CX-NV8080 (NSX-V8080) ‘CX-NV820 (NSX-V820) (CX-NV900 (NSX-V900) ‘CX-NV9000 (NSX-V9000) CX-NV9090 (NSX-V9030) CX-NV915 (NSX-V915) CX-NV929 (NSX-V929) FD-NAKH8 (NSX-AKH8) FD-NH8 (NSX-AVH8) FD-NH8 (NSX-AVH8) FD-NH80 (NSX-AVH80) FD-NH9 (NSX-AVH9) FD-NH9 (NSX-AVH9) FD-NH90 (NSX-AVH90) FD-SNAKH8 (NSX-AKH8) FD-SNH9 (NSX-AVH9) 150REFERENCE NAME LIST ELECTRICAL SECTION REFERENCE NAME ANTENNAS air GAP, CHIP DESCRIPTION ANT c Scar G-caP 1 eCOI cep SFA CSLIDE sw esw corr cvR CZENER CAP. CER CAPE CAP, MIF CERAFIL oF BL. EIcaP FLT FLIR FUSE RES Mor. P-DIODE. P-SNSR Pan POLY VARI PPCAP Pr PTA, RES RC RES NF TR TRIMMER, TUN-CAP vig, CER VIB, XTAL va ZENER SF FLey 25aD DIODE, CHIP DIODE’ CHIP FET CHIE FILTER. CHIP IKCK, CHIP LED, cHiP RES, CHIP SFR CHIP SLIDE SWITCH, CHIP SWITCH, CHIP TRANSISTOR, CHIP VOLUME, CHIP ZENER GHIP GAP, CeRA.SOL CaP, ELecT CAP, FILM GAP CERASOL GAP; CERASOL ss Gab. TANTALUM FILTER, CERAMIC FILTER, CERAMIC DELAY LINE CAB ELECT FILTER, FILTER ES, FUSE MOTOR PHOTO DIODE PHOTO SENSER PHOTO TRANSISTOR, VARIABLE CAPACITOR, 7 CaP. POViER TRANSFORMER PTR, MELE REMOTE CONTROLLER, ES, NON-FLAMMABLE RESONATOR, SHIELD. SOLENOID ‘SPEAKER SWITCH, LEVER SWITCH, ROTARY SWITCH, SLIDE GaP, Cena-SOL THERMISTOR TRANSISTOR, GAP, TRIMMER VARIABLE cAPacITOR RESONATOR, CERAMIC RESONATOR, CRYSTAL VOLUME DIODE, Zener, SERGESUPPRESSOR CAP.CERA 1st MECHANICAL SECTION DESCRIPTION ADHESHIVE a BAR-ANT ear Batt HINGE, BAT HLOR HIPSINK a IDLE IND, LR KEY, CONT KEY. PRGM Knog, St ta Uo, Bart Lip, cass La Buse. PANEL, CONT PANEL. FR PRoW PULLY, LOAD MO BBN § See SH SHLD-SH St 3P SP-scREW SPACER, BAT SPR SPRP ‘SPR.PC-PUSH TSP TERM TriG wat, WORM.WHL BIR STIR Ahoo7 ROee ElSex ERGO REFERENCE NAME SHEET ADHESHIVE RaIMUTH BAR-ANTENNA BATTERY BATTERY BEARING BUTTON CABINET GASSETTE CHASSIS COLLAR, CONTROL GuRson GUSHION GUSHION DIRECTION DUBBING FRONT LOADING FLYWHEEL FRONT. FUNCTION G-cUSHION HANDOL. torn HINGE, BATTERY HOLDER HEAT SINK INSTRUCTION BOOKLET IDLER. INDICATOR, L-A KEY, CONTROL KEY! PROGRAM NOS, SLIDE UABEL UO, BATTERY LID, CASSETTE Lever P-SPRING PANEL, CONTROL PANEL, FRONT PROGRAM PULLY LOAD MOTOR RIBBON SPECIAL SEGMENT SHEET SHIELD-SHEET SLIDE SPRING SPECIAL-SCREW SPACER, BATTERY SPRING P-SPRING P-SPRING, C-PUSH TSPRING TERMINAL TRIGGER TUNING VOLUME WASHER WHEEL WORMEWHEEL ARM SHAFT GUIDE, SHAFT ‘STRAP S.SCREW HINGE SSOREW SCREW,SERRAATPT TRABA AIWA CO.,LTD. T110 RRBARR tie 1— 2-11 ‘03 (3827) 3111 (ft) (areiea, 750088 ] Tokyo Japan Printed in Singapore

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