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Chapter 4

Electrodeposition
Madhav Datta

4.1 Introduction
Electrodeposition is the process of cathodic deposition of metals, alloys, and other conducting materials from an electrolyte using an external potential (electric current) for the cation reduction process to occur at the working substrate. The deposition process is also known as electrolytic plating, electroplating, or simply plating. Electrodeposition is widely employed in a variety of applications ranging from coatings for wear and corrosion resistance to nanoscale feature fabrication for ultra-large-scale integration (ULSI). The deposition thickness may vary from few angstroms of uniformly deposited compact lms to electroformed structures that are millimeters thick. Compared to competing vacuum deposition processes, electrodeposition has emerged as more environmentally friendly and cost-effective micro/nanofabrication method. These features of electrodeposition make it an enabling technology for applications such as chip metallization and ipchip solder bumping. Electrodeposition has thus become an integral part of wafer processing fabs and an enabling technology in many aspects of microelectronic packaging. Although some aspects of electrodeposition still remain empirical, the gap between fundamental understanding and manufacturing application is narrowing [1]. In the following text the terms electrodeposition, electroplating, and plating are used synonymously. Advances in electrodeposition have played a major role in the phenomenal growth of storage, chip interconnects, microelectronic packaging, microelectromechanical systems (MEMS), and many other microelectronic and micromechanical components [210]. Some early examples of electrodeposition in the electronics industry include fabrication of printed circuit boards. Continued advances in plating processes for ne line wiring technology have contributed to the development of advanced boards and packages that are used today. Development of alloy plating

M. Datta (B) Cooligy Inc., 800 Maude Avenue, Mountain View, CA 94043, USA e-mail: mdatta@cooligy.com

Y. Shacham-Diamand et al. (eds.), Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications, DOI 10.1007/978-0-387-95868-2_4, C Springer Science+Business Media, LLC 2009

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process, precision plating tool, and the application of through-mask plating for thin lm heads laid the foundation for the advances in electrochemical technology in the micro- and nanoelectronics industry [2]. Continued efforts on the development of novel magnetic materials and their precision plating have led to the advanced storage devices [3, 4]. Phenomenal advances in electroplating occurred in the last decade when it enabled a paradigm shift in chip making with the introduction of plated ip-chip technology and Cu metallization for chip interconnects [68]. Indeed, the material change from aluminum to copper for chip metallization has been heralded as a major breakthrough that will enable extension of Moores law beyond its earlier expectations. Other applications of electroplating in microelectronics include fabrication of connectors and interconnect, and metallization for multi-chip modules and other advanced packages [9]. These applications heavily relied on the advances in electroplating technologies which have been possible due to simultaneous progress in different areas. They include (i) continuous improvements and innovations in photolithography, (ii) fundamental understanding of the engineering principles that govern electrochemical micro- and nanofabrication processes and the ability to produce tailored materials and structures, and (iii) development of high yielding electrochemical processing tools that are compatible with ultra-clean semiconductor fabrications [10]. Some of these aspects are briey discussed below.

4.2 Key Considerations


For electroplating on silicon wafers, one of the essential requirements is the presence of a continuous conducting layer (seed layer), which provides electric current path from the wafer edge contact to all points in the wafer where deposition is desired. Two different types of electroplating are applicable in the fabrication of a metallic structure: (i) through-mask plating (ii) and Damascene plating. While photoresist masks in through-mask plating are stripped to release the plated structure, in Damascene plating the patterned dielectric remains intact and forms a functional part of the structure. A continuous seed layer conformally covers the patterned dielectric. Plating occurs all over the surface thus creating challenges for void-free structure fabrication [7]. Chemical mechanical polishing (CMP) is used for planarization and removal of excess overburden metal and seed layers. Development of electroplating processes and tools for fabrication of micro- and nanostructures requires a thorough understanding of the underlying electrochemical engineering principles. This involves the understanding of the ability to produce tailored materials and structures and the application of the principles of mass transport and current distribution [11]. Small changes in process conditions can have an enormous effect on the microstructure and composition of the deposit and hence its properties. These small changes may be in the form of additives or complexing agents or in the deposition parameters. These aspects of electroplating offer the possibility of fabricating structures with tailored materials and properties. Precise control of the additives and process parameters is extremely critical to obtain reproducibility and uniformity

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of deposition. Internal stress that frequently develops in electrodeposits can cause cracking or loss of adhesion. Mismatch between substrate and deposit, grain coalescence during growth, and incorporation of additives or hydrogen may contribute to the internal stress. It is well known that electrodeposition under limiting current conditions leads to dendritic or powdery deposits [12, 13]. Therefore; the value of the operating current density with respect to the mass transport limited current density is a critical parameter for deposit morphology. Mass transport conditions at the wafer limit the rate of electroplating and inuences the current distribution and microstructure of the deposit. These criteria determine the thickness and uniformity of blanket deposited layers. In patterned plating, they also determine the shape evolution, leveling, and superlling. The current distribution in patterned plating is considered on three different scales: substrate scale, repeating pattern scale, and feature scale [14]. At the substrate level, the current distribution is governed by the overall cell geometry and the uniformity of current distribution is generally achieved by using auxiliary electrodes or current shielding concepts. On the pattern scale, the current distribution depends on the feature geometry and the spacing. Current density on a feature is higher when it is spaced farther away from a neighboring feature. On a feature scale, the current distribution evolves with time due to the continuously changing shape of the feature. The current distribution within the features is inuenced by the use of suitable additives [7, 14, 15]. Additives are widely employed in electroplating practice for grain rening, stress relieve, leveling, and brightening. Surfactants are also commonly added to plating electrolytes to facilitate evacuation of gas bubbles. A leveling agent is a suitably chosen additive that generally acts as an inhibitor for the metal deposition reaction. It is consumed at the cathode and its reaction rate is mass transport controlled [1518]. Since peaks are more accessible than valleys, they are more strongly inhibited by the additives, leading to preferential metal deposition into recess. These concepts have been used to develop understanding of superlling during dual-Damascene plating and to develop electroplating baths for Cu interconnects. Grain rening and brightening are related to inhibition which affects nucleation and growth. Early studies of the role of additives for the development of microstructure in electrodeposition were performed by Seiter and Fischer [19], who recognized the importance of inhibition for obtaining ne-grained deposits. Fishers concepts were further rened by Winand [20] and the factors affecting microstructure of electrodeposits were also discussed by Landolt [12]. The use of additives in electrodepositon of copper is a widely studied topic. Schimdt et al. [21] found that in a sulfate solution without additives copper nucleation on gold was three-dimensional. The presence of BTA decreased the size of nuclei and increased their number, while the presence of thiourea led to the formation of small at plates. Armstrong and Muller [22] found that BTA inhibits the growth of specic planes of copper but does not affect the number of nuclei. Kelly et al. [23] investigated the synergistic effects of adsorbed species using electrochemical methods and near eld microscopy. These authors demonstrated a strong synergistic effect between the adsorbed plating additive and the chloride ion. Such studies of the interactions between different additive species

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and their role in the nucleation and growth of deposits in nanostructures are of great importance to understand the mechanisms involved in Damascene plating of copper interconnects.

4.3 Pulse Plating and Pulse Reverse Plating


Pulsating the current (or voltage) permits the plating process to be operated at higher average current density than dc plating without the formation of dendrites. Furthermore, the composition of alloy deposits can be varied by varying pulse parameters while keeping the average current density constant. Mass transport in pulse plating has been studied by a number of authors [2426]. In principle, pulsating current creates a combination of steady-state and non-steady-state diffusion processes such that by varying the pulse parameters, the relative contribution of each diffusion process can be controlled. Two different limiting currents must be distinguished, the steady-state limiting current density iL which for a given electrolyte concentration depends only on hydrodynamic conditions and the pulse-limiting current density, ipL . The pulse-limiting current density ipL corresponds to that value of peak current, ip, where the reactant concentration at the surface reaches zero just at the end of a pulse. For a applied pulse current density close to ipL the current distribution is governed mostly by non-steady-state mass transport and therefore may become relatively uniform. Indeed, in metal deposition using pulse plating one usually works well below the pulse-limiting current density in order to avoid dendrite formation. In alloy deposition, on the other hand, when the nobler component is present at small concentration in the electrolyte its pulselimiting current density is exceeded during deposition of the less noble component. This can lead to spatial uniformity of composition because one component is governed by tertiary current distribution and the other by secondary current distribution. Depending on the mass transport conditions at the cathode, the current distribution in pulse plating can be less or more uniform than in dc plating. In the absence /di , which governs of signicant mass transport effects the Wagner number, Wa = d eL secondary current distribution in pulse-plating depends on the pulse current density rather than the average current density. Because the pulse current density is always higher than the average current density the Wagner number corresponding to a given deposition rate is smaller in pulse plating than in dc plating and the current distribution therefore is less uniform. In the presence of signicant mass transport effects the situation is quite different, however, and the current distribution in pulse plating may be more uniform than in dc plating. Due to the high instantaneous current densities applied in pulse plating the reaction rate during the pulse on time may become limited by non-steady-state mass transport even under conditions where the average current density is well below the dc limiting current density. For an average current density corresponding to a secondary current distribution in dc plating a tertiary current distribution may therefore prevail in pulse plating under certain conditions leading to a more uniform current distribution.

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Pulse reverse plating offers the possibility of achieving more uniform current distribution than in dc plating. In order to achieve this, the pulse parameters are so chosen that during the cathodic deposition cycle the current distribution is more uniform than during the anodic dissolution cycle. For example, one can apply a cathodic pulse corresponding to a relatively uniform secondary or tertiary current distribution, followed by a short high current density anodic pulse corresponding to a primary current distribution. The application of pulse reverse current is throughhole plating was studied by Pesco and Cheh [27]. Although the use of pc leads to a less uniform current distribution than the use of dc, pulse reverse plating was considered by the authors as a promising technique for improving current distribution. Wan et al. [28] investigated the applicability of pulse plating and pulse reverse plating in through-hole plating taking into account both the potential distribution and the prevailing mass transport conditions. From their theoretical analysis the authors concluded that throwing power is not improved by pulse plating but the use of pulse reverse plating may lead to more uniform deposits, in agreement with Pesco and Cheh [27]. Yung et al. [29] showed that the critical parameter characterizing the deposition rate in through-hole plating is proportional to L2 /r where L is the printed circuit board thickness and r is the hole radius. The current distribution therefore depends on the absolute dimension of the hole in addition to the aspect ratio.

4.4 Electrodeposition of Copper


Copper is the most commonly plated material for its varying decorative, functional, and engineering applications. Several different types of copper plating systems that have been reported in the literature include alkaline cyanide, uoborate, pyrophosphate, and acid sulfate baths [30]. Due to toxicity and waste treatment issues, cyanide baths are getting replaced by non-cyanide baths. High speed plating uoborate baths and pyrophosphate baths used in plated through-hole PCBs have been mostly replaced by acid sulfate baths that have become the most commonly used, cost-effective copper plating systems in the micro- and nanoelectronics. Copper sulfate and sulfuric acid are the primary constituents of the acid sulfate baths. The sulfate bath generally contains chloride ions in varying range of concentrations to inuence the deposit properties such as microstructure, microhardness, crystallographic orientation, internal stress, and surface appearance. Several organic additives are also frequently added to the bath to inuence surface nish, grain rening, and suppression of dendritic deposition. A list of these additives and their functions in electrodeposition of copper is presented in [30] and of applied current density on the deposit morphology has been reported in the literature [13, 3133]. Increasing inhibition and/or increasing current density produces ne-grained structures. Kinetically limited growth tends to favor compact columnar or equiaxial growth in copper deposits while mass transport limited growth favors formation of loose dendritic deposits. During electroplating of microfeatures, the use of proper additives is essential for leveling and superlling [7, 34].

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Additives that act as inhibitors tend to promote formation of ne equiaxial grains, which may lead to increased internal stress. Electrodeposited copper may contain non-equilibrium grain structures, which spontaneously recrystallize even at room temperature [35]. As a consequence, structure-dependent properties such as sheet resistance and internal stress of deposits may change slowly with time after deposition.

4.4.1 Electrodeposition Process for Copper Interconnects


Cu interconnects are fabricated by dual-Damascene process which is referred to a metallization patterning process by which two insulator (dielectric) levels are patterned, lled, and planarized to create a metal layer consisting of vias and lines [7]. A sandwich of two levels of insulator and etch stop layers is patterned as holes for vias and troughs for lines. They are then lled with a single metallization step. Finally, the excess material is removed, and the wafer planarized by CMP. Electroplating enables deposition of Cu in via holes and overlying trenches in a single step thus eliminating via/line interface and signicantly reducing the cycle time. Due to these reasons and due to relatively less expensive tooling, electroplating is a cost-effective and efcient process for Cu interconnects fabrication. The Damascene copper plating process is typically based on a chloridecontaining acid copper sulfate solution [7, 36]. In such a system formation of voids is very common, particularly in narrow trenches, where top ridges build up rst thus creating a void in the middle of the structure. Formation of seams is commonly observed during conformal plating as well. Such seams can be as disastrous as the voids. So formed voids and seams lead to electromigration problems in submicrometer interconnect structures. These defects can also entrap electrolyte that can lead to serious corrosion issues. Elimination of voids and seams is therefore very critical to minimize electromigration and other reliability issues. In dual-Damascene plating, defect-free lling of trenches can be achieved by creating a condition where higher deposition rate is achieved in less accessible bottom of the trenches, compared with the easily accessible at top surface and upper side walls. Small amounts of organic additives added in right concentrations can increase the plating rate inside trenches and vias relative to the planar surface. This differential bottom-up plating rate leads to superlling. For defect-free, superlling deposition, several organic additives are added to the bath. Based on their function, these additives can be broadly categorized into two types: an accelerator and an inhibitor. The accelerator is essentially an organic sulfur-containing compound (a mercapto species) that preferentially adsorbs at the bottom of a via. Inhibitor additive (s) in the bath may contain one or more components. The main inhibitor is generally a glycol, which acts to suppress the electrodeposition rate especially in the presence of chloride ions. Some baths also contain a nitrogen-containing molecule that acts as a leveling agent. Competitive adsorption of these inhibitor molecules together with the fact that one or more of these co-adsorbed species may be mass transport controlled lead to a condition whereby via/trench bottoms are less inhibited.

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Mathematical modeling work by Dukovic et al. [7, 14] assumed that the additives react under diffusion control while the metal deposition reaction is under activation controlled. Thus by optimizing the reaction rates (by varying additive concentration and adjusting the current density of Cu deposition), it is possible to obtain higher deposition rate at the bottom of via/trench. Moffat et al. [34, 3739] and West et al. [23, 40] explained the superconformal electrodeposition of copper by a curvature enhanced accelerator coverage model. The model is based on the assumptions that the local growth velocity is proportional to the surface coverage of the accelerator and the accelerator remains segregated at the metal/electrolyte interface during copper deposition. During deposit growth on nonplanar geometries, this leads to enrichment of the accelerator on the evolving concave surfaces and depletion on convex surfaces. This phenomenon gives rise to bottom-up superlling of submicrometer trenches and vias. In addition to the superlling property, these additives also inuence the deposit structure (hence stress) and roughness. It is evident that a delicate balance of respective additives is needed in the bath to obtain precise fabrication of void-free, nanoscale Cu interconnects that are to be uniformly laid on hundreds to thousands of chips in a 300 mm wafer.

4.5 Concluding Remarks


This chapter presented a brief description of electrodeposition process and a focused discussion of copper electrodeposition for chip interconnects. It must be emphasized that different chip manufacturers have their unique combination of electrodeposition tools, proprietary tailored bath, and integration scheme for copper chip interconnects. Successful implementation of the copper electrodeposition process in high volume chip manufacturing involves equal attention to metrology, process integration, and reliability issues. Besides void-free deposition of interconnect structures, selection of a reliable CMP process, excellent adherence of copper lines/vias to the dielectric, low resistivity, and resistance to electromigration are some of the key requirements for a high yielding, reliable interconnect electrodeposition process. All these aspects are addressed in greater detail in different chapters of this book.

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