MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012

CMOSNORGate
Ingeneral,aparallelpathintheNMOSnetwork
correspondstoaseriespathinthePMOSnetwork.
CMOSNORGate:parallelNMOS,seriesPMOS.
CMOSNORgate ReferenceInverter
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CMOSNORGateSizing
Whensizingthetransistors,theR
on
onthe
PMOSbranchoftheNORgatemustbethe
sameasthereferenceinverter(tokeepthe
delaytimesequalundertheworstcase
conditions)
ForatwoinputNORgate,the(W/L)
p
mustbe
madetwiceaslarge
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
ThreeInputNORGateLayout
Itispossibletoextendthissamedesigntechniqueto
createmultipleinputNORgates
ThreeinputCMOSNORgate: = A +B +C
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CMOSNANDGates
Ingeneral,aseriespathintheNMOSnetworkcorresponds
toaparallelpathinthePMOSnetwork.
CMOSNANDGate:seriesNMOS,parallelPMOS.
CMOSNANDgate
ReferenceInverter
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CMOSNANDGatesSizing
ThesamerulesapplyforsizingtheNANDgate
asthedidfortheNORgate,exceptfornow
theNMOStransistorsareinseries
The(W/L)
N
willbetwicethesizeofthe
referenceinvertersNMOS
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
MultiInputCMOSNANDGates
FiveinputCMOSNANDgate: = ABCE
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CapacitancesinLogicCircuits
Variouscapacitances
associatedwithtransistors
Thecapacitancesonagiven
nodecanbelumpedintoafixed
effectivenodalcapacitanceC
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
LogicGateDynamicResponses
Risetime(t
r
): timerequired
from10%pointto90%point
Falltime(t
f
): timerequired
from90%pointto10%point
Propagationdelay(
P
):
differenceintimebetween
theinputandoutputsignals
reachingthe50%points
foroutputhightolow:
PHL
foroutputlowtohigh:
PLH
averagepropagationdelay
P
=
(
PLH
+
PHL
)/2
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
DynamicResponseof
CMOSInverter
AssumeabruptV
I
change
fromV
L
toV
H
V
O
changesfromV
H
toV
L
bydischargingC viaM
N
Sameastheresistiveload

PHL
= 1.2R
onn
C
R
onn
=
1
K
n
(I
H
-I
1N
)
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
DynamicResponseof
CMOSInverter
AssumeabruptV
I
changefromV
H
toV
L
V
O
changesfromV
L
toV
H
bychargingC viaM
P
Similarlyweget

PLH
= 1.2R
onp
C
R
onp
=
1
K
p
(I
H
+I
1P
)
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CMOSInverterwithSymmetricalDelay
CMSinverterwithsymmetricaldelayhas
PLH PHL onn onp n p
Thisisexactlythesymmetricalinverter
p
n
= 2.Sp
p

w
I
p
= 2.S
w
I
n

P
=

PLH
+
PLH
2
= 1.2R
onn
C
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CMOSSwitchingSpeed
Canestimateswitchingtimeforcapacitiveloadverysimply:
t =
C
totaI
:
i
avg
=

i
avg
For
PHL
, v
I
=V
DD
,PMOSOFF,NMOSON.
NMOSsaturatedforv
O
>V
DD
V
TN
,linearforv
O
<V
DD
V
TN
JusttheoppositeforLHtransition.
MicroelectronicCircuitDesign UWEEChen/Dunham EE331Spr 2012
CMOSPerformanceScaling

P
:
PHL
+:
PLH
2

P
C

P
R
on

w
L
-1
Delayisproportionaltototalloadcapacitance
C,andinverselyproportionaltoW/L.
Largersize(largerW/L)=>shorterdelay