www.4tech.com.

vn

HIN THC M HNH MNG NEURON NHN TO TRN FPGA

HONG MNH H 1 - TRN THANH PHNG 2 B no ngi bao gm khong 100 t neuron v gia chng c khong 100 t t kt ni. N l mt i tng phc tp nht c bit trong v tr. Mng neuron nhn to l s m phng theo hot ng ca mng neuron sinh hc. Hin nay vic thit k cc m hnh neuron nhn to trn my tnh i hi phc tp ngy cng tng phc v cho cc ng dng thc tin m i hi kh nng x l ca cc neuron nhn to t n mc gn vi neuron sinh hc. iu ny vt ra ngoi kh nng ca cc m hnh phn mm my tnh truyn thng. FPGA (Field Programmable Gate Arrays) l cc vi mch tch hp mt cc cao c kh nng x l mnh, kh nng ti cu hnh d dng, do ang l ng c vin sng gi trong vic thit k cc m hnh neuron nhn to hin nay cng nh trong tng lai. Bi bo ny gii thiu qu trnh hin thc mt m hnh neuron nhn to trn phn cng FPGA hin c ca phng th nghim in t - Vin thng, i hc Tn c Thng. Gii thiu mc ch v l do thc hin ti Qu trnh x l ca no mang tnh song song v phn b. Mng neuron c kh nng hc cc quy lut m t trong tp d liu hun luyn, v t thng tin thu thp trc , p ng vi nhng mu mi. Mng neuron c tnh dung th vi cc li, tc l vic mt mt vi neuron hoc mt s cc kt ni th khng nh hng nghim trng n ng x ca n, do vic x l i hi mt s lng ln cc neuron v cc lin kt. Mng neuron nhn to l s m phng theo hot ng ca mng neuron sinh hc. ti cu hnh v kh nng thc hin cc php tnh ton s hc v logic vi tc cao. Cc vi mch ny c s dng mt cch rng ri trong cc thit b cng nghip cng nh dn dng hin nay, chng hn cc b vi iu khin, cc thit b quang bo, cc loi my nh s, Cc k s vin thng chuyn thit k mng, radar, thng tin v tuyn, x l video v audio s, cc thit b hng khng, thit b qun s, cc thit b o kim, x l nh y khoa v v s cc ng dng khc u s dng FPGA vi vai tr l b ng x l hoc b x l s tn hiu (DSP) trong thit k ca mnh. Ngoi ra, FPGA cn c s dng trong sinh hc: nghin cu DNA v protein cng s dng FPGA gim thi gian x l, cc vn phn tch, chn on bnh thi gian thc cng c thc hin nh li dng kh nng ca FPGA. Sau khi cc thit k c thc hin thnh cng trn FPGA, c th a vo sn xut hng lot vi cng ngh ASIC. l mt thit b tng t nh FPGA nhng c tc x l nhanh hn, ng thi mang li li th chi ph nu sn xut s lng ln, mc d n khng c kh nng thay i linh hot nh FPGA v chi ph cao nu thit k s lng thp. Vi cng ngh FPGA hin nay, cc FPGA c tc ln n 500MHz, s slice ln n hng trm ngn. Mt s FPGA cn c cc DSP slice, chng hn nh Vertex-4 s DSP slice c th ln n 512, hot ng 500MHz th kh nng x l c th ln n 256 Giga-MACs (multiply-accumlate operations). Mc tiu ca ti l hin thc ha mt s cu trc mng neuron ln FPGA xy dng m hnh mng neuron trn phn cng FPGA lm c s cho vic hin thc ho cc gii thut hun luyn cho mng neuron trn chip, v t c th m ra cc hng thit k cc ng dng x l

a s cc ng dng hin nay dng mng neuron di dng cc phn mm. Tuy nhin, c mt li im trong chnh cu trc ca mng neuron l tnh song song vn c ca chng, do rt ph hp nu thc hin chng bng phn cng. Trong nhng nm 80 v na u thp k 90 c nhiu nghin cu thc hin cc my tnh neuron nhng cha thnh cng do hn ch v lng ti nguyn v tc ca phn cng, do cc nghin cu kt thc vo cui nhng nm 90. Tuy nhin, hin nay lnh vc nghin cu ny ang c nhiu nh khoa hc quan tm, do c s pht trin mnh m ca cng ngh ASIC3 v FPGA. FPGAs l cc vi mch tch hp chuyn dng c thit k vi tnh nng c bn l kh nng

www.4tech.com.vn

w w

ng dng ca mng neuron nhn to c hai mng chnh: nhn dng (phn lp i tng), xp x hm (vi mt tp cc mu mng neuron tm mt hm trn xp x nh x gia ng vo v ng ra). Cc ng dng ca mng neuron c th tm thy trong nhiu lnh vc, chng hn: x l tn hiu, phn tch nh, h thng chun on y khoa, d bo ti chnh, ...

.4 t

ec h.
-1-

co m

.v

www.4tech.com.vn
Hm hot ho c chn trong nghin cu ny 1 l hm sigmoid: f (u ) =
1 + exp( u )

2. nh dng s C hai nh dng chun trong vic biu din gi tr s thc l nh dng du chm ng (floating point FLP) v nh dng du chm tnh (Fixed point FXP). nh dng du chm ng c c im tm gi tr biu din rt rng v chnh xc cao, tuy nhin thc hin php tnh s vi cc gi tr theo nh dng du chm ng phi cn lng ti nguyn ln. Ngc li, vi nh dng du chm tnh lng ti nguyn cn thit thc hin cc php tnh th ch tng ng vi lng ti nguyn thc hin php tnh trn s nguyn c cng s bit. Tuy nhin, tm gi tr th hin c v chnh xc b gii hn. Trong nghin cu ny, nh dng du chm tnh 18 bit vi 11 bit cho phn thp phn c s dng biu din mt gi tr s thc. 3. Hin thc mt neuron Vic chn la mc song song trong m hnh tnh ton ca mng neuron c xt n cc yu t: lng ti nguyn ca FPGA hin c, v tc x l ca mng neuron. Trong nghin cu ny, qu trnh x l song song ca mng neuron c thc hin mc mi phn t neuron, tc l mi phn t neuron thc hin qu trnh tnh ton c lp. Cc neuron trong cng mt lp mng thc hin tnh ton song song. Vic tnh ton ca tng neuron c thc hin trn vic tnh tng tch lu cc tch d liu vo v trng s. Vi m hnh ny, ng vi mi neuron cn mt b nhn, mt b tng tch lu, v mt b RAM lu tr cc trng s tng ng ca cc ng vo ca neuron. Qu trnh tnh ton ca mi neuron c thc hin tun t vi tng phn t vector d liu vo.

M hnh mng neuron hin thc trn FPGA 1. M hnh mng neuron
I I O O

Hnh 1. Cu trc mng neuron hai lp (1 lp n)

s : ch s ca lp mng, s = 1, 2,..., M ; M : s lp mng.

k : ch s ca neuron trong lp mng. N ( s 1) : s neuron trong lp ( s 1) . (s) ok : ng ra ca neuron th k trong lp mng s. f : hm hot ho. H k( s ) : tng cc tch ng vo vi trng s.
o(js 1) : ng ra ca neuron th j trong lp mng

s 1 (s) wkj : trng s ca neuron th k trong lp s

lin h vi ng ra ca neuron th j trong lp s1. (s) wk 0 : h s bias ca neuron th k trong lp s.

w w

(s) k

= f (H

(s) k

N ( s ) ( s 1) (s) o j + wk ) = f wkj 0 j =1
( s 1)

.4 t

Trong nghin cu ny, m hnh mng neuron nhn to c s dng l m hnh mng neuron perceptron mt lp v hai lp (vi mt lp n). Mt cch tng qut, quan h vo ra ca mt mng neuron M lp c cho bi biu thc:

www.4tech.com.vn

ec h.
-2-

co m
O

Hnh 2. S cu trc ca mt neuron hin thc trn FPGA

4. Xp x hm sigmoid C nhiu k thut c dng thc hin cc hm i s bng phng php s: tra bng, xp x bng hm a gic, gii thut CORDIC,

.v

www.4tech.com.vn
u

If u<0, invert u

FPGA. Ch xt on ng vi u > 0 . Nu u < 0 th u c o du, v f (u ) = 1 f (u ) . 5. Mt lp mng neuron Cc neuron trong mt lp mng x l tnh ton ng thi. Qu trnh tnh ton ca mi neuron c thc hin tun t vi tng phn t trong vector d liu vo ca lp. Cu trc mt lp mng neuron c hin thc trn FPGA c th hin trong s khi hnh 5. Khi Neuron RAM of Weights l mt neuron v b nh lu tr cc trng s ca neuron . Khi RAM of Data input l b nh lu tr d liu vo ca lp mng neuron. Khi control iu khin iu khin qu trnh nhp cc trng s vo RAM ca cc neuron, qu trnh nhp d liu vo, v khi control cng iu khin qu trnh tnh ton ca cc neuron.

u1
Compare

mn sign bn

u1

f(u1)= mnu1+bn
If sign negative, Else

1 f (u1 ) f (u1 )
f(u)

.v co m
Data in RAM
Of Data Inputs

n
Control
Neuron
RAM of Weight

Neuron RAM of Weights

Hnh 3. S tnh hm sigmoid

Data out

Bng 1: Cc h s ca cc on chia
on Chia u1 mn

.4 t

Trong nghin cu ny, k thut xp x hm bng hm a gic c chn. K thut ny thc hin xp x hm i s phc tp bng cc hm bc nht trn cc on khc nhau. chnh xc ca k thut ny ph thuc s on chia v cch thc chia cc on. Trn on th n, hm i s c xp x bng hm bc nht: f (u ) = mn u + bn , y mn , bn l hng s ng vi on th n.
bn

Neuron RAM of Weights

Data out

ec h.

Neuron
RAM of Weights

Data out

T 0.0 n 1.5 T 1.5 n 3.0 T 3.0 n 4.0 T 4.0 n 6.0 Ln hn 6.0

0.2117 0.0900 0.0294 0.0078

0.5000 0.6826 0.8643 0.9510 1.0000

Hnh 5. S khi 1 lp mng neuron thc hin trn FPGA

w w

6. Mng neuron hai lp

Neuron
RAM of Weight

0.0000

RAM
Of Data Inputs

Neuron
RAM of Weight

Neuron
MUX
RAM of Weight

0.025 0.02 0.015 0.01

Neuron
RAM of Weight

Neuron
RAM of Weight

Sai s

0.005 0 -0.005 -0.01 -0.015 -0.02 -0.025 -10

Control
Hnh 6. S khi mng neuron 2 lp thc hin trn FPGA

u1 Hnh 4. Sai s vic xp x hm sigmoid

-8

-6

-4

-2

10

Do tnh i xng ca hm sigmoid, s lng on chia c th c gim i mt na. Do gim mt na s b so snh khi thc hin trn

Cu trc mng neuron hai lp c hin thc trn FPGA c th hin trong s khi hnh_6. Vi cu trc mng neuron hai lp, cc lp mng c ni ni tip vi nhau. Tuy nhin trong lp mng th hai, khng cn mt RAM lu tr cc d liu vo ca lp mng ny m trong mi chu k nhp tnh ton ca

www.4tech.com.vn

-3-

www.4tech.com.vn
lp th hai d liu vo c chn thng qua b MUX. 7. Nhp xut d liu Mng neuron cn c b trng s v d liu vo thc thi vic tnh ton. B trng s c lu vo RAM ca mi neuron trong qu trnh khi to mng neuron cho ng dng c th. Sau khi c nhp b trng s, qu trnh tnh ton ca mng c th c thc hin vi mi vector d liu vo v xut ra mt vector kt qu. Kt qu Vic hin thc m hnh mng neuron c thc hin mc thit k RTL (Register Transfer Level). Ngn ng thc hin cho vic m t thit k l VHDL. Kit XUPV2P ca Xilinx vi chip FPGA XC2VP30 c s dng trong nghin cu ny. Cu trc v lng ti nguyn cn thit thc hin hai mng neuron mt lp v hai lp c cho trong bng_2.
Bng 2: Cu trc v lng ti nguyn s dng Mng mt lp
Cu trc S neuron lp 1 32 S neuron lp 1

Nhn xt, ngha khoa hc Nghin cu ny hin thc c hai cu trc mng neuron nhn to trn FPGA vi kt qu thc thi ca hai mng neuron ny kh khp vi kt qu thc thi ca mng neuron m phng trn my tnh. Sai s xut hin y do hai yu t: sai s do vic xp x hm sigmoid v y l sai s c nh hng ln n kt qu, v sai s lng t do s gii hn bit. S chu k nhp thc hin vic tnh ton ca mng neuron mt lp l 36, s chu k nhp thc tnh ton ca mng neuron neuron hai lp l 36+26. Tc ngun Clock cung cp cho mng neuron mt lp l 100MHz, nh vy cu trc ny c kh nng x l 2.6 Giga MACs; v vi mng neuron hai lp tc ngun Clock cung cp l 50MHz, nh vy vi cu trc ny v hai lp mng c iu khin x l dng ng ng th kh nng x l c th ln n 2.5 Giga MACs. Nh vy module neuron nhn to trn FPGA hon ton c th thay th c cc phn mm my tnh trong vic phn tch v x l nh, m c th y l nhn dng nh cc k t trong bng ch ci.

Mng hai lp

S neuron lp 2 S ng vo S b tnh sigmoid hm 64 01 01 01 S ng vo

S b tnh sigmoid

S giao tip UART S b iu khin

.4 t
S giao tip UART S b iu khin S slice S slice Flip Flop S LUT 4 ng vo S BRAM S b nhn 18 bit

S slice S slice Flip Flop

Lng ti nguyn s dng

923 735

w w

S LUT 4 ng vo S BRAM

1224 33

S b nhn 18 bit

33

Mng neuron mt lp v hai lp hin thc trn FPGA nh m t phn trn c s dng cho vic nhn dng 26 k t. Kt qu thc thi ca hai mng neuron hin thc trn FPGA nhn dng ng 100% cc mu c hun luyn. Kt qu thc thi ca mng neuron mt lp v hai lp hin thc trn FPGA cn c so snh vi kt qu thc thi m phng mng neuron c cng b trng s v cng tp d liu vo. Sai s gia hai kt qu nh sau: i vi mng neuron mt lp sai s cc i l 0,003597. i vi mng neuron hai lp sai s cc i l 0,026523. Cc sai s trn c xc nh trong trng hp cc gi tr vo trong khong [0 1].

www.4tech.com.vn

ec h.
32 64 hm 02 01 01 1748 1346 2244 65 66

32

co m
-4-

Kh nng ng dng ca ca m hnh ny l xy dng mt module c bn cho vic pht trin cc ti nghin cu khoa hc tip theo ca sinh vin v ging vin thuc ngnh in t - Vin thng. ng thi, mt s module nh ca ti c th a vo phc v ging dy mn Th nghim Thit k logic s. Hin nay, vn x l nh ang l mt ni dung nghin cu mang li nhiu ng dng thc tin, chng hn nh phn loi cc sn phm trong mt dy chuyn sn xut, nhn dng bin s xe x l vi phm, kim sot vn thu ph giao thng mt cch t ng, c bit l cc ng dng trong lnh vc y sinh nh phn tch cc yu t di truyn hoc chn on bnh da trn hnh nh siu m, v trong k thut x l nh th th phng php dng mng neuron l mt phng php kh hiu qu. Do , y cng l ngun tham kho cho cc sinh vin, ging vin v cc nh nghin cu trong lnh vc vin thng.

Nh phn trn trnh by kh nng ng dng ca mng neuron nhn to c lin quan n phc tp ca n, m phc tp ca m hnh li ph thuc vo kh nng ca thit b FPGA. Hin nay phng th nghim in t - Vin thng ch mi c trang b cc thit b rt n gin phc v cho mc ch ging dy l ch yu. Do , trong iu kin gii hn v kinh

.v

www.4tech.com.vn
- a gii thut hun luyn vo cu trc mng neuron. Cu trc c th thc hin nh s khi sau:

Hiu qu kinh t - x hi v gio dc Hin nay c rt nhiu lnh vc trong cng nghip v i sng ng dng cc gii thut x l nh. Nh trn gii thiu, cc ng dng ny rt phong ph v a dng, c trong lnh vc gii tr (video, cameras), trong lnh vc sn xut (phn loi sn phm), cng nh trong cc vn qun l (nhn dng bin xe, tnh ph giao thng) v trong y hc (chn on bnh). cc nc tin tin, da trn cc cng ngh thit k chip (m FPGA l mt trong s ), ngi ta sn xut ra cc thit b thc hin cc ng dng trn vi kch thc ngy cng nh v kh nng x l v tin cy ngy cng cao. T em li hiu qu kinh t cao trong cng nghip, cng nh p ng ngy cng tt nhu cu ca con ngi. nc ta hin nay, vn phi s dng nhng h thng c kch thc ln nhng tin cy li khng cao. Vi nhng nghin cu v cng ngh thit k da trn FPGA, vn ny c th c ci thin trong tng lai gn. Hin nay, Vit Nam nhiu cng ty cng nghip trong lnh vc thit k chip v ang c u t xy dng, c bit l nh my sn xut chip ca tp on Intel. Cc cng ty ny ang cn mt ngun nhn lc cng ngh cao lm vic trong nhng d n ca mnh. Do , cc sinh vin chuyn ngnh in t - vin thng hin nay rt cn phi trang b cho mnh nhng k nng c bn v cng ngh FPGA: nhng hiu bit v quy trnh thit k, k nng vit chng trnh m t phn cng, k nng kim tra v hiu chnh thit k, Vi nhng ti nh th ny, chng ta s c thm nhiu bi hc cho sinh vin gip h nng cao cc k nng ny.

Hnh 7. S khi thc hin gii thut hun luyn cho mng neuron

- S dng cc k thut khc ci thin chnh xc cho vic tnh hm sigmoid.

w w

.4 t

ec h.

co m
FPGA

- Tip tc thc hin mt s ng dng c th, chng hn: nhn dng v nh v i tng nh, b lc thch nghi, iu khin robot t hnh thch nghi, - T kt qu ca ti, nu c kinh ph c th pht trin tip bng cch thit k cc chip thng minh thc hin nhng chc nng ring bit trong cng nghip, chng hn chc nng phn loi sn phm tc cao, hiu chnh sai s thit b, - a mt s module ca ti ny cng nh thm mt s module khc c thit k tip theo vo phc v cho vic ging dy cc mn hc H thng VLSI (phn k nng lp trnh) v mn hc Th nghim thit k logic s. Ti liu tham kho:

1. Amos R. Omondi, Jagath C. Rajapakse,

implementations of neural networks, Springer, 2006.

V vy, nu chng ta la chn mt s phn c bn t ti ny, chng hn cc gii thut tnh tng tch ly cc tch, x l s du chm ng v tnh, cc module giao tip, a vo ging dy cho sinh vin, kin thc ca sinh vin v cng ngh FPGA, v k nng lp trnh chip s c nng cao hn v c th p ng mt cch y cc nhu cu nhn lc hin nay trong lnh vc ny. Hng pht trin Trn c s nhng kt qu t c cng nh nhng hn ch ca ti, cn tip tc nghin cu cc vn sau:

2. Yu Hen Hu, Jenq-Neng Hwang, Handbook

of neural network signal processing, CRC Press, 2002.

3. Antony W. Savich, Medhat Moussa,

Shawki Areibi, The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study, IEEE transactions on neural networks, VOL. 18, NO. 1, January 2007.

www.4tech.com.vn

-5-

.v

- S dng nh dng s du chm ng tng tm gi tr cng nh tng chnh xc.

www.4tech.com.vn 4. Paul
D. Reynolds, Algorithm

6. Virtex-II Pro and Virtex-II Pro X FPGA

User Guide, Xilinx Inc., 2007.

Implementation in FPGAs Demonstrated Through Neural Network Inversion on the SRC-6e, Baylor University, 2005.

5. Xilinx University Program Virtex-II Pro

Development System Hardware Reference Manual, Xilinx Inc., 2005.

1 2 3

Ging vin Khoa in in t, i hc Tn c Thng. Nh trn. Application Specific Integrated Circuits

www.4tech.com.vn

w w

.4 t
-6-

ec h.

co m

.v