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7th SEM VLSI Lab Programs | Manish Chiniwalar

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26 Nov, 2011 College Lab M anish

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Here are the lab programs for VLSI (VII sem, Electronics and communication) Subject Code : 06ECL77

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7th SEM EC VLSI Lab Programs & Layouts | SIZE:7.04 MB

Part A
1. Inverter
Verilog Code: +e x p a n ds o u r c e TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

2. OR Gate
Verilog Code: +e x p a n ds o u r c e TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

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3. NAND Gate
Verilog Code: +e x p a n ds o u r c e TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

7th SEM VLSI Lab Programs | Manish Chiniwalar

4. D-FlipFlop
Verilog Code: 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 m o d u l em y d f f ( d , c l k , q , q b ) ; i n p u td , c l k ; o u t p u tq , q b ; r e gq , q b ; a l w a y s @ ( p o s e d g ec l k ) b e g i n c a s e ( d ) 1 ' d 0 : q = 0 ; 1 ' d 1 : q = 1 ; e n d c a s e q b = ~ q ; e n d e n d m o d u l e
?

TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

5. T-FlipFlop
Verilog Code: 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 m o d u l em y t f f ( t , q , q b , c l k ) ; i n p u t t , c l k ; o u t p u tq , q b ; r e gq , q b ; i n i t i a lq = 0 ; a l w a y s @ ( p o s e d g ec l k ) b e g i n i f( t = = 1 ) b e g i n q = ~ q ; e n d e l s e b e g i n q = q ; e n d q b = ~ q ; e n d e n d m o d u l e
?

TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

6. JK-FlipFlop
Verilog Code: 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 m o d u l em y j k f f ( j k , c l k , q , q b ) ; o u t p u tq , q b ; i n p u t [ 1 : 0 ]j k ; i n p u tc l k ; r e gq , q b ; a l w a y s@ ( p o s e d g ec l k ) b e g i n c a s e ( j k ) 2 ' d 1 : q = 0 ; 2 ' d 2 : q = 1 ; 2 ' d 3 : q = ~ q ;
?

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1 4 1 5 1 6 1 7 1 8 1 9 2 0

7th SEM VLSI Lab Programs | Manish Chiniwalar

2 ' d 0 : q = q ; e n d c a s e q b = ~ q ; e n d e n d m o d u l e

TestBench Code: 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 ` t i m e s c a l e1 n s / 1 n s m o d u l ej k f f ( j , k , c l k , q , q b ) ; i n p u tj , k ,c l k ; o u t p u tq ,q b ; r e gq , q b ; i n i t i a l b e g i n q = 0 ; q b = 1 ; e n d a l w a y s @( p o s e d g e( c l k ) ) b e g i n i f ( j = = 0& &k = = 0 ) q = 0 ; e l s ei f ( j = = 0& &j = = 1 ) q = 0 ; e l s ei f( j = = 1& &k = = 0 ) q = 1 ; e l s eq = q b ; q b = ~ q ; e n d e n d m o d u l e ` t i m e s c a l e1 n s / 1 n s m o d u l ej k f f _ t b ; r e ga , b , c ; w i r ey , y b ; j k f fo u t( . j ( a ) ,. k ( c ) , . c l k ( b ) ,. q ( y ) ,. q b ( y b ) ) ; i n i t i a l b e g i n c = 0 ; a = 0 ; b = 0 ; # 1 0 0 ; b = 1 ; # 1 0 0 ; a = 1 ; b = 0 ; # 1 0 0 ; b = 1 ; # 1 0 0 ; c = 1 ; a = 0 ; b = 0 ; # 1 0 0 ; a = 0 ; b = 1 ; # 1 0 0 ; a = 1 ; # 1 0 0 ; b = 1 ; # 1 0 0 ; e n d e n d m o d u l e

?

PEX NetList Code: +e x p a n ds o u r c e

7. Full Adder
Verilog Code: 1 2 3 4 5 6 m o d u l ef a ( a , b , c , s , c 1 ) ; i n p u ta , b , c ; o u t p u ts , c 1 ; a s s i g ns = a ^ b ^ c ; a s s i g nc 1 = a & b | ( b & c ) | ( c & a ) ; e n d m o d u l e
?

TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

8. Counter

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Verilog Code: 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 m o d u l eb i n c o u n t ( c l k , c l r , q ) ; i n p u tc l k , c l r ; o u t p u t [ 3 : 0 ]q ; r e g [ 3 : 0 ]q ; i n i t i a lq = 4 ' b 0 0 0 0 ; a l w a y s@ ( p o s e d g ec l k ) b e g i n i f( c l r= =0 ) b e g i n c a s e ( q )

7th SEM VLSI Lab Programs | Manish Chiniwalar

?

4 ' b 0 0 0 0:q = 4 ' b 0 0 0 1 ; 4 ' b 0 0 0 1:q = 4 ' b 0 0 1 0 ; 4 ' b 0 0 1 0:q = 4 ' b 0 0 1 1 ; 4 ' b 0 0 1 1:q = 4 ' b 0 1 0 0 ; 4 ' b 0 1 0 0:q = 4 ' b 0 1 0 1 ; 4 ' b 0 1 0 1:q = 4 ' b 0 1 1 0 ; 4 ' b 0 1 1 0:q = 4 ' b 0 1 1 1 ; 4 ' b 0 1 1 1:q = 4 ' b 1 0 0 1 ; 4 ' b 1 0 0 1:q = 4 ' b 1 0 1 0 ; 4 ' b 1 0 1 0:q = 4 ' b 1 0 1 1 ; 4 ' b 1 0 1 1:q = 4 ' b 1 1 0 0 ; 4 ' b 1 1 0 0:q = 4 ' b 1 1 0 1 ; 4 ' b 1 1 0 1:q = 4 ' b 1 1 1 0 ; 4 ' b 1 1 1 0:q = 4 ' b 1 1 1 1 ; e n d c a s e e n d e l s e q = 4 ' b 0 0 0 0 ; e n d e n d m o d u l e

TestBench Code: +e x p a n ds o u r c e PEX NetList Code: +e x p a n ds o u r c e

Part B
Related Searches: Application Development W ordpress Templates Source Control Software Version Control Software W ordPress Development Free W ordPress Video Tutorials Source Control System Source Control
[Spice NetList code]

1. Inverter
+e x p a n ds o u r c e

2. NOR Gate
+e x p a n ds o u r c e

3. NAND Gate
+e x p a n ds o u r c e

4. Common Source
+e x p a n ds o u r c e

5. OpAmp
+e x p a n ds o u r c e

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Ankur Desai
November 26, 2011 at 6:45 am

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hey thanx a lot

7th SEM VLSI Lab Programs | Manish Chiniwalar

manishchiniwalar
December 8, 2011 at 5:05 am

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