AND Gate

OR Gate

XOR Gate

A F B
INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT F 0 0 0 1

A F B
INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT F 0 1 1 1

A B
INPUT A 0 0 1 1 B 0 1 0 1

F

OUTPUT F 0 1 1 0

NAND Gate

NOR Gate

XNOR Gate

A F B
INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT F 1 1 1 0

A F B
INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT F 1 0 0 0

A F B

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT F 1 0 0 1

TITLE AUTHOR DATE REVISION

Logic Truth Table
SHEET 1 OF 1

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