ESCUELA SUPERIOR POLITCNICA DEL LITORAL

(ESPOL)

FACULTAD DE INGENIERIA EN ELECTRICIDAD Y COMPUTACIN

(FIEC) PROYECTO DE

LAB. DE SISTEMAS DIGITALES

Tema:

CONTADOR DE 4 MODOS
Docente:

Ing. Ronald Ponguillo Intriago

Integrantes:

Burbano Moreira William Pal Gastezzi Pacheco Bruno Cronwel

Paralelo:

8
Grupo:

#13
Fecha de presentacin:

21/06/2012
2012 I TRMINO

CONTADOR DE 4 MODOS
1. ESPECIFICACIN
Este proyecto se trata de un contador de cuatro modos, es decir que muestra cuatro secuencias diferentes dependiendo de los valores que se le asignen a las entradas. Mediante la entrada de habilitacin START, se activa el circuito el cual mediante las entradas de control CNT1 y CNT2 genera la secuencia de conteo, cualquiera de los cuatro modos dependiendo de sus respectivos valores como se muestra a continuacin:
CNT1= CNT2=0 000000 100000 010000 001000 000100 000010 000001 CNT1=0, CNT2=1 000000 000001 000011 000111 001111 011111 111111 CNT1=1, CNT2=0 111111 011111 001111 000111 000011 000001 000000 CNT1=1, CNT2=1 111111 011111 101111 110111 111011 111101 111110

Si durante el desarrollo de una de las secuencias cambia el valor de la entrada de control CNT, el circuito va al estado donde empieza la otra secuencia y la sigue. Si durante el desarrollo de las secuencias el valor de la entrada de control no cambia, el circuito, repite la secuencia en forma indefinida hasta que haya un cambio en la seal de control. Este contador funciona tanto con reloj manual (pulsando un botn), como con reloj automtico (1Hz).

1.1 ENTRADAS START.H: Seal que activa el contador. CNT1.H: Primer bit de control para la secuencia de conteo. CNT2.H: Segundo bit de control para la secuencia de conteo. CLOCK.H: Seal pulsador. SEL.H: Selector para reloj manual y automtico.

2. DIAGRAMA DE BLOQUES. START CNT1 CNT2 SEL CLOCK

SALIDAS

CONTADOR DE 4 MODOS

Q5

LEDS

3. DIAGRAMA ASM
CONTROLADOR_GENERAL:

CONTROLADOR_SECUENCIA1:

CONTROLADOR_SECUENCIA2:

4. DIAGRAMA DE TIEMPO. 4.1 Entrada CNT1=0 y CNT2=0.

4.2 Entrada CNT1=0 y CNT2=1.

4.3 Entrada CNT1=1 y CNT2=0.

4.4 Entrada CNT1=1 y CNT2=1.

5. DIAGRAMA ESQUEMTICO.

6. CDIGO VHDL. 6.1 CONTROLADOR_GENERAL.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity controlador_general is port(Resetn,Clock, Start Ena end controlador_general;

: :

in std_logic; out std_logic);

architecture comportamiento of controlador_general is --Seniales intermediarias type estado is (Ta,Tb); signal y : estado; begin --Diagrama ASM MSS_Transsiciones:Process(Resetn,Clock) begin if Resetn='0' then y<=Ta; elsif Clock'event and Clock='1' then case y is when Ta=> if Start='0' then y<=Ta; else y<=Tb; end if; when Tb=> y<=Tb; end case; end if; end Process; MSS_Salidas:Process (y) begin Ena<='0'; case y is when Ta when Tb end case; end process; End comportamiento;

=> => Ena<='1';

6.2 CONTROLADOR_SECUENCIA1.
--Controlador de la secuencia 1 funcionando library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity controlador_secuencia_1 is port(Resetn,Clock,uno,fin,z : LdCa,EnCa : end controlador_secuencia_1;

in std_logic; out std_logic);

architecture comportamiento of controlador_secuencia_1 is --Seniales intermediarias type estado is (Ta,Tb,Tc); signal y : estado; begin --Diagrama ASM MSS_Transsiciones:Process(Resetn,Clock) begin if Resetn='0' or z='1' then y<=Ta; elsif Clock'event and Clock='1' then case y is when Ta=> if uno='0' then y<=Ta; else y<=Tb; end if; when Tb=> if fin='0' then y<=Tb; else y<=Tc; end if; when Tc=> y<=Ta; end case; end if; end Process; MSS_Salidas:Process (y) begin EnCa<='0'; LdCa<='0'; case y is when Ta => EnCa<='1'; LdCa<='1'; when Tb => EnCa<='1'; when Tc => end case; end process; End comportamiento;

6.3 CONTROLADOR_SECUENCIA2.
--Controlador de secuencia 2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity controlador_secuencia_2 is port(Resetn,Clock,dos,fin2,Z2 LdCb,EnCb end controlador_secuencia_2;

in std_logic; :

out std_logic);

architecture comportamiento of controlador_secuencia_2 is --Seniales intermediarias type estado is (Ta,Tb,Tc); signal y : estado; begin --Diagrama ASM MSS_Transsiciones:Process(Resetn,Clock) begin if Resetn='0' OR Z2='1' then y<=Ta; elsif Clock'event and Clock='1' then case y is when Ta=> if dos='0' then y<=Ta; else y<=Tb; end if; when Tb=> if fin2='0' then y<=Tb; else y<=Tc; end if; when Tc=> y<=Ta; end case; end if; end Process; MSS_Salidas:Process (y) begin EnCb<='0'; LdCb<='0'; case y is when Ta => EnCb<='1'; LdCb<='1'; when Tb => EnCb<='1'; when Tc => end case; end process; End comportamiento;

6.4 REG_SECUENCIA1.
library ieee; use ieee.std_logic_1164.all; entity reg_secuencia1 is port(Resetn,Clock,En,Ld,R1:in std_logic; Fin:out std_logic; Q:buffer std_logic_vector(5 downto 0)); end reg_secuencia1; architecture comportamiento of reg_secuencia1 is begin process(Resetn,Clock) begin if Resetn='0' or (En='0'and Ld='0') then Q<="000000"; elsif (clock'event and clock='1') then if En='1' then if Ld='1' then Q<="100000"; else desplazamiento:for i in 0 to 4 loop Q(i)<=Q(i+1); end loop; Q(5)<=R1; Fin<=Q(0); end if; end if; end if; end process; end comportamiento;

6.5 REG_SECUENCIA2.
library ieee; use ieee.std_logic_1164.all; entity reg_secuencia2 is port(Resetn,Clock,En,Ld,L2:in std_logic; Fin: out std_logic; Q:buffer std_logic_vector(5 downto 0)); end reg_secuencia2; architecture comportamiento of reg_secuencia2 is begin process(Resetn,Clock) begin if Resetn='0' or (En='0' and Ld='0') then Q<="000000";

--if Resetn='0' or (En='0'and Ld='0') then Q<="000000"; elsif (clock'event and clock='1') then if En='1' then if Ld='1' then Q<="000001"; else desplazamiento:for i in 1 to 5 loop Q(i)<=Q(i-1); end loop; Q(0)<=L2; Fin<=Q(5); end if; end if; end if; end process; end comportamiento;

6.6 REG.
library ieee; use ieee.std_logic_1164.all; entity reg is port ( Clock,En:in std_logic; Ent:in std_logic_vector(1 downto 0); Q:out std_logic_vector (1 downto 0)); end reg; architecture comportamiento of reg is begin process(Clock) begin if Clock'event and Clock='1' then if En ='1' then Q <= Ent; --En es la entrada de habilitacion end if; end if; end process; end comportamiento;

6.7 DECODER SIMPLE.

-- DECIDE SI ES UNO DOS TRES CUATRO library ieee; use ieee.std_logic_1164.all; entity decodersimple is port(R: in std_logic_vector(1 downto 0);

Total0:out std_logic; Total1:out std_logic; Total2:out std_logic; Total3:out std_logic); end decodersimple; architecture comportamiento of decodersimple is begin Total0<= '1' when R = "00" else '0'; Total1<= '1' when R = "01" else '0'; Total2<= '1' when R = "10" else '0'; Total3<= '1' when R = "11" else '0'; end comportamiento;

--para 0 --para 1 --para 2 --para 3

6.8 BUSMUX_4a1_6BITS.
library IEEE; use IEEE.STD_LOGIC_1164.all; ENTITY busmux_4a1_6bits IS PORT(A,B,C,D : IN std_logic_vector(5 DOWNTO 0); sel : IN std_logic_vector(1 DOWNTO 0); out1 : OUT std_logic_vector(5 DOWNTO 0)); END busmux_4a1_6bits; ARCHITECTURE synth OF busmux_4a1_6bits IS BEGIN pMux : process (A,B,C,D,Sel) begin case Sel is when "00" => out1 <= A; when "01" => out1 <= B; when "10" => out1 <= C; when others => out1 <= D; end case; end process pMux; END synth;

6.9 MUX2_1.
library ieee; use ieee.std_logic_1164.all;

entity mux2_1 is port(A,B: in std_logic_vector(5 downto 0); Q: out std_logic_vector(5 downto 0); sel: in std_logic); end mux2_1; architecture sol of mux2_1 is begin with sel select Q<=A when '1',B when others; end sol;

6.10

RETARDO2.
library ieee; use ieee.std_logic_1164.all; entity Retardo2 is port(Q:in std_logic_vector(5 downto 0); Fin: out std_logic); end Retardo2; architecture sol of Retardo2 is Begin Fin<=Q(0) AND Q(1) AND Q(2) AND Q(3) AND Q(4) AND Q(5); end sol;

6.11

INVERSOR3.
library ieee; use ieee.std_logic_1164.all; entity inversor3 is port(Resetn,Clock:in std_logic; A:in std_logic_vector(5 downto 0); B: out std_logic_vector(5 downto 0)); end inversor3; architecture comportamiento of inversor3 is begin process(Resetn,Clock) begin if Resetn='0' then B<="000000";

else B(5)<=A(0); B(4)<=A(1); B(3)<=A(2); B(2)<=A(3); B(1)<=A(4); B(0)<=A(5); end if; end process; end comportamiento;

6.12

NEGADOR3.
library ieee; use ieee.std_logic_1164.all; entity negador3 is port(Resetn,Clock:in std_logic; A:in std_logic_vector(5 downto 0); Q3: out std_logic_vector(5 downto 0)); end negador3; architecture comportamiento of negador3 is begin process(Resetn,Clock) begin if Resetn='0' then Q3<="000000"; else Q3(0)<= not A(0); Q3(1)<= not A(1); Q3(2)<= not A(2); Q3(3)<= not A(3); Q3(4)<= not A(4); Q3(5)<= not A(5); end if; end process; end comportamiento;

6.13

NEGADOR4.
library ieee; use ieee.std_logic_1164.all; entity negador4 is port(Resetn,Clock:in std_logic;

A:in std_logic_vector(5 downto 0); Q4: out std_logic_vector(5 downto 0)); end negador4; architecture comportamiento of negador4 is begin process(Resetn,Clock) begin if Resetn='0' then Q4<="111111"; else Q4(0)<= not A(0); Q4(1)<= not A(1); Q4(2)<= not A(2); Q4(3)<= not A(3); Q4(4)<= not A(4); Q4(5)<= not A(5); end if; end process; end comportamiento;

6.14

CLOCK_DIV.
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY CLOCK_DIV IS PORT ( CLOCK_8MHz :IN STD_LOGIC; CLOCK_1MHz :OUT STD_LOGIC; CLOCK_100KHz :OUT STD_LOGIC; CLOCK_10KHz :OUT STD_LOGIC; CLOCK_1KHz :OUT STD_LOGIC; CLOCK_100Hz :OUT STD_LOGIC; CLOCK_10Hz :OUT STD_LOGIC; CLOCK_1Hz :OUT STD_LOGIC); END CLOCK_DIV; ARCHITECTURE a OF CLOCK_DIV IS SIGNAL count_1Mhz: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL count_100Khz, count_10Khz, count_1Khz: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL count_100hz, count_10hz, count_1hz: STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC; SIGNAL clock_100hz_int, clock_10hz_int, clock_1hz_int: STD_LOGIC; BEGIN PROCESS BEGIN -- Divide by 8 WAIT UNTIL clock_8Mhz'EVENT and clock_8Mhz = '1'; -- 8 Mhz IF count_1Mhz < 7 THEN count_1Mhz <= count_1Mhz + 1; ELSE count_1Mhz <= "000"; END IF; IF count_1Mhz < 4 THEN clock_1Mhz_int <= '0'; ELSE clock_1Mhz_int <= '1'; END IF; -- Ripple clocks are used in this code to save prescalar hardware -- Sync all clock prescalar outputs back to master clock signal clock_1Mhz <= clock_1Mhz_int; clock_100Khz <= clock_100Khz_int; clock_10Khz <= clock_10Khz_int; clock_1Khz <= clock_1Khz_int; clock_100hz <= clock_100hz_int; clock_10hz <= clock_10hz_int; clock_1hz <= clock_1hz_int; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1'; IF count_100Khz /= 4 THEN count_100Khz <= count_100Khz + 1; ELSE count_100Khz <= "000"; clock_100Khz_int <= NOT clock_100Khz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1'; IF count_10Khz /= 4 THEN count_10Khz <= count_10Khz + 1; ELSE count_10Khz <= "000";

clock_10Khz_int <= NOT clock_10Khz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1'; IF count_1Khz /= 4 THEN count_1Khz <= count_1Khz + 1; ELSE count_1Khz <= "000"; clock_1Khz_int <= NOT clock_1Khz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1'; IF count_100hz /= 4 THEN count_100hz <= count_100hz + 1; ELSE count_100hz <= "000"; clock_100hz_int <= NOT clock_100hz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1'; IF count_10hz /= 4 THEN count_10hz <= count_10hz + 1; ELSE count_10hz <= "000"; clock_10hz_int <= NOT clock_10hz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1'; IF count_1hz /= 4 THEN count_1hz <= count_1hz + 1; ELSE count_1hz <= "000"; clock_1hz_int <= NOT clock_1hz_int; END IF; END PROCESS; END a;

6.15

ANTIREBOTE.
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; -- Debounce Pushbutton: Filters out mechanical switch bounce for around 40Ms. ENTITY ANTIREBOTE IS PORT(PB_N, CLOCK_100Hz : IN STD_LOGIC; PB_SIN_REBOTE : OUT STD_LOGIC); END ANTIREBOTE; ARCHITECTURE a OF ANTIREBOTE IS SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN -- Debounce clock should be approximately 10ms or 100Hz PROCESS BEGIN WAIT UNTIL (clock_100Hz'EVENT) AND (clock_100Hz = '1'); -- Use a shift register to filter switch contact bounce SHIFT_PB(2 DOWNTO 0) <= SHIFT_PB(3 DOWNTO 1); SHIFT_PB(3) <= NOT PB_N; IF SHIFT_PB(3 DOWNTO 0)="0000" THEN PB_SIN_REBOTE <= '0'; ELSE PB_SIN_REBOTE <= '1'; END IF; END PROCESS; END a;

6.16

RELOJ.
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; -- Single Pulse circuit -- the output will go high for only one clock cycle ENTITY RELOJ IS PORT(PB_SIN_REBOTE, CLOCK : IN STD_LOGIC; UN_PULSO : OUT STD_LOGIC);

END RELOJ; ARCHITECTURE a OF RELOJ IS SIGNAL PB_debounced_delay, Power_on : STD_LOGIC; BEGIN PROCESS BEGIN WAIT UNTIL (CLOCK'event) AND (CLOCK='1'); -- Power_on will be initialized to '0' at power up IF Power_on='0' THEN -- This code resets the critical signals once at power up UN_PULSO <= '0'; PB_debounced_delay <= '1'; Power_on <= '1'; ELSE -- A single clock cycle pulse is produced when the switch is hit -- No matter how long the switch is held down -- The switch input must already be debounced IF PB_SIN_REBOTE = '1' AND PB_debounced_delay = '0' THEN UN_PULSO <= '1'; ELSE UN_PULSO <= '0'; END IF; PB_debounced_delay <= PB_SIN_REBOTE; END IF; END PROCESS; END a;

6.17

SELECTOR.
--RELOJ MANUAL O AUTOMATICO library ieee; use ieee.std_logic_1164.all; entity selector is port(A0,B1 Sel C end selector;

: :

in std_logic; in std_logic; : out std_logic);

architecture comportamiento of selector is Begin

--A es el para 0 --B es para 1 WITH Sel SELECT C <= A0 WHEN '0', B1 WHEN '1', '0' WHEN OTHERS; end comportamiento;

6.18

PUERTA_AND.
library ieee; use ieee.std_logic_1164.all; entity puerta_and is port( A, B: in std_logic; C: out std_logic); end puerta_and; architecture sol of puerta_and is begin C<= A AND B; end sol;

6.19

PUERTA_OR.
library ieee; use ieee.std_logic_1164.all; entity puerta_or is port( A, B: in std_logic; C: out std_logic); end puerta_or; architecture sol of puerta_or is begin C<= A OR B; end sol;

6.20

PUERTA_NOT
library ieee; use ieee.std_logic_1164.all; entity puerta_not is port( A : in std_logic; B: out std_logic); end puerta_not; architecture sol of puerta_not is begin B<= NOT A; end sol;

7 REPORTE DE APROVECHAMIENTO.