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NI DUNG

Chng 1.

Kit DE2 Development and Education Board ................... 20

1.1 Tng quan v Kit DE2.................................................................. 20


1.2 c im ca kit DE2 .................................................................. 20
1.3 Ti liu h tr ............................................................................... 26
1.4 ng dng trong ging dy v hc tp: .......................................... 27
1.5 ng dng trong nghin cu v thit k......................................... 27
1.6 Mt s ng dng minh ha ........................................................... 27
1.6.1 ng dng trong truyn hnh ............................................... 27
1.6.2 ng dng giao tip USB .................................................... 28
1.6.3 ng dng to bi ht karaoke v my nghe nhc ................ 29

Chng 2.

Hng dn s dng Kit DE2 .............................................. 31

2.1 Kim tra Kit DE2 ......................................................................... 31


2.2 Hng dn ci t USB-Blaster Driver ........................................ 32
2.3 Thit lp cu hnh ban u v thay i cu hnh mi cho Cyclon II
FPGA ....................................................................................... 36
2.3.1 Thit lp cu hnh ban u cho FPGA thng qua vic np cu hnh
cho b nh EPPROM EPCS16 bng AS mode: .................. 39
2.4 S mch v hot ng ca cc linh kin trn Kit DE2 ............. 40
2.4.1 Switches (cng tc) v Button (nt nhn) ........................... 40
2.4.2 Leds................................................................................ 43
2.4.3 LED hin th by on........................................................ 45
2.4.4 LED hin th LCD .............................................................. 48
1

2.4.5 Ng vo xung Clock........................................................... 61


2.4.6 Expansion Header (Jac cm m rng) ................................ 62
2.4.7 VGA ............................................................................... 66
2.4.8 Audio CODEC 24-bit ......................................................... 71
2.4.9 Cng ni tip RS-232 ......................................................... 72
2.4.10 Cng ni tip PS/2 ............................................................. 73
2.4.11 Mch iu khin mng Fast Ethernet.................................. 74
2.4.12 TV Decoder........................................................................ 76
2.4.13 TV Encoder ........................................................................ 78
2.4.14 USB Host and Device ........................................................ 79
2.4.15 Cng hng ngoi ................................................................ 81
2.4.16 B nh SDRAM/SRAM/Flash ........................................... 82

Chng 3.
Hng dn ci t v s dng phn mm Control Panel iu
khin kit DE2 ....................................................................................... 89
3.1 Hng dn ci t Control Panel iu khin Kit DE2................... 89
3.2 Tng quan v cu trc v hot ng ca Control Panel ................ 92
3.3 Hng dn s dng Control Panel ................................................ 95
3.3.1 iu khin LEDs, LEDs by on, LCD ............................ 95
3.3.2 Truy xut b nh SDRAM/SRAM ..................................... 96
3.3.3 Truy xut b nh Flash (Flash memory)............................. 99
3.3.4 TOOLS Multi-Port SRAM/SDRAM/Flash Controller ... 102
3.3.5 VGA Display Control....................................................... 103

Chng 4.
Hng dn thit k v thc hnh mn hc H thng s trn Kit
DE2 ........................................................................................ 109
4.1 Hng dn thc hnh ................................................................. 109
4.1.1 To mt project trn Quartus II ........................................ 109
4.1.2 Thit k mt mch in n gin ( cng XOR ) dng Schematic trn
Quartus II: ........................................................................ 115
4.1.3 Gn pin............................................................................. 121
4.1.4 M phng mch thit k : ............................................ 126
4.1.5 Programming mch thit k ln FPGA : ...................... 131
4.2 Ni dung thc hnh mn H thng s ........................................ 135
4.2.1 Bi thc hnh s 1 Switchs, Lights, Multiplexers .......... 135
4.2.2 Bi thc hnh s 2 S v cch hin th .......................... 142
4.2.3 Bi thc hnh s 3 Latch, Flip-flop, Register ................ 150
4.2.4 Bi thc hnh s 4 B m (Counters) .......................... 157
4.2.5 Bi thc hnh s 5 Adder, Subtractor, Multiplier of two signed
numbers in 2s- complement form .................................... 161
Chng 5.
Hng dn thit k v thc hnh mn Thit k mch dng Verilog
HDL trn Kit DE2 .............................................................................. 168
5.1 Hng dn thc hnh ................................................................. 168
5.1.1 To mt project trn Quartus II ........................................ 168
5.1.2 Thit k mt mch in n gin (cng XOR) dng Verilog trn
Quartus II: ........................................................................ 174
5.1.3 Gn pin............................................................................. 180
5.1.4 M phng mch thit k : ............................................ 185
5.1.5 Programming mch thit k ln FPGA : ...................... 190
5.2 Ni dung thc hnh mn Thit k mch vi Verilog HDL ......... 194
3

5.2.1 Bi thc hnh s 1 Thit k mch t hp v mch tun t n gin


......................................................................................... 194
5.2.2 Bi thc hnh s 2 Thc hnh tm hiu thit k latches, flip-flops
v counters. ...................................................................... 198
5.2.3 Bi thc hnh s 3 Thit k h thng s dng xung Clock thi
gian thc .......................................................................... 208
5.2.4 Bi thc hnh s 4 Thc hnh tm hiu thit k s dng State
machine ............................................................................ 210
5.2.5 Bi thc hnh s 5 Thc hnh tm hiu phng php thit k
onchip Memory trn FPGA v phng php s dng offchip
Memory............................................................................ 214

Chng 6.
Hng dn thit k v thc hnh mn Kin trc my tnh nng
cao. ......................................................................................... 227
6.1 Kin thc tng qut v vi x l Nios II ....................................... 227
6.1.1 Gii thiu tng quan Nios II ............................................. 227
6.1.2 Kin trc b x l Nios II................................................. 233
6.1.3 M hnh lp trnh.............................................................. 240
6.2 Hng dn thc hnh trn vi x l Nios II .................................. 273
6.2.1 Nios II System :................................................................ 273
6.2.2 M mt project mi.......................................................... 274
6.3 Ni dung thc hnh mn Kin trc my tnh nng cao ............... 296
6.3.1 Bi thc hnh s 1 Thit k v s dng mt h thng my tnh n
gin .................................................................................. 296
6.3.2 Bi thc hnh s 2 iu khin nhp xut d liu t Vi x
l...301
6.3.3 Bi thc hnh s 3 Tm hiu cch thc hot ng v s dng
Subroutine v Stack ca Vi x l NiosII ........................... 313
4

6.3.4 Bi thc hnh s 4 Tm hiu cch thc hot ng v s dng


Polling v Interrupt ca Vi x l NiosII ............................ 327
6.3.5 Bi thc hnh s 5 Tm hiu cch thc giao tip Bus .... 350

Chng 7.

M phng m t thit k bng ModelSim ......................... 359

7.1 Gii thiu ................................................................................... 359


7.2 M phng pre-synthesis ............................................................. 360
7.3 M phng post-synthesis ............................................................ 372
7.3.1 Dng Quartus to Verilog netlist cho vic m phng postsynthesis ....................................................................... 372
7.3.2 Dng ModelSim chy m phng post-synthesis .......... 375
7.3.3 M li project v waveform chy m phng ................ 389

MC LC HNH
Hnh 1.1 Board mch DE2 ................................................................................... 20
Hnh 1.2 S khi board mch DE2.................................................................. 22
Hnh 1.3 ng dng trong x l nh v truyn hnh ............................................... 28
Hnh 1.4 ng dng giao tip USB ....................................................................... 29
Hnh 1.5 ng dng trong x l m thanh.............................................................. 29
Hnh 2.1 Mn hnh VGA mc nh ...................................................................... 32
Hnh 2.2 Ch v tr driver cho hardware................................................................ 33
Hnh 2.3 Ch ng dn cho driver ...................................................................... 34
Hnh 2.4 Ch ng dn cho driver ...................................................................... 34
Hnh 2.5 Ch ng dn cho driver ...................................................................... 35
Hnh 2.6 Khng cn kim tra driver ..................................................................... 36
Hnh 2.7 Driver c ci t thnh cng ......................................................... 36
Hnh 2.8 Thit lp cu hnh cho FPGA thng qua JTAG mode ............................ 38
Hnh 2.9 Thit lp cu hnh cho FPGA thng qua AS mode ................................ 39
Hnh 2.10 Chc nng chng ny cho Push button ................................................ 40
Hnh 2.11 Mch thit k ca switches v push button .......................................... 41
Hnh 2.12 Mapped pins gia switches v FPGA .................................................. 42
Hnh 2.13 Mapped pins gia Push button v FPGA ............................................. 42
Hnh 2.14 Mch thit k ca Leds ........................................................................ 43
Hnh 2.15 Mapped pins gia LEDs v FPGA ...................................................... 44
Hnh 2.16 Led 7 on .......................................................................................... 45
Hnh 2.17 Mch thit k ca LEDs 7 on ........................................................... 46
Hnh 2.18 Mapped pins gia LEDs 7 on v FPGA ........................................... 48
6

Hnh 2.19 Mch thit k ca LCD ....................................................................... 49


Hnh 2.20 Cu to LCD ....................................................................................... 50
Hnh 2.21 Mapped pins gia LCD v FPGA ........................................................ 50
Hnh 2.22 Thanh ghi iu khin hot ng ca LCD ........................................... 51
Hnh 2.23 B m a ch .................................................................................... 52
Hnh 2.24 B nh lu gi d liu hin th ............................................................ 52
Hnh 2.25 B nh lu gi mu k t .................................................................... 54
Hnh 2.26 B nh lu gi tt c cc mu k t ..................................................... 55
Hnh 2.27 B to mu k t .................................................................................. 56
Hnh 2.28 Tp lnh LCD...................................................................................... 61
Hnh 2.29 Mch thit k ca ng vo xung Clock ................................................ 61
Hnh 2.30 Mapped pins gia ng vo xung Clock v FPGA ................................ 62
Hnh 2.31 Mch thit k giao tip gia PIO v FPGA.......................................... 63
Hnh 2.32 Mapped pins gia pin PIO v FPGA .................................................. 66
Hnh 2.33 S mch VGA ................................................................................ 67
Hnh 2.34 Gin nh thi ca tn hiu HSYNC ............................................... 68
Hnh 2.35 M t nh thi cho vic ng b hng................................................ 69
Hnh 2.36 M t nh thi cho vic ng b ct .................................................. 69
Hnh 2.37 Mapped pins gia ADV7123 v FPGA ............................................... 71
Hnh 2.38 Mch thit k ca Audio Codec........................................................... 72
Hnh 2.39 Mapped pins gia Audio Codec v FPGA ........................................... 72
Hnh 2.40 Mch thit k giao tip gia RS-232 v FPGA .................................... 73
Hnh 2.41 Mapped pins gia RS-232 v FPGA.................................................... 73
Hnh 2.42 Mch thit k giao tip gia cng PS/2 v FPGA ................................ 74
Hnh 2.43 Mapped pins gia cng PS/2 v FPGA................................................ 74
Hnh 2.44 Mch thit k giao tip gia DM9000A v FPGA ............................... 75
7

Hnh 2.45 Mapped pins gia DM9000A v FPGA............................................... 76


Hnh 2.46 Mch thit k giao tip gia ADV7181 v FPGA................................ 77
Hnh 2.47 Mapped pins gia ADV7181 v FPGA ............................................... 78
Hnh 2.48 TV encoder ADV7123 v FPGA ......................................................... 79
Hnh 2.49 Mch thit k giao tip USB gia chip ISP1362 v FPGA .................. 80
Hnh 2.50 Mapped pins gia ISP1362 v FPGA .................................................. 81
Hnh 2.51 Mch giao tip gia cng hng ngoi v FPGA .................................. 82
Hnh 2.52 Mapped pins gia cng hng ngoi v FPGA...................................... 82
Hnh 2.53 Mch giao tip thit k gia DRAM v FPGA .................................... 83
Hnh 2.54 Mch giao tip thit k gia SRAM v FPGA ..................................... 83
Hnh 2.55 Mch giao tip thit k gia FLASH v FPGA ................................... 84
Hnh 2.56 Mapped pins gia SDRAM v FPGA.................................................. 85
Hnh 2.57 Mapped pins gia SRAM v FPGA .................................................... 87
Hnh 2.58 Mapped pins gia FLASH v FPGA ................................................... 88

Hnh 3.1 Giao din cho vic cu hnh thit k ln FPGA ..................................... 90
Hnh 3.2 Giao din Control Panel ........................................................................ 91
Hnh 3.3 Giao tip gia Control Panel v cc thit b ngoi vi trn FPGA ........... 92
Hnh 3.4 S khi giao tip gia Control Panel v cc thit b ngoi vi ............ 94
Hnh 3.5 Giao din Control Panel iu khin LEDs 7 on ................................. 95
Hnh 3.6 Giao din Control Panel iu khin LEDs n ...................................... 96
Hnh 3.7 Giao din Control Panel iu khin SDRAM ........................................ 97
Hnh 3.8 Giao din Control Panel iu khin FLASH .........................................100
Hnh 3.9 Giao din Control Panel iu khin Multi-Ports ...................................102
Hnh 3.10 Giao din Control Panel iu khin VGA...........................................103
Hnh 3.11 Giao din Control Panel iu khin Multi-ports .................................105
8

Hnh 3.12 Cu hnh trn FPGA ca Multi-ports ..................................................105


Hnh 3.13 Mn hnh VGA...................................................................................106
Hnh 3.14 Trnh bin i nh ..............................................................................107
Hnh 3.15 Gi tr ngng ca nh .......................................................................108

Hnh 4.1 Mn hnh chnh ca Quartus.................................................................109


Hnh 4.2 Tab File ................................................................................................110
Hnh 4.3 To project ...........................................................................................110
Hnh 4.4 Ch ng dn v tn project................................................................111
Hnh 4.5 ng dn cha tn ti ........................................................................111
Hnh 4.6 Add cc file s dng trong project........................................................112
Hnh 4.7 Chn thit b FPGA ..............................................................................112
Hnh 4.8 Thit lp EDA tool ...............................................................................113
Hnh 4.9 Hon thnh vic to project ..................................................................114
Hnh 4.10 Mn hnh chnh sau khi to project hon thnh...................................114
Hnh 4.11 Thit k mt mch s n gin ...........................................................115
Hnh 4.12 Chn cng c thit k .........................................................................115
Hnh 4.13 Ca s thit k mch s ......................................................................116
Hnh 4.14 Lu thit k ........................................................................................116
Hnh 4.15 Chn linh kin ....................................................................................117
Hnh 4.16 Cc linh kin c chn ................................................................118
Hnh 4.17 t tn pin cho thit k.......................................................................118
Hnh 4.18 Thit k hon chnh ............................................................................119
Hnh 4.19 Ca s trnh bin dch report ..............................................................120
Hnh 4.20 Ca s mapped pin gia thit k v FPGA .........................................122
Hnh 4.21 Ca s gn pin....................................................................................122
9

Hnh 4.22 Ca s lit k danh sch pin ca FPGA ..............................................123


Hnh 4.23 Ca s sau gn pin .............................................................................123
Hnh 4.24 Dng Microsoft Excel to file gn pin ...........................................124
Hnh 4.25 Import file gn pin ..............................................................................125
Hnh 4.26 File gn pin to sn bi Altera ............................................................126
Hnh 4.27 To waveform ....................................................................................127
Hnh 4.28 Ca s to waveform..........................................................................127
Hnh 4.29 Nhp tn signal ca thit k ................................................................128
Hnh 4.30 Dng chc nng Node Finder .............................................................128
Hnh 4.31 To input waveform ...........................................................................129
Hnh 4.32 To mc logic "1" ..............................................................................129
Hnh 4.33 Mc logic "1" c to ..................................................................130
Hnh 4.34 Thit lp ch ch simulation ...............................................................130
Hnh 4.35 Waveform sau khi chy m phng .....................................................131
Hnh 4.36 Np thi k ln FPGA ........................................................................132
Hnh 4.37 Thit lp cng giao tip gia kit DE2 v Computer ............................132
Hnh 4.38 Chn cu hnh np thit k .................................................................133
Hnh 4.39 Thit k ch np ln FPGA bng AS mode....................................133
Hnh 4.40 Chn loi ROM tng ng .................................................................134
Hnh 4.41 Chn file thit k .pof .........................................................................135
Hnh 4.42 Thit k n gin................................................................................136
Hnh 4.43 Mch s n gin ...............................................................................136
Hnh 4.44 Mch gm 8 MUX 2-1 .......................................................................137
Hnh 4.45 Mch 8 MUX 2-1 vi SW v LED .....................................................138
Hnh 4.46 Mch chn knh .................................................................................139
Hnh 4.47 Mch chn knh 3 input .....................................................................139
10

Hnh 4.48 Mch gii m HEX.............................................................................140


Hnh 4.49 Bng gii m ......................................................................................140
Hnh 4.50 Mch chn knh v hin th ................................................................141
Hnh 4.51 Mode hin th .....................................................................................142
Hnh 4.52 Ca s to Symbol .............................................................................143
Hnh 4.53 Mch gii m hin th HEXA .............................................................144
Hnh 4.54 Mch hin th t 0 n 15 ...................................................................145
Hnh 4.55 Mch FA ............................................................................................146
Hnh 4.56 Mch cng FA 4 bit ............................................................................147
Hnh 4.57 Mch latch..........................................................................................150
Hnh 4.58 Gin xung input ca mch latch RS ...............................................151
Hnh 4.59 mch D latch ......................................................................................152
Hnh 4.60 Gin xung input ca D latch ..........................................................152
Hnh 4.61 Mch D-Flipflop.................................................................................153
Hnh 4.62 Gin xung input D Flipflop............................................................154
Hnh 4.63 Latch v Flipflop ................................................................................155
Hnh 4.64 Gin xung input .............................................................................156
Hnh 4.65 Bng ni dung hin th .......................................................................160
Hnh 4.66 Mch cng hai s c du b 2 ............................................................162
Hnh 4.67 Mch cng hai s c du b 2 ............................................................164
Hnh 4.68 Mch nhn hai s c du b 2 ............................................................165

Hnh 5.1 Mn hnh chnh Quartus .......................................................................168


Hnh 5.2 Tab File ................................................................................................169
Hnh 5.3 To project mi ....................................................................................169
Hnh 5.4 Nhp ng dn v tn project .............................................................170
11

Hnh 5.5 ng dn cha tn ti ........................................................................170


Hnh 5.6 Add cc file lin quan n project ........................................................171
Hnh 5.7 Chn tn FPGA ....................................................................................171
Hnh 5.8 Thit lp thng s EDA ........................................................................172
Hnh 5.9 Project mi c to ............................................................................173
Hnh 5.10 Ca s Quartus sau khi project mi c to .....................................173
Hnh 5.11 Mch s n gin ...............................................................................174
Hnh 5.12 Chn mi trng thit k Verilog .......................................................174
Hnh 5.13 Ca s thit k Verilog .......................................................................175
Hnh 5.14 Lu thit k ........................................................................................175
Hnh 5.15 M t thit k .....................................................................................176
Hnh 5.16 Chn template Verilog .......................................................................176
Hnh 5.17 Add file Verilog lin quan ..................................................................177
Hnh 5.18 Ch ng dn ....................................................................................178
Hnh 5.19 Ca s sau qu trnh bin dch ............................................................179
Hnh 5.20 Ca s mapped pin gia thit k v FPGA .........................................181
Hnh 5.21 Ca s gn pin....................................................................................181
Hnh 5.22 Ca s lit k danh sch pin ca FPGA ..............................................182
Hnh 5.23 Ca s sau gn pin .............................................................................182
Hnh 5.24 Dng Microsoft Excel to file gn pin ...........................................183
Hnh 5.25 Import file gn pin ..............................................................................184
Hnh 5.26 File gn pin to sn bi Altera ............................................................185
Hnh 5.27 To waveform ....................................................................................186
Hnh 5.28 Ca s to waveform..........................................................................186
Hnh 5.29 Nhp tn signal ca thit k ................................................................187
Hnh 5.30 Dng chc nng Node Finder .............................................................187
12

Hnh 5.31 To input waveform ...........................................................................188


Hnh 5.32 To mc logic "1" ..............................................................................188
Hnh 5.33 Mc logic "1" c to ..................................................................189
Hnh 5.34 Thit lp ch ch simulation ...............................................................189
Hnh 5.35 Waveform sau khi chy m phng .....................................................190
Hnh 5.36 Np thi k ln FPGA ........................................................................191
Hnh 5.37 Thit lp cng giao tip gia kit DE2 v Computer ............................191
Hnh 5.38 Chn cu hnh np thit k .................................................................192
Hnh 5.39 Thit k ch np ln FPGA bng AS mode....................................192
Hnh 5.40 Chn loi ROM tng ng .................................................................193
Hnh 5.41 Chn file thit k .pof .........................................................................194
Hnh 5.42 Mt mch latch RS .............................................................................199
Hnh 5.43 Mch thc hin trn FPGA cho mch RS latch ..................................201
Hnh 5.44 Mch D latch ......................................................................................202
Hnh 5.45 Mch master-slave D flipflop .............................................................203
Hnh 5.46 Mch v dng sng ng vo cho phn 4 .............................................204
Hnh 5.47 Mt b m ng b 4 bit ..................................................................206
Hnh 5.48 Dng Tool to Mega Wizard ..............................................................215
Hnh 5.49 To mt Mega mi .............................................................................216
Hnh 5.50 Chn cc thng s nh hnh v ...........................................................217
Hnh 5.51 Chn thng s nh trn hnh ..............................................................218
Hnh 5.52 Gn registers cho inputs .....................................................................219
Hnh 5.53 Khng to gi tr ban u cho SRAM .................................................219
Hnh 5.54 Simulation library...............................................................................220
Hnh 5.55 Chn cc loi d liu cn to ra ..........................................................221
Hnh 5.56 Add d liu to ra vo project hin hnh ............................................221
13

Hnh 5.57 M t verilog ca SRAM va to ra ...................................................222

Hnh 6.1 Mt v d v h thng x l Nios II ......................................................228


Hnh 6.2 S khi Nios II processor ................................................................234
Hnh 6.3 Mch m t phn cng cc thanh ghi phc v ngt ..............................252
Hnh 6.4 Cu trc ca Stack Pointer ...................................................................266
Hnh 6.5 nh dng t lnh loi I ........................................................................267
Hnh 6.6 nh dng t lnh loi R ......................................................................268
Hnh 6.7 nh dng t lnh loi J........................................................................268
Hnh 6.8 Nios system ..........................................................................................273
Hnh 6.9 Nios system n gin ...........................................................................274
Hnh 6.10 To project .........................................................................................275
Hnh 6.11 t tn cho Nios system .....................................................................275
Hnh 6.12 Ca s SOPC .....................................................................................276
Hnh 6.13 Chn processor ...................................................................................276
Hnh 6.14 Quay v SOPC Builder.......................................................................277
Hnh 6.15 Chn On-Chip memory ......................................................................278
Hnh 6.16 Quay v SOPC Builder.......................................................................279
Hnh 6.17 Chn PIO ...........................................................................................279
Hnh 6.18 Quay v SOPC Builder.......................................................................280
Hnh 6.19 Chn JTAG UART.............................................................................281
Hnh 6.20 Quay v SOPC Builder.......................................................................281
Hnh 6.21 Thay i c tnh cho Processor .........................................................282
Hnh 6.22 Thay i Exception Vector .................................................................283
Hnh 6.23 To verilog files cho nios system .......................................................283
Hnh 6.24 Top-level module ...............................................................................284
14

Hnh 6.25 Programmer........................................................................................285


Hnh 6.26 Ca s programmer ............................................................................286
Hnh 6.27 Gi ca s ny trong sut qu trnh np FPGA ..................................286
Hnh 6.28 Chng trnh assemble n gin ........................................................287
Hnh 6.29 Ca s Altera Monitor Program .........................................................288
Hnh 6.30 Thit lp cu hnh ...............................................................................288
Hnh 6.31 Chn file chng trnh .......................................................................289
Hnh 6.32 Ca s Debug .....................................................................................290
Hnh 6.33 Chng trnh dng C ..........................................................................291
Hnh 6.34 To Breakpoints .................................................................................292
Hnh 6.35 Thit lp iu kin to Breakpoints ....................................................293
Hnh 6.36 Thanh ghi Registers ............................................................................294
Hnh 6.37 Vng nh ca On-Chip memory.........................................................295
Hnh 6.38 Thay i ni dung nh.....................................................................295
Hnh 6.39 SOPC Builder.....................................................................................296
Hnh 6.40 Based address ca cc components.....................................................303
Hnh 6.41 Thit lp thng s cho PIO .................................................................305
Hnh 6.42 Thit lp thng s ng b cho Input Port ..........................................306
Hnh 6.43 i thng s trn ca s SOPC Builder..............................................306
Hnh 6.44 Mapping gia Based address trn SOPC vi address trong program ..311
Hnh 6.45 Based address .....................................................................................317
Hnh 6.46 Load ni dung cho b nh ..................................................................317
Hnh 6.47 Ni dung c load vo b nh .....................................................318
Hnh 6.48 Nios System .......................................................................................324
Hnh 6.49 S khi ca JTAG UART..............................................................328
Hnh 6.50 Chn v thit lp thng s cho JTAG UART .....................................330
15

Hnh 6.51 Chn v thit lp thng s cho timer ..................................................331


Hnh 6.52 Chn interrupt request ........................................................................331
Hnh 6.53 JTAG UART Core Register Map .......................................................333
Hnh 6.54 Data Register Bits ..............................................................................333
Hnh 6.55 Control Register Bits ..........................................................................333
Hnh 6.56 S chu k cho mi lnh .......................................................................335
Hnh 6.57 S chu k cho mi lnh .......................................................................336
Hnh 6.58 S chu k cho mi lnh .......................................................................337
Hnh 6.59 Exception Vector ................................................................................340
Hnh 6.60 Thanh ghi ca Timer ..........................................................................345
Hnh 6.61 M hnh Nios System dng Avalon to External Bus Bridge ...............351
Hnh 6.62 Gin xung hot ng ca SRAM ...................................................352
Hnh 6.63 Giao tip LED 7 on.........................................................................353
Hnh 6.64 Connection gia cc components .......................................................354
Hnh 6.65 Giao tip vi RAM .............................................................................355
Hnh 6.66 Giao tip vi RAM v LED 7 on ....................................................357

Hnh 7.1 Ca s ModelSim .................................................................................360


Hnh 7.2 Ca s to project mi .........................................................................361
Hnh 7.3 Ca s in thng tin cho project .........................................................361
Hnh 7.4 To new file .........................................................................................362
Hnh 7.5 in thng tin cho new file ..................................................................362
Hnh 7.6 Ca s sau khi to project ....................................................................363
Hnh 7.7 Ca s dng cho m t thit k.............................................................363
Hnh 7.8 M t thit k D-Flipflop......................................................................364
Hnh 7.9 To new file .........................................................................................364
16

Hnh 7.10 M t Testbench cho thit k ..............................................................365


Hnh 7.11 Lu m t testbench ...........................................................................365
Hnh 7.12 Add file Testbench vo project ...........................................................366
Hnh 7.13 Ch ng dn n file Testbench ......................................................366
Hnh 7.14 Ca s Workspace sau thit k ...........................................................366
Hnh 7.15 Compile thit k .................................................................................367
Hnh 7.16 Compile thnh cng ...........................................................................367
Hnh 7.17 Thit lp m phng ............................................................................368
Hnh 7.18 Chn thit k cn m phng ...............................................................368
Hnh 7.19 Chn tn hiu dng sng cn quan st .................................................369
Hnh 7.20 Ca s dng sng ...............................................................................370
Hnh 7.21 Thit lp thi gian chy m phng .....................................................370
Hnh 7.22 Chy m phng ..................................................................................370
Hnh 7.23 Nhn "No" ..........................................................................................371
Hnh 7.24 Dng sng sau m phng ...................................................................371
Hnh 7.25 M t thit k D-Flipflop....................................................................372
Hnh 7.26 Thit lp thng s cho qu trnh synthesis ..........................................373
Hnh 7.27 Thit lp thng s ...............................................................................374
Hnh 7.28 Th mc sau qu trnh synthesis.........................................................375
Hnh 7.29 Hai file quan trng c to ra ...........................................................375
Hnh 7.30 Ca s ModelSim ...............................................................................376
Hnh 7.31 To project mi ..................................................................................376
Hnh 7.32 in thng tin cho project mi ...........................................................377
Hnh 7.33 Add file thit k c sn .......................................................................378
Hnh 7.34 Ch ng dn n file Verilog netlist ................................................378
Hnh 7.35 To file m t thit k mi .................................................................378
17

Hnh 7.36 in thng tin cho new file ................................................................379


Hnh 7.37 Ca s m t thit k c m ra .......................................................379
Hnh 7.38 M t Testbench cho thit k ..............................................................380
Hnh 7.39 Compile thit k .................................................................................380
Hnh 7.40 M t thit k thnh cng ...................................................................381
Hnh 7.41 Thit lp m phng ............................................................................381
Hnh 7.42 Ca s thit lp m phng ..................................................................382
Hnh 7.43 Ch Libraries cho thit k ...................................................................383
Hnh 7.44 File SDF c gi trong Verilog netlist..............................................384
Hnh 7.45 Chn thit k cn chy m phng .......................................................385
Hnh 7.46 Ca s waveform m ra .....................................................................385
Hnh 7.47 Chn tn hiu cn xem waveform .......................................................386
Hnh 7.48 Ca s dng sng m phng...............................................................387
Hnh 7.49 Thit lp thi gian chy m phng ....................................................387
Hnh 7.50 Chy m phng ..................................................................................387
Hnh 7.51 Nhn "No" ..........................................................................................388
Hnh 7.52 Dng sng sau m phng ...................................................................388
Hnh 7.53 M li project .....................................................................................390
Hnh 7.54 Ch ng dn project cn m............................................................390
Hnh 7.55 Ca s Transcript ...............................................................................391
Hnh 7.56 Nhp dng lnh nh trn ....................................................................391
Hnh 7.57 Nhp dng lnh nh trn ....................................................................391
Hnh 7.58 Nhp dng lnh nh trn ....................................................................392

18

MC LC BNG
Bng 6.1 Thao tc h tr bi Nios II ALU ..........................................................235
Bng 6.2 Cc thanh ghi a dng ca NIOS II......................................................242
Bng 6.3 Cc bit v tn ca thanh ghi iu khin ................................................244
Bng 6.4 Cho bit chi tit cc trng c nh ngha trong thanh ghi status .....245
Bng 6.5 Cc trng ca thanh ghi iu khin estatus ........................................247
Bng 6.6 Cc trng ca thanh ghi iu khin bstatus ........................................247
Bng 6.7 Nhm lnh chuyn d liu ...................................................................256
Bng 6.8 Lnh logic v s hc ............................................................................257
Bng 6.9 Cc lnh di chuyn...............................................................................259
Bng 6.10 Cc lnh so snh ................................................................................260
Bng 6.11 Lnh dch v xoay ..............................................................................261
Bng 6.12 Nhm lnh nhy v gi hm khng iu kin ....................................262
Bng 6.13 Nhm lnh nhy c iu kin .............................................................263
Bng 6.14 Nhm lnh iu khin khc................................................................264
Bng 6.15 Cc kiu d liu Nios II .....................................................................264
Bng 6.16 M ha trng OP ca cc t lnh .....................................................269
Bng 6.17 M ha trng OPX ca cc t lnh loi R ........................................270
Bng 6.18 Danh sch cc lnh v lnh tng ng ...........................................271
Bng 6.19 Danh sch cc macro hin hnh .........................................................272

19

Chng 1.

Kit DE2 Development and Education Board

1.1 Tng quan v Kit DE2


Mc ch ca Kit DE2 l cung cp cho sinh vin mt phng tin ti u
nghin cu v k thut s, cu trc my tnh v FPGA. Kit ny s dng nhng cng
ngh mi nht c v phn cng ln cng c CAD (Computer Aid Design) gip
khng ch sinh vin m cn c gio vin c th nghin cu c nhiu ng dng
khc nhau. Kit cung cp nhiu c im ph hp cho cng vic nghin cu cng
nh pht trin nhng h thng s thng thng ln phc tp trong phng th
nghim ca cc trng i hc.

1.2 c im ca kit DE2


Di y l hnh nh ca Kit DE2. N th hin b mt trn ca Kit cng nh
v tr ca nhng linh kin trn Kit.

Hnh 1.1 Board mch DE2


Kit DE2 mang nhng c im cho php ngi s dng c th thit k t
nhng mch in n gin cho n nhng thit k phc tp nh multimedia.
20

Kit DE2 gm nhng linh kin chnh sau:


Chip Cyclone II 2C35 FPGA 672 pins. Tt c nhng linh kin trn kit
u c kt ni sn vi nhng pin ca FPGA, iu ny cho php ngi s dng
c th iu khin tt c nhng linh kin cng nh ng dng ca chng.
Rom EPCS16 Dng thit lp cu hnh ban u cho thit b, hot
ng ni tip.
USB Blaster Dng ci t chng trnh t computer cho FPGA, h
tr hai mode : JTAG v AS ( Active Serial ).
512 Kbyte SRAM
8 Mbyte SDRAM
4 Mbyte Flash memory
Khe cm th nh SD card.
18 toggle switches
4 push-button switches
18 red LEDs
9 green LEDs
LED 7 on (7-segments displays)
LED hin th k t dng LCD (16x2 character displays)
Ngun xung clock 50 MHz v 27 MHz.
24-bit CD-quality audio CODEC vi nhng u cm line-in, line-out, v
microphone-in.
VGA DAC (10-bit high-speed triple DACs) vi u cm VGA-out.
TV Decoder ( NTSC/PAL) vi u cm TV-in.
Giao tip chun RS-232 vi u cm 9 pin.
Giao tip chun PS/2 cho chut v bn phm.
Giao tip USB 2.0 ( c host ln device )
21

Giao tip Ethernet 10/100


Giao tip hng ngoi ( IrDA)
Hai cng kt ni ( header) dng giao tip vi nhng thit b ngoi vi
khc m ngi s dng mun kt ni vo Kit.
i km vi nhng c tnh phn cng, Altera cng cung cp nhng giao tip
I/O chun v bng iu khin vic truy xut nhng linh kin trn Kit da trn phn
mm DE2 Control Panel.
Hnh 1.2 m t s khi ca Kit DE2:

Hnh 1.2 S khi board mch DE2


Cyclone II 2C35 FPGA
 33216 Les
 105 M4K RAM blocks
 483840 RAM bits
22

 35 embedded multipliers
 4 PLLs
 475 I/O pins
 FineLine BGA 672-pin package.
Serial Configuration device v USB Blaster circuit
 Rom EPCS16 Serial Configuration device
 USB Blaster for programing v user API control
 JTAG v AS programming modes
SRAM:
 512- Kbyte SRAM memory chip
 c t chc nh l 256K x 16 bits
 C th truy cp nh l b nh cho vi x l Nios II hoc truy cp
thng qua bng iu khin Control Panel.
SDRAM:
 8-Mbyte Single Data Rate Synchronous Dynamic RAM.
 c t chc nh l 1M x 16 bits x 4 banks
 C th truy cp nh l b nh cho vi x l Nios II hoc truy cp
thng qua bng iu khin Control Panel.
Flash memory:
 4-Mbyte NOR Flash memory
 8-bit data bus
 C th truy cp nh l b nh cho vi x l Nios II hoc truy cp
thng qua bng iu khin Control Panel.
Khe cm th nh SD card:
 Truy xut SD card bng mode SPI

23

 C th truy cp nh l b nh cho vi x l Nios II vi DE2 SD


card driver.
Pushbutton swiches:
 4 pushbutton switches
 Hi phc li tn hiu bng mch Schmitt trigger.
 trng thi bnh thng, tn hiu mc cao; khi switch c
nhn, tn hiu to ra mt xung tch cc mc thp v hi phc li
trng thi bnh thng mc cao.
Toggle switches:
 18 toggle switches
 Khi switch v tr DOWN ( gn cnh ca Kit DE2 ) th tn hiu
mc thp; ngc li th tn hiu mc cao.
Clock inputs:
 Ngun xung clock 50 MHz
 Ngun xung clock 27 MHz
 C th s dng ngun xung clock ngoi thng qua chn SMA.
Audio CODEC:
 Wolfson WM8731 24-bit sigma-delta audio CODEC
 u cm Line-in, Line-out, Microphone-in
 Tn s ly mu : 8-96 KHz
 ng dng cho MP3 players, recorders, PDAs, smart phones,
voice recorders
VGA output:
 S dng ADV7123 240-MHz triple 10-bit high-speed video
DAC
 Vi u cm 15-pin high-density D-sub
24

 H tr phn gii 1600x1200 ti 100-Hz refresh rate.


 C th kt hp vi Cyclone II FPGA thc thi mt TV
Encoder tc cao.
NTSC/PAL TV decoder circuit :
 S dng ADV7181B Multi-format SDTV Video Decoder
 H tr NTSC-(M,J,4.43), PAL-(B/D/G/H/I/M/N), SECAM
 Tch hp 3 ADC 9-bit 54-MHz
 Hot ng vi ngun xung clock 27-MHz
 H tr Composite Video (CVBS) RCA jack input
 H tr ng ra digital (8-bit/16-bit): ITU-R BT.656 YcrCb 4:2:2
ouput + HS, VS, FIELD
 ng dng: DVD recoders, LCD TV, Digital TV, Portable Video
devices, Set-top boxes.
B iu khin 10/100 Ethernet
 Tch hp MAC and PHY vi giao tip vi x l thng thng.
 H tr ng truyn 100Base-T v 10Base-T
 H tr hot ng kp ti 10Mb/s v 100Mb/s vi auto-MDIX
 Hon ton tng thch vi cu hnh IEEE 802.3u
 H tr IP/TCP/UPD checksum generation v checking
 H tr back-pressure mode for half-duplex mode flow control.
USB Host/Slave controller
 USB 2.0
 H tr truyn data vi high-speed v low-speed.
 H tr USB ch/t.
 Hai cng USB ( Cng A cho ch v Cng B cho t).

25

 Cung cp giao tip song song n b vi x l; h tr Nios II bi


Terasic driver.
 H tr Programmed I/O (PIO) v Direct Memory Access
(DMA).
Cng ni tip :
 Mt cng giao tip RS-232
 Mt cng giao tip PS/2
Cng giao tip hng ngoi ( IrDA)
 B truyn nhn tn hiu 115.2 kb/s
 Dng iu khin LED 32 mA
 c bo v bi mt lp EMI
 IEC825-1 Class 1 eye safe
 Tn hiu ng vo c xc nhn bi tch cc cnh.
Hai u ni m rng ( 40 pin)
 2x40 pin ca 2 u ni c kt ni vi 72 pin ca Cyclone II
I/O pins v 8 pin power v mass.
 u ni 40 pin ny c th tng thch vi cable chun 40 pin
c dng cho cng IDE.
 c bo v bi diode v in tr.

1.3 Ti liu h tr
Phn mm i km vi Kit DE2 bao gm Quartus II Web Edition CAD v
Nios II Embedded Processor. Ngoi ra mt s hng dn v ng dng n gin
gip sinh vin v gio vin hiu r v ng dng ca Kit trong ging dy v nghin
cu.
Thng thng nhng Kit FPGA c sn xut cho mc ch gio dc s
cung cp nhiu c tnh v phn cng cng nh cng c CAD c th to ra
26

nhiu ng dng trn Kit, nhng c rt t ti liu hng dn c km theo cho mc


ch ging dy. u im ca Kit DE2 l, ngoi phn cng v phn mm, Altera
cn cung cp nhng bi thc hnh vi nhng kha hc c th nh H thng s,
Cu trc my tnh. iu ny gip sinh vin trong cc trng i hc nhanh tip
cn hn vi nhng cng ngh mi c trnh by trong nhng lp l thuyt.

1.4 ng dng trong ging dy v hc tp:


Nhng kha hc v thit k mch logic v cu trc my tnh thng cp
n nhng thit b v linh kin in t. Ngy nay khi m cng ngh ang pht trin
vi tc chng mt th nhng gio trnh cng nh nhng thit b trong cc phng
th nghim cng phi lun c cp nht nhng cng ngh v cng c thit k hin
i nht, tuy nhin n vn phi m bo gip sinh vin nm vng nhng kin thc
nn tng cho n nhng kin thc cao hn. Kit DE2 c thit k p ng c
tt c nhng yu cu trn.

1.5 ng dng trong nghin cu v thit k


Vi Chip Cyclone II FPGA tn tin, nhiu loi giao tip I/O v nhiu loi
memory khc nhau, Kit DE2 s gip ngi s dng rt linh ng trong vic thit
k nhiu loi ng dng khc nhau. Cng vi nhng ng dng minh ha km theo
Kit, ngi thit k c th to ra nhng th nghim th v v nhng ng dng nh l
audio, video, USB, network v memory. Kit DE2 cng c th thc thi c nhng
ng dng nhng s dng vi x l Nios II.

1.6 Mt s ng dng minh ha


1.6.1

ng dng trong truyn hnh

27

Hnh 1.3 ng dng trong x l nh v truyn hnh

B gii m TV cht lng cao


Audio CD 24 bit cht lng cao
VGA monitor
To mt nn thit k cho nhng ng dng trn video
1.6.2

ng dng giao tip USB

28

Hnh 1.4 ng dng giao tip USB

S dng giao tip USB trn Kit DE2.


S dng trnh iu khin thit b ch v t cho Nios II
Cung cp minh ha v SRAM video buffer.
1.6.3

ng dng to bi ht karaoke v my nghe nhc

Hnh 1.5 ng dng trong x l m thanh


CD audio 24 bit cht lng cao
29

To mt nn thit k cho nhng ng dng trn audio.

30

Chng 2.

Hng dn s dng Kit DE2

2.1 Kim tra Kit DE2


Khi m ngun trn Kit DE2, mt chng trnh c khi to sn
s c np ln FPGA, chng trnh ny th hin mt s c tnh ca Kit. Chng
trnh ny cng gip ngi s dng kim tra Kit c hot ng hay khng. m
ngun v kim tra Kit, ta thc hin nhng bc sau:
i.

Kt ni dy cp USB t my tnh cha phn mm Quartus II n cng


giao tip USB Blaster trn Kit DE2. c th giao tip gia my tnh
v Kit DE2 thng qua cp USB ny, ta cn phi ci t trnh iu
khin (driver) Altera USB Blaster.

ii.

Kt ni ngun 9V n Kit DE2.

iii.

Kt ni mn hnh my tnh n cng giao tip VGA trn Kit DE2.

iv.

Kt ni headphone vo cng giao tip Audio Line-out trn Kit DE2.

v.

Bt switch RUN/PROG trn Kit DE2 v v tr RUN; v tr PROG ch


c dng khi np chng trnh cho mode AS (Active Serial).

vi.

Bt power ca Kit DE2 bng cch nhn switch ON/OFF.

Sau khi bt power, nu Kit DE2 khng c vn g th ta c th quan st


nhng hin tng sau:
Tt c LED nhp nhy.
Tt c LED by on hin th s t 0 F theo chu k lp li.
Mn hnh LCD hin th dng ch : Welcome to the Altera DE2 Board
Mn hnh my tnh (VGA) hin th hnh nh sau:

31

Hnh 2.1 Mn hnh VGA mc nh


Bt switch SW17 xung v tr DOWN, ta s nghe mt m thanh tn
s 1-KHz
Bt switch SW17 ln v tr UP v kt ni u ra ca my nghe nhc (
radio, ipod, MP3 ) vo cng giao tip Line-in trn Kit DE2; Sau khi
kt ni xong, ta s nghe c m thanh ca my nghe nhc thng qua
headphone kt ni vo Line-out trc .
Ta c th kt ni mt microphone vo cng giao tip Microphone-in
trn Kit DE2; t headphone ta c th nghe c ging ni ca ta chn
ln trong ting nhc.

2.2 Hng dn ci t USB-Blaster Driver


Bo mch DE2 c ng gi bao gm tt c nhng phn cn thit cho hot
ng ca n ngoi mt b ngun adapter 9 volt v cp kt ni USB. Bo mch c
bo v bi m lp knh nhm hn ch s h hng khng mong mun trong qu
trnh s dng.
Cm ngun adapter 9 volt vo bo mch DE2. S dng cp USB kt ni
cng USB (cng nm lin k nt m ngun (power) trn bo mch DE2 vi cng
32

USB trn my tnh c th chy c nhng phn mm Quartus II. Sau m


ngun trn bo mch DE2.
My tnh s nhn ra mt thit b phn cng c kt ni n cng USB, tuy
nhin n s khng th thc thi vic truyn nhn d liu nu trnh iu khin cha
c ci t. Bo mch DE2 c lp trnh bng vic s dng cng USB-Blaster
vi c ch hot ng ca Altera. Nu trnh iu khin USB-Blaster cha c ci
t, mn hnh New Hardware Wizard nh Hnh 2.2 s xut hin.

Hnh 2.2 Ch v tr driver cho hardware


Bi v trnh iu khin cn thit khng c sn trn Window Update
Website, ta chn No, not this time tr li cho cu hi v nhn Next. Mt
mn hnh nh trong Hnh 2.3 s xut hin.

33

Hnh 2.3 Ch ng dn cho driver


Trnh iu khin USB-Blaster c sn bn trong phn mm ci t Quartus II,
do ta chn Install from a specific location v nhn Next ra mn hnh nh
trong Hnh 2.4.

Hnh 2.4 Ch ng dn cho driver


34

By gi, ta chn Search for the best driver in these locations v nhn
Browse xut hin hp thoi nh trong Hnh 2.5. Tm trnh iu khin mong
mun nm trong th mc C:\altera\90\quartus\drivers\usb-blaster\x32. Nhn OK,
sau mn hnh s chuyn v nh trong Hnh 2.4, nhn Next. Lc ny th vic ci
t c bt u, nhng s c mt hp thoi nh trong Hnh 2.6 s xut hin
thng bo rng trnh iu khin cha hon thnh kim tra Window Logo. Nhn
Continue Anyway.

Hnh 2.5 Ch ng dn cho driver

35

Hnh 2.6 Khng cn kim tra driver


By gi trnh iu khin s c ci t nh trong Hnh 2.7. Nhn Finish v
ta c th bt u s dng bo mch DE2.

Hnh 2.7 Driver c ci t thnh cng

2.3 Thit lp cu hnh ban u v thay i cu hnh mi cho Cyclon


II FPGA
Qui trnh ti mt mch thit k t my ch ln Kit DE2 c m t chi tit
trong cc phn hng dn thc hnh h thng s, verilog hoc kin trc my tnh
nng cao trong Chng 4. , Chng 5. hoc Chng 6. . Ta nn c phn hng
36

dn ny trc v tham kho nhanh nhng thng tin di y hiu r qui trnh s
dng Kit.
Trn kit DE2 c mt b nh EEPROM hot ng ni tip, b nh ny cha
d liu khi to cu hnh ban u cho Cyclon II FPGA. D liu ny s t ng
c ti ln FPGA t EEPROM mi khi ngun in ca Kit DE2 c cung cp.
Sau khi ngun in c cung cp, FPGA s iu khin cc thit b trn Kit DE2
(leds, switchs,) hot ng vi d liu khi to. Sau , ta hon ton c th thay
i cu hnh khi to trn bng vic ti trc tip ln FPGA mt d liu, mt
chng trnh do ta thit k bng phn mm Quartus II. Bn cnh ta cng c th
thay i cu hnh khi to bng vic thay i d liu trn b nh EEPROM. Hai
phng php trn s c lit k di y:
JTAG ( Joint Test Action Group) programming: Trong phng php
ti chng trnh ny, chui bit cu hnh d liu s c ti trc tip
ln Cyclone II FPGA. FPGA s gi cu hnh ny cho n khi ngun
in khng cn c cung cp ln Kit DE2 na.
AS ( Active Serial) Programming: Trong phng php ti chng
trnh ny, chui bit cu hnh s c ti ln b nh EEPROM
EPCS16 hot ng ni tip. D liu lu tr trn b nh ny c nh
khng b mt hoc xa khi khng cn ngun in cung cp. Mi khi
ngun in c cung cp ln Kit DE2, d liu t b nh EEPROM
ny s t ng c ti ln Cyclone II FPGA.
Tng bc ca qu trnh thc thi vic ti chng trnh bng JTAG v AS s
c m t di. c hai phng php trn, Kit DE2 c kt ni vi my tnh
ch thng qua cap USB. Vi kt ni ny, Kit DE2 s c nhn dng bi my tnh
ch nh l mt thit b USB Blaster. Trnh iu khin (driver) dng nhn dng
v giao tip gia my tnh ch vi thit b USB Blaster cn c ci t trn my
37

tnh ch ( trnh by trong phn 2.2). Thit lp cu hnh mi cho FPGA t phn
mm QuartusII trn my tnh thng qua JTAG mode:

Hnh 2.8 Thit lp cu hnh cho FPGA thng qua JTAG mode
ti mt chui bit d liu cu hnh ln FPGA, ta cn thc thi nhng bc
sau:
1- Cung cp ngun cho Kit DE2.
2- Kt ni cp USB n cng USB Blaster trn Kit DE2.
3- Bt switch RUN/PROG v v tr RUN (pha tri ca Kit).
4- S dng cng c Programmer trn phn mm Quartus II ti file
cha chui bit d liu cu hnh c nh dng .sof ln FPGA.

38

2.3.1

Thit lp cu hnh ban u cho FPGA thng qua vic np cu hnh cho b nh
EPPROM EPCS16 bng AS mode:

Hnh 2.9 Thit lp cu hnh cho FPGA thng qua AS mode


ti mt chui bit d liu cu hnh ln b nh EPPROM EPCS16, ta cn
thc thi nhng bc sau:
1- Cung cp ngun cho Kit DE2.
2- Kt ni cp USB n cng USB Blaster trn Kit DE2.
3- Bt switch RUN/PROG v v tr PROG (pha tri ca Kit).
4- S dng cng c Programmer trn phn mm Quartus II ti file
cha chui bit d liu cu hnh c nh dng .pof ln b nh
EPPROM EPCS16..
5- Khi qu trnh ti chng trnh hon thnh, bt li switch RUN/PROG
v v tr RUN v ngt ngun khi Kit, sau li cung cp ngun li.
Thao tc ny s lm cho d liu cu hnh mi t b nh EPPROM
EPCS16 c t ng np ln FPGA. V d liu cu hnh mi ny s
c xem nh d liu cu hnh khi to mi cho Kit DE2 mi ln ta
cung cp ngun cho n.

39

2.4 S mch v hot ng ca cc linh kin trn Kit DE2


2.4.1

Switches (cng tc) v Button (nt nhn)

Kit DE2 cung cp bn Switch nhn. Khi khng c nhn tn hiu ng ra


ca nhng Switch ny mc cao, khi Switch c nhn gi tr tn hiu ng ra ca
mi Switch s tch cc mc thp v s c phc hi tr li gi tr mc cao nh c
nh mch Schmitt Trigger ngay khi Switch c th ra. Bn tn hiu ng ra ca
mch Schmitt Trigger c gi l KEY0, , KEY3 c kt ni trc tip n pin
ca Cyclone II FPGA. Nhng tn hiu ny thch hp cho vic to tn hiu xung
clock hay tn hiu Reset cho mch.

Hnh 2.10 Chc nng chng ny cho Push button


Ngoi ra Kit DE2 cung cp thm 18 Switch bt tt hot ng nh nhng
cng tc in. Khi nhng Switch ny v tr DOWN (gn cnh ca Kit), tn hiu
ng ra ca n s in p mc thp (0Volt) v ngc li khi Switch v tr UP, tn
hiu ng ra s cung cp in p mc cao (3.3V). Mi tn hiu ng ra t Switch ny
c ni trc tip n pin ca FPGA. Thng thng ta nn s dng in p mc
thp iu khin hot ng ca mch thit k. Di y l s mch kt ni
ca Switch trn Kit DE2 v danh sch lit k nhng tn hiu ng ra t Switch c
kt ni n nhng Pin tng ng ca Cyclone II FPGA.
40

Hnh 2.11 Mch thit k ca switches v push button

41

Hnh 2.12 Mapped pins gia switches v FPGA

Hnh 2.13 Mapped pins gia Push button v FPGA

42

2.4.2

Leds

Kit DE2 cung cp 27 LEDs, trong c 18 LEDs ( c t ngay trn 18


Switch bt tt), 8 LEDs xanh ( c t ngay trn 4 Switch nhn) v LED xanh th
9 nm ngay gia LED 7 on. Mi LED c iu khin trc tip bi mt tn hiu
t pin ca Cyclone II FPGA; LED sng khi tn hiu ny c in p mc cao v
ngc li LED tt khi tn hiu c in p mc thp. Di y l s mch kt ni
LED v danh sch lit k nhng tn hiu ng vo ca LED c kt ni n nhng
Pin tng ng ca Cyclone II FPGA.

Hnh 2.14 Mch thit k ca Leds

43

Hnh 2.15 Mapped pins gia LEDs v FPGA


44

2.4.3

LED hin th by on

Kit DE2 cung cp 8 LED hin th by on. LED sng khi tn hiu vo mc
thp v LED tt khi tn hiu vo mc cao. By on hin th trn LED c nh
s t 0 n 6, vi v tr c th hin nh hnh di, ch l du chm (.) trn mi
LED khng c kt ni nn khng th s dng.

Hnh 2.16 Led 7 on


Di y l s mch kt ni LED by on v danh sch lit k nhng
tn hiu ng vo ca LED by on c kt ni n nhng Pin tng ng ca
Cyclone II FPGA.

45

Hnh 2.17 Mch thit k ca LEDs 7 on

46

47

Hnh 2.18 Mapped pins gia LEDs 7 on v FPGA


2.4.4

LED hin th LCD

Khi LED hin th LCD vi kiu ch mc nh c to sn dng hin


th nhng k t bng vic gi nhng cu lnh thch hp n khi iu khin hin
48

th LCD HD44780. Ta c th tm hiu chi tit hot ng v chc nng ca LCD


trn Datasheet ca n. S mch kt ni ca LED LCD v nhng tn hiu ng
vo ca LED LCD n nhng Pin tng ng ca FPGA v danh sch lit k nhng
nhng tn hiu ng vo ca LED LCD n nhng Pin tng ng ca Cyclone II
FPGA.

Hnh 2.19 Mch thit k ca LCD

49

Hnh 2.20 Cu to LCD

Hnh 2.21 Mapped pins gia LCD v FPGA

50

2.4.4.1 iu khin hot ng cho LCD:

Trong khi hin th LCD c mt khi iu khin LSI, khi iu khin ny c


hai thanh ghi 8 bit, gm mt thanh ghi m lnh (IR) v mt thanh ghi d liu (DR).
Thanh ghi m lnh IR lu gi nhng m lnh nh xa hin th, dch con tr
v nhng a ch ca d liu cn hin th nm trong b nh DDRAM v b to k
t CGRAM. Thanh ghi IR ch c th c ghi vo t mt vi iu khin (MPU).
Thanh ghi d liu DR lu gi tm thi nhng d liu s c ghi vo hoc
c ra t DDRAM hay CGRAM. Khi a ch c ghi vo IR, d liu ng vi a
ch t DDRAM hay CGRAM s c lu gi trong DR. chn thao tc vi
mt trong hai thanh ghi trn, ta dng tn hiu chn thanh ghi (RS).

Hnh 2.22 Thanh ghi iu khin hot ng ca LCD

Busy Flag (BF)


Khi RS = 0 v R/W = 1, gi tr ca c BF s c c ra. Nu BF = 1, bo
hiu khi iu khin LSI ang bn thc hin nhng thao tc bn trong nn n s
khng nhn thm bt k lnh no t bn ngoi. Ch khi no chc chn gi tr ca c
BF = 0 th ta mi ghi lnh k tip.
B m a ch (AC):
B m a ch dng gn a ch cho DDRAM hoc CGRAM.
51

Hnh 2.23 B m a ch

B nh lu gi d liu hin th (DDRAM):


DDRAM c dng lu gi k t (c m ha bi mt gi tr 8 bit) hin
th trn LCD. Hnh di y th hin s tng ng gia a ch ca DDRAM vi
v tr hin th ca n trn LCD(2x16)

Hnh 2.24 B nh lu gi d liu hin th


Gi s hin th k t no ln v tr hng th 2, ct th 15 th ta phi
ghi 8 bit m ha cho k t vo nh c a ch 4E (BCD) trong DDRAM,
nh vy a ch ca AC s l:

Mun ghi d liu vo DDRAM, trc ht ta phi nh a ch ca DDRAM


m ta mun d liu s c lu vo ( cng chnh l v tr m k t s c
hin th trn LCD). Vic nh a ch ca DDRAM thng qua b m a ch
52

AC[6:0], sau khi a ch ca DDRAM c xc nh, ta s ghi d liu ( y


chnh l 8 bits m ha ca mu k t m ta mun hin th) vo thng qua 8 bits
DB[7:0].
B nh ROM lu gi mu k t ( Character Generator ROM Pattern)
B nh ROM ny c dung lng 4096x8 bits nn c 12 ng a ch
A[11:0] gii m. to mt mu k t 5x8 th ta cn 8 nh 8 bits. Gi s nh
trong hnh di lu gi mt mu k t b trong ROM, nh sn xut phi dng
8 nh c a ch t [011000100000] n [011000100111]. Ni dung ca mi
nh gm 8 bits O[7:0] c gn gi tr nh hnh di ( Nhng bit O[7:5] c
gn bng 0 ). Khi mun hin th k t b ra mn hnh LCD, ta ghi 8 bits d liu
m ha ca k t b vo b nh DDRAM (ghi gi tr vo DDRAM trnh by
trong phn DDRAM), 8 bits d liu m ha chnh l 8 bits gi tr a ch
A[11:4] ca ROM, vy ta phi ghi d liu 8 bits [01100010] vo trong b nh
DDRAM k t b hin th ln LED. Ta t hi qu trnh c d liu t 8 nh
trong ROM xut ra LED nh th no. Ta c th hnh dung n gin nh sau,
sau khi nhn 8 bits d liu t DDRAM, khi iu khin s hiu 8 bits chnh l 8
bits A[11:4] ca ROM, n s t ng c lin tc (ni tip) d liu t 8 nh
trong ROM m bt u t a ch A[11:4][0000] v chuyn n thnh mt chui d
liu song song 8x8 bits bng b chuyn i ni tip sang song song v xut ra
LED.

53

Hnh 2.25 B nh lu gi mu k t
Di y l b mu k t c nh sn xut to sn trong ROM ca khi
iu khin v 8 bits d liu m ha ( ta dng ghi vo b nh DDRAM) tng
ng cho tng mu k t. ( 8 bits d liu ny cng chnh l A[11:4] ca a ch m
mu k t c lu trong ROM).

54

Hnh 2.26 B nh lu gi tt c cc mu k t

55

V d: by gi ta mun hin th s 9 ln LCD hng 2, ct 14 th trc


tin ta phi ghi gi tr a ch hexadecimal 4D [01001101] vo b m a ch AC
sau ghi 8 bits d liu m ha ca k t 9 l [00111001].
B to k t RAM (CGRAM)
RAM c dung lng 64x8 bits nn c 5 ng a ch gii m A[5:0].
CGRAM cho php ngi s dng t to mu k t cho ring mnh. V ch c dung
lng 64x8 bits nn ta ch c th to c ti a 8 k t 5x8 hoc 4 k t 5x10.
Di y l bng m t s tng quan gia a ch ca CGRAM vi DDRAM m
b iu khin s da vo kim sot hot ng.

Hnh 2.27 B to mu k t

56

hiu ngha ca bng trn, ta s dng mt th d minh ha. V y l


CGRAM cho php ngi s dng t to mu k t ring nn trc ht ta phi to
mu k t m mnh mun ( m khng c sn trong CGROM nh sn xut cung
cp). Gi s ta mun to mu k t R 5x8 nh trn hnh v. V y l mu k t
5x8 nn s cn 8 nh trong CGRAM lu gi, y lu mu k t R vo 8
nh m bt u bng nh c a ch A[000000] v kt thc l nh c a ch
A[000111] vi ni dung ca tng nh nh bng pha bn phi (CGRAM data)
tng trng cho gi tr 1 c lu trong CGRAM. Nh vy ta to xong mt
mu k t trong CGRAM.
Gi ta mun hin th k t ra LCD, vy lm sao ta bit c 8 bits d liu
c m ha cho mu k t trn ghi vo DDRAM cho vic xut ra. Vic m
ha ny khi iu khin s t ng ngm hiu nh sau: N ly 3 bits a ch ca
CGRAM A[5:3] lm 3 bits thp D[2:0] ca 8 bits m ha, 4 bits cao D[7:4] ca 8
bits m ha s gn bng 0 , cn bit th 4 D[3] n s khng quan tm. Nh vy 8
bits m ha cho mu k t R m ta va to trn l D[0000x000]. Vy hin
th k t R trn ta ch cn ghi 8 bits c gi tr [0000x000] ( trong x c th l
0 hay 1) vo b nh DDRAM. ( ghi gi tr vo DDRAM trnh by trong
phn DDRAM).
Tp lnh ca LCD:

57

58

59

60

Hnh 2.28 Tp lnh LCD

2.4.5

Ng vo xung Clock

Kit DE2 cung cp hai ngun tn hiu xung Clock 27 MHz v 50 MHz. Ngoi
ra ta cng c th cung cp ngun xung Clock t bn ngoi thng qua cng ng vo
SMA. S mch kt ni ngun xung Clock v danh sch lit k nhng tn hiu
ngun xung Clock kt ni n nhng Pin tng ng ca Cyclone II FPGA.

Hnh 2.29 Mch thit k ca ng vo xung Clock

61

Hnh 2.30 Mapped pins gia ng vo xung Clock v FPGA


2.4.6

Expansion Header (Jac cm m rng)

Kit DE2 cung cp thm hai expansion headers 40-pins. Mi header c kt


ni trc tip n 36 pins ca Cyclone II FPGA, 1 pin ngun DC +5V (VCC5), 1
pin ngun DC +3.3V (VCC33) v 2 pins GND. Hnh di m t mt phn ca
mch cho 4 pins ca mi expansion headers, mch y s gm 40 pins cho mi
expansion headers. Mi pin t expansion header c kt ni n hai diode v mt
in tr dng bo v khi hin tng qu p hay h p.

62

Hnh 2.31 Mch thit k giao tip gia PIO v FPGA


Di y l bng lit k 80 pins ca hai expansion header v 80 pins ca
FPGA c kt ni tng ng .

63

64

65

Hnh 2.32 Mapped pins gia pin PIO v FPGA

2.4.7

VGA

Bo mch DE2 c mt ng raVGA D-SUB 16 pin. Nhng tn hiu ng b


VGA c cung cp trc tip t FPGA Cyclone II, v mt con chip x l tn hiu
s sang tng t video DAC ADV7123 vi tc cao 10 bit c dng to ra
nhng tn hiu tng t (, xanh lam, xanh lc). S mch VGA c cho
66

Hnh 2.33 v c th h tr phn gii ln n 1600x1200 pixels tc


100MHz.

Hnh 2.33 S mch VGA

c t thi gian cho nhng d liu v ng b VGA cng nh d liu RGB


( , xanh luc, xanh lam) c th c tm thy trn nhiu trang web v o to (v
d, ch cn tm kim trn google vi t kha VGA signal timing). Hnh 2.34
minh ha nhng rng buc c bn v thi gian cho mi hng ( horizontal) hin
th trn mn hnh VGA. Mt tn hiu xung tch cc mc thp trong mt khong
thi gian nht nh ( khoang thi gian a nh trong hnh) c cp n tn hiu ng
vo ng b hng (hsync) ca mn hnh cho bit du hiu kt thc mt hng d
liu v bt u mt hng d liu k tip. Nhng ng vo RGB trn mn hnh phi
tt ( iu khin v 0V) trong mt khong thi gian gi l back porch (b) sau khi
xung tn hiu ng vo ng b hng (hsync) xut hin, v tip tc theo sau khong
67

thi gian (b) ny l khong thi gian hin th (c). Trong sut khong thi gian hin
th, tn hiu RGB iu khin mi pixel hin th dc theo hng. Cui cng, trong
mt khong thi gian gi l front porch (d) nhng tn hiu RGB phi tt i ln
na trc khi tn hiu xung ng vo ng b hng (hsync) k tip xut hin bt
u mt hng mi. c t v thi gian cho tn hiu ng b ct (vsync) c trnh
by tng t trong Hnh 2.34, n ch khc l xung tn hiu vsync cho bit du
hiu kt thc mt khung (frame) mn hnh v bt u mt khung mn hnh k tip.
Hnh 2.35 v Hnh 2.36 m t nhng khong thi gian ng b hng v ct a, b, c
v d ng vi nhng phn gii khc nhau.
Thng tin chi tit v vic s dng chip Video DAC ADV7123 c m t r
trong datasheet ca n m ta c th tm thy trn website ca nh sn xut. Vic
gn pin gia FPGA Cyclone II v chip ADV7123 c lit k trong Hnh 2.37.

Hnh 2.34 Gin nh thi ca tn hiu HSYNC

68

Hnh 2.35 M t nh thi cho vic ng b hng

Hnh 2.36 M t nh thi cho vic ng b ct

69

70

Hnh 2.37 Mapped pins gia ADV7123 v FPGA

2.4.8

Audio CODEC 24-bit

Bo mch DE2 cung cp vic x l m thanh cht lng cao 24 bit thng qua
mt chip Wolfson WM8731 audio CODEC (encoder/DECcoder). Con chip ny h
tr ng vo microphone, ng vo v ng ra c kh nng iu chnh tc ly mu
t 8 kHz n 96 kHz. Chip WM8731 c kt ni vi cc pin trn FPGA Cyclone
II thng qua giao thc giao tip bus ni tip I2C. S mch x l m thanh c
th hin trn Hnh 2.38, v vic gn pin trn FPGA c lit k trong bng Hnh
2.39. Thng tin chi tit v cch thc s dng chip WM8731 CODEC c trnh
by trn datasheet ca n v ta cng c th tm thy trn website ca nh sn xut.

71

Hnh 2.38 Mch thit k ca Audio Codec

Hnh 2.39 Mapped pins gia Audio Codec v FPGA


2.4.9

Cng ni tip RS-232

Bo mch DE2 s dng chip truyn nhn d liu MAX232 v cng giao tip
D-SUB 9 pin cho vic giao tip RS-232. Thng tin chi tit v cch thc s dng
72

chip MAX232 cng nh cng giao tip D-SUB c trnh by trn datasheet ca
n v ta cng c th tm thy trn website ca nh sn xut. Hnh 2.40 m t mch
kt ni cng ni tip RS-232, v vic gn pin cho FPGA Cyclone II c lit k
trong Hnh 2.41

Hnh 2.40 Mch thit k giao tip gia RS-232 v FPGA

Hnh 2.41 Mapped pins gia RS-232 v FPGA


2.4.10 Cng ni tip PS/2

Bo mch DE2 c mt giao tip chun PS/2 v mt cng kt ni PS/2 cho


bn phm hoc con chut my tnh. Hnh 2.42 m t mch kt ni ca PS/2. Hng
dn s dng chut PS/2 hay bn phm PS/2 c th c tm thy trn rt nhiu
website. Vic gn pin gia cng kt ni PS/2 c ch ra trn Hnh 2.43.

73

Hnh 2.42 Mch thit k giao tip gia cng PS/2 v FPGA

Hnh 2.43 Mapped pins gia cng PS/2 v FPGA


2.4.11 Mch iu khin mng Fast Ethernet

Bo mch DE2 cung cp vic h tr kt ni Ethernet thng qua chip iu


khin Davicom DM9000A Fast Ethernet. Chip DM9000A bao gm mt giao tip
vi mt vi x l thng thng, mt SRAM 16 Kbytes, mt khi iu khin truy
xut truyn thng (MAC), v mt b truyn nhn d liu 10/100M PHY. Hnh
2.44 m t mch thc hin vic giao tip Fast Ethernet. Hnh 2.45 lit k vic gn
pin gia chip DM9000A v FPGA Cyclone II. Thng tin chi tit v cch thc s
dng chip DM9000A c trnh by trn datasheet ca n v ta cng c th tm
thy trn website ca nh sn xut.

74

Hnh 2.44 Mch thit k giao tip gia DM9000A v FPGA

75

Hnh 2.45 Mapped pins gia DM9000A v FPGA


2.4.12 TV Decoder

Bo mch DE2 c trang b mt chip m ha thit b tng t TV


ADV7181. Chip ADV7181 l mt mch m ha video tch hp c chc nng d
tm v chuyn i mt tn hiu analog (tng t) truyn hnh c gii nn chun
(NTSC, PAL, SECAM) sang tn hiu d liu digital (s) 4:2:2 c kh nng tng
thch vi CCIR601/CCIR656 16bit/8bit. Chip ADV7181 tng thch c vi
nhiu thit b Video khc nhau bao gm u DVD, thit b truyn thng cng nh
camera theo di.
Nhng gi tr ca nhng thanh ghi trong chip m ha TV c th c lp
trnh thng qua giao tip bus ni tip I2C c kt ni vi FPGA Cyclone II nh
trong Hnh 2.46. Vic gn pin c lit k trong Hnh 2.47. Thng tin chi tit v
cch thc s dng chip ADV7181 c trnh by trn datasheet ca n v ta cng
c th tm thy trn website ca nh sn xut.

76

Hnh 2.46 Mch thit k giao tip gia ADV7181 v FPGA

77

Hnh 2.47 Mapped pins gia ADV7181 v FPGA

2.4.13 TV Encoder

Mc d bo mch DE2 khng c chip TV Encoder, nhng ta c th s dng


chip ADV7123 (chip ADC 10 bit tc cao) thc thi mt khi TV encoder vi
cht lng cao trong phn x l tn hiu s c thc hin trong FPGA Cyclone
II. Hnh 2.48 m t s khi thc thi mt TV encoder

78

Hnh 2.48 TV encoder ADV7123 v FPGA

2.4.14 USB Host and Device

Bo mch DE2 cung cp ng thi hai giao tip USB host v device bng
vic s dng mt chip iu khin USB ISP1362 ca Philips. B iu khin host v
device tng thch vi chun giao tip USB 2.0, h tr vic truyn d liu vi tc
cao (12 Mbit/s) v tc thp (1.5 Mbit/s). Hnh 2.49 m t s mch kt ni
USB. Hnh 2.50 lit k vic gn pin kt ni t chip ISP1362 n FPGA Cyclone II.
Thng tin chi tit v cch thc s dng chip ISP1362 c trnh by trn
datasheet ca n v ta cng c th tm thy trn website ca nh sn xut. Phn
thch thc nht ca mt ng dng USB l lun cn mt phn mm iu khin.

79

Hnh 2.49 Mch thit k giao tip USB gia chip ISP1362 v FPGA

80

Hnh 2.50 Mapped pins gia ISP1362 v FPGA

2.4.15 Cng hng ngoi

Bo mch DE2 cung cp mt giao tip truyn thng n gin khng dy s


dng b truyn pht hng ngoi cng sut thp Agilent HSDL-3201. Thng tin chi
tit v cch thc s dng chip Agilent HDSL-3201 c trnh by trn datasheet
ca n v ta cng c th tm thy trn website ca nh sn xut. Ch rng tc
truyn cao nht c h tr l 115.2 Kbit/s v c hai pha nhn v thu phi s dng
tc truyn nh nhau. Hnh 2.51 m t mch kt ni ca giao tip hng ngoi.
hiu r thm v cch thc truyn v nhn d liu dung cng hng ngoi, ta c th
vo website sau tham kho:
http://techtrain.microchip.com/webseminars/documents/IrDA_BW.pdf.

81

Vic kt ni pin gia cng hng ngoi v FPGA Cyclone II c lit k


trong Hnh 2.52

Hnh 2.51 Mch giao tip gia cng hng ngoi v FPGA

Hnh 2.52 Mapped pins gia cng hng ngoi v FPGA


2.4.16 B nh SDRAM/SRAM/Flash

Bo mch DE2 cung cp mt b nh SDRAM 8 Mbyte, mt b nh SRAM


512 Kbyte v mt b nh Flash 4 Mbyte (1 Mbyte trn mt s board mch). Hnh
2.53, Hnh 2.54 v Hnh 2.55 m t s mch kt ni ca mi loi b nh. Vic
gn pin kt ni gia FPGA Cyclone II vi mi loi b nh c lit k trong cc
Hnh 2.56, Hnh 2.57 v Hnh 2.58. Datasheet ca mi loi b nh c th tm thy
d dng trn cc website.

82

Hnh 2.53 Mch giao tip thit k gia DRAM v FPGA

Hnh 2.54 Mch giao tip thit k gia SRAM v FPGA

83

Hnh 2.55 Mch giao tip thit k gia FLASH v FPGA

84

Hnh 2.56 Mapped pins gia SDRAM v FPGA

85

86

Hnh 2.57 Mapped pins gia SRAM v FPGA

87

Hnh 2.58 Mapped pins gia FLASH v FPGA

88

Chng 3.

Hng dn ci t v s dng phn mm Control


Panel iu khin kit DE2

3.1 Hng dn ci t Control Panel iu khin Kit DE2


Trnh ng dng Control Panel i km vi Kit DE2 cho php ngi s dng
iu khin tt c nhng linh kin trn Kit DE2 thng qua cng USB t mt
computer cha trnh ng dng Control Panel trn. Trong phn ny, ta s m t mt
s chc nng c bn ca trnh ng dng Control Panel, sau ta s m t cu trc
ca n di dng s khi, v cui cng l m t nhng kh nng ca n.
ci t trnh iu khin Control Panel, Altera cung cp cho ngi s
dng 2 file sau y:
i.

DE2_USB_API.sof

ii.

DE2_control_panel.exe

kch hot trnh ng dng Control Panel, ta cn thc hin nhng bc sau:
1- Kt ni cp USB n cng USB Blaster. Cung cp ngun 9V. Bt
ngun ln v tr ON.
2- Chuyn switch RUN/PROG v tr RUN.
3- M phn mm Quartus II .
4- Chn Tools  Programmer, ta s c hnh sau:

89

Hnh 3.1 Giao din cho vic cu hnh thit k ln FPGA


5- Nhn chn Add File, ch ng dn n file cu hnh
DE2_USB_API.sof
6- Nhn chn  ct Program/Configure.
7- Nhn Start np file cu hnh DE2_USB_API.sof xung FPGA.
thc thi file DE2_control_panel.exe trn computer bng cch nhp p
ln biu tng ca file. Sau khi chy xong, ta s thy mt giao din nh sau:

90

Hnh 3.2 Giao din Control Panel


Trn Control Panel, ta m cng USB bng cch nhn : Open  Open USB
Port 0. Trnh ng dng DE2 Control Panel s lit k tt c nhng cng USB kt
ni vi Kit DE2. Trnh ng dng ny c th iu khin 4 Kit DE2 cng mt lc
thng qua USB links. Ch , trn trnh ng dng DE2 Control Panel s xut hin
cng USB cho n khi ta ng cng ny li; khi cng USB cha c ng li th
ta khng th dng Quartus II np file cu hnh DE2_USB_API.sof xung
FPGA.
Trnh ng dng DE2 Control Panel by gi sn sng cho vic iu khin;
tin hnh th nghim bng cch thit lp gi tr cho mt vi LEDs by on v
quan st kt qu trn Kit DE2.
Hot ng ca trnh ng dng DE2 Control Panel c minh ha nh hnh
di y:

91

Hnh 3.3 Giao tip gia Control Panel v cc thit b ngoi vi trn FPGA
Trong IP thc thi chc nng iu khin. IP ny c thit k trn FPGA.
N lin lc vi trnh ng dng DE2 Control Panel trn computer thng qua cng
USB Blaster. Giao din ha c s dng truyn lnh xung mch iu
khin. Cng vic ca IP l qun l tt c nhng yu cu v thc thi vic truyn d
liu gia my tnh v Kit DE2.
Trnh ng dng DE2 Control Panel c th c dng thay i gi tr hin
th trn LEDs by on, bt LEDs, giao tip vi bn phm PS/2, c v ghi SRAM,
Flash Memory v SDRAM, ti hnh nh ln mn hnh VGA, ti nhc vo b nh
v nghe nhc qua audio DAC. c tnh c v ghi mt byte hay ton b file t hay
n Flash Memory cho php ngi s dng pht trin nhiu ng dng multimedia (
Flash Audio Player, Flash Picture Viewer) m khng cn quan tm n cch to ra
mt Flash Memory Programmer.

3.2 Tng quan v cu trc v hot ng ca Control Panel


DE2 Control Panel giao tip vi mt module in t (thit k bng ngn ng
phn cng nh Verilog hay VHDL) c bin dch v np vo Chip Cyclone II
FPGA. V Altera cung cp cho chng ta nhng module trn di dng ngn ng

92

Verilog, do ta hon ton c th da vo chnh sa v thay i chc nng


hot ng ca Control Panel, tt nhin ta phi nm vng ngn ng Verilog.
Hnh di m t cu trc ca Control Panel. Mi thit b ng vo hoc ng
ra u c iu khin bi mt trnh iu khin c thit k bng ngn ng
Verilog v c np ln FPGA (DE2_USB_API.sof). Vic giao tip gia nhng
trnh iu khin ny vi PC c thc hin thng qua USB Blaster. Nhn trn hnh
ta thy khi Command Controller, chc nng ca khi ny l bin dch nhng lnh
nhn t PC v thc thi nhng tc v thch hp. Nhng khi trnh iu khin cho
SDRAM, SRAM v Flash Memory c ba chn user-selectable bt ng b cng
vi mt chn Host kt ni n khi Command Controller. Kt ni gia trnh
iu khin VGA DAC n b nh ca FPGA cho php hin th mt hnh nh mc
nh (Tiger) lu sn trong b nh ca FPGA. Kt ni gia trnh iu khin
Audio DAC ti mt lookup table trn FPGA to ra mt tn hiu m thanh
test c tn s 1KHz.

93

Hnh 3.4 S khi giao tip gia Control Panel v cc thit b ngoi vi
Ta c th kt ni nhng module ca mnh n mt trong nhng User
Ports ca trnh iu khin SRAM/SDRAM/Flash memory, sau ta c th ti d
liu nh phn vo trong SRAM/SDRAM/Flash memory. Khi d liu c ti
vo trong SRAM/SDRAM/Flash memory, ta c th thit lp li cu hnh cho cc
khi trnh iu khin SRAM/SDRAM/Flash memory nhng khi ny c th
c/ghi d liu ca SRAM/SDRAM/Flash memory thng qua User Ports (
thit lp li cu hnh cho nhng khi ny i hi ta phi c kin thc v Verilog).

94

3.3 Hng dn s dng Control Panel


3.3.1

iu khin LEDs, LEDs by on, LCD

Chc nng c bn ca Control Panel l cho php thit lp nhng gi tr hin


th trn LEDs, LEDs by on v LCD.
Trn ca s Control Panel hnh di y, chn tab PS2 & 7-SEG nhng
gi tr c th hin trn LEDs by on (HEX7-HEX0) c th c nhp vo t
nhng tng ng. nhng gi tr va nhp trn hin th trn LED by on
bng cch nhn vo nt Set. hin th cc k t trn LCD, ta c th s dng bn
phm c kt ni vi Kit DE2 thng qua cng PS/2, sau ta c th nhp k t t
bn phm ny hin th ln LCD.

Hnh 3.5 Giao din Control Panel iu khin LEDs 7 on

1- Chn tab LED & LCD ta s c ca s nh hnh di

95

Hnh 3.6 Giao din Control Panel iu khin LEDs n


2- Ta c th bt sng mt LED bt k bng cch chn  vo LED sau
nhn nt Set. Ta cng c th hin th nhng k t ln LCD bng
cch nhp nhng k t ln hp LCD trn ca s Control Panel, sau
nhn nt Set.
Vic thit lp gi tr hin th ln nhng thit b hin th n gin trn th
cng khng cn n mt trnh ng dng nh Control Panel, tuy nhin vi trnh ng
dng Control Panel, ta s c mt cng c n gin kim tra hot ng ca tng
linh kin trn Kit DE2, ng thi n cng c dng debug trong qu trnh thit
k.
3.3.2

Truy xut b nh SDRAM/SRAM

Ta c th truy xut d liu nh c d liu t b nh hay ghi d liu vo b


nh (SDRAM/SRAM) trn Kit DE2. Di y ta s m t cch thc truy xut
SDRAM thng qua Control Panel (cch thc ny cng tng t i vi SRAM).
Chn tab SDRAM, ta s nhn thy mt ca s nh hnh di
96

Hnh 3.7 Giao din Control Panel iu khin SDRAM

Vi Control Panel, ta c th truy xut mt t 16 bits hoc truy xut


mt dy nhng t nhng nh lin tip.
ghi mt t 16 bits (Random access), ta nhp a ch nh cn ghi
vo Address, tip n nhp data cn ghi vo wDATA, sau
nhn nt Write. Trong hnh trn, ta mun ghi gi tr di dng
hexadecimal 6CA vo b nh a ch 200. Sau khi ta nhn nt
Write th gi tr 6CA c ghi vo nh c a ch 200 ca b
nh.
c mt t 16 bits (Random access), ta nhp a ch nh cn c
ra, sau nhn nt Read. Trong hnh trn, ta mun c gi tr t
nh c a ch 200. Sau khi ta nhn nt Read th gi tr 6CA ( gi s
gi tr ny c ghi vo t thao tc ghi) s hin th trn rDATA

97

ghi mt chui nhng k t lin tip hay ni dung ca mt file vo


SDRAM (Sequential Write), ta thc hin nhng thao tc sau:
1. Nhp a ch ca nh bt u lu tr ni dung ca mt file
vo Address.
2. Nhp chiu di ca ni dung file cn ghi vo hp Length. Nu ta
mun ghi ton b file vo trong SDRAM ta chi vic chn  cho
File Length m khng cn Nhp chiu di ca ni dung file cn
ghi vo Length.
3. Ch ng dn ca file data cn ghi bng cch nhn Write a File
to SDRAM v xc nh ng dn cho file .
Control Panel cng h tr ghi file c ni dung c nh dng Hexa.
File nh dng Hexa l file cha nhng k t ASCII biu din
nhng gi tr Hexadecimal. Gi s, ta c mt file cha dng nhng k
t ASCII sau :
0123456789ABCDEF
Dng k t trn xc nh bn gi tr 16-bit : 0123, 4567, 89AB, CDEF.
Nhng gi tr ny s c ghi theo tun t vo SDRAM.
c mt chui nhng k t lin tip hay ni dung ca mt file t
SDRAM (Sequential Read), ta thc hin nhng thao tc sau:
1. Nhp a ch ca nh bt u ca chui nh m ta mun c ra
vo Address.
2. Nhp chiu di ca ni dung file cn c (s byte) vo hp
Length. Nu ta mun c ton b ni dung trong SDRAM ( tt c

98

8 Mbytes) ta chi vic chn  cho Entire SDRAM m khng cn


nhp chiu di ca ni dung file cn c vo Length.
3. Ch ng dn ca file th hin nhng gi tr mun c t
SDRAM ra bng cch nhn Load SDRAM Content to a File v
xc nh ng dn cho file . Sau ta c th xem ni dung va
c ra t SDRAM trn file ny.

3.3.3

Truy xut b nh Flash (Flash memory)

Control Panel cho php ta truy xut (ghi/c) d liu ca Flash


memory trn Kit DE2. Ta c th s dng Control Panel thc hin cc thao tc
sau:
Xa ton b b nh Flash
Ghi mt byte ln b nh Flash
c mt byte t b nh Flash
Ghi mt file binary ln b nh Flash
c ni dung ca b nh Flash ra mt file.
Ch : Di y l nhng c tnh ca b nh Flash
Dung lng b nh Flash l 4Mx8bits
Ta phi xa ton b b nh Flash trc khi ghi d liu ln n. (S ln
xa b gii hn bi nh sn xut, do ngi s dng phi nhn thc
c s ln c th xa b nh Flash m khng khin n b hng).
Thi gian xa ton b b nh Flash l khong 20s. Do khng
c ng (ngt ngun) Kit DE2 trong sut qu trnh xa b nh
Flash.
truy xut b nh Flash thng qua Control Panel, ta chn tab FLASH trn
ca s Control Panel, mt ca s nh hnh di s xut hin
99

Hnh 3.8 Giao din Control Panel iu khin FLASH


ghi mt byte d liu vo mt v tr ngu nhin trn b nh Flash, ta cn
thc hin nhng bc sau:
1. Nhn nt Chip Erase. Qu trnh xa c thc hin trong khong
20s.
2. Nhp a ch ca nh m ta mun ghi mt byte d liu vo trn
Address.
3. Nhp byte d liu cn ghi vo wDATA. Sau nhn nt Write
c mt byte d liu vo mt v tr ngu nhin trn b nh Flash, ta cn
thc hin nhng bc sau:
1. Nhp a ch ca nh m ta mun c mt byte d liu ra trn
Address.
2. Sau nhn nt Read. Byte d liu c ra s c hin th trn
rDATA.
100

ghi mt file d liu (Sequential Write) vo trong b nh Flash, ta cn


thc hin nhng bc sau:
1. Nhp a ch ca nh bt u lu tr ni dung ca mt file
vo Address.
2. Nhp chiu di ca ni dung file cn ghi vo hp Length. Nu ta
mun ghi ton b file vo trong b nh Flash ta ch vic chn 
cho File Length m khng cn nhp chiu di ca ni dung file
cn ghi vo Length.
3. Ch ng dn ca file data cn ghi bng cch nhn Write a File
to Flash v xc nh ng dn cho file .
c mt chui nhng k t lin tip hay ni dung ca mt file t b nh
Flash (Sequential Read), ta thc hin nhng thao tc sau:
1. Nhp a ch ca nh bt u ca chui nh m ta mun c ra
vo Address.
2. Nhp chiu di ca ni dung file cn c (s byte) vo hp
Length. Nu ta mun c ton b ni dung trong b nh Flash ta
chi vic chn  cho Entire Flash m khng cn nhp chiu di
ca ni dung file cn c vo Length.
3. Ch ng dn ca file th hin nhng gi tr mun c t b
nh Flash ra bng cch nhn Load Flash Content to a File v xc
nh ng dn cho file . Sau ta c th xem ni dung va c
ra t b nh Flash trn file ny.

101

3.3.4

TOOLS Multi-Port SRAM/SDRAM/Flash Controller

Chn Tab TOOLS trn ca s Control Panel s cho php ta chn User
Ports. Chng ta s mt v d c th bng vic thc thi mt Flash Music Player. Ta
ti mt file nhc vo trong Flash memory. User Port 1 ca trnh iu khin Flash
memory c dng truyn file nhc n trnh iu khin Audio DAC v xut ra
output.
thc hin v d trn ta thc thi theo cc bc sau:
1. Xa b nh Flash . Sau ghi file nhc (music.wav) ln b nh
Flash (Trnh by trong phn 3.3.3 )
2. Trn Control Panel, chn Tab TOOLS, mt ca s nh hnh di
s xut hin.

Hnh 3.9 Giao din Control Panel iu khin Multi-Ports

3. Chn cng Asynchronous 1 cho Flash Multiplexer v nhn nt


Configure kch hot cng trn. Ta cn nhn nt Configure
cho php kt ni t Flash Memory n Asynchronous Port 1 ca
trnh iu khin Flash.
102

4. Tt SW1 ( v tr DOWN) v bt SW0 ( v tr UP).


5. Cm headphone vo audio output, ta c th nghe nhc c pht ra
t khi mch Audio DAC.
Ch rng, Asynchronous Port 1 c kt ni n Audio DAC nh hnh
trn. Khi ta chn Asynchronous Port 1 v nhn nt Configure, trnh iu khin
Audio DAC s giao tip trc tip vi b nh Flash. Trong v d trn, khi module
Verilog AUDIO_DAC c nhim v c ni dung ca b nh Flash v truyn n
n Chip Audio bn ngoi FPGA.

3.3.5

VGA Display Control

Control Panel cung cp mt cng c kt hp vi IP cho php ta hin th hnh


nh thng qua cng ng ra VGA. Di y l nhng bc dng minh ha cch
thc hin th mt bc nh ln mn hnh VGA.
Chn tab VGA trn ca s Control Panel, mt ca s nh hnh di s xut
hin.

Hnh 3.10 Giao din Control Panel iu khin VGA


1. nh du  vo hai Default Image v Cursor Enable

103

2. Kt ni mn hnh VGA n kit DE2. Ta s nhn thy mt mn hnh


mc nh (do ta chn  Default Image) nh hnh mc nh
nh hnh trn. Trn mn hnh bao gm mt con tr (do ta chn
 Cursor Enable) m v tr ca n c iu khin bi thanh
cun X/Y trn Control Panel.
Hnh nh xut hin mn hnh trn c lu tr trong mt vng nh M4K
trn Cyclon II FPGA. N s c ti n vng nh M4K di nh dng MIF/Hex
(Intel) trong sut qu trnh ta thit lp cu hnh mc nh cho n.
Tip theo ta s trnh by cch hin th mt hnh nh bt k ta mong mun ln
mn hnh VGA.
1. Ta c th ly mt hnh nh c nh dng pitutre.dat ( minh ha
cho phn trnh by ny ta s ly hnh nh c sn trong th mc
DE2_demonstrations/picture/picture.dat trn a CD DE2 System.
2. Ti file picture.dat vo trong SRAM ( trnh by phn c/Ghi
SRAM)
3. Chn tab TOOLS trn Control Panel, trn tab TOOLS ta chn
Asynchronous 1 cho mc SRAM multiplexer nh hnh di.

104

Hnh 3.11 Giao din Control Panel iu khin Multi-ports


4. Nhn nt Configure kch hot hot ng ca multi-port. Sau
khi kch hot, FPGA s c cu hnh li nh hnh di y

Hnh 3.12 Cu hnh trn FPGA ca Multi-ports

105

5. Chn tab VGA trn Control Panel v khng chn hp Default


Image na. Trn mn hnh VGA (nh hnh di) s xut hin hnh
nh ca file picture.dat m c lu tr trong SRAM.

Hnh 3.13 Mn hnh VGA


Ta c th hin th bt k hnh nh no bng vic ti file hnh nh vo
trong SRAM hoc vng nh M4K trong Cyclone II FPGA. Tuy nhin nh dng
ca file hnh nh ny phi c chuyn sang nh dng bitmap (file.dat ),
chuyn sang nh dng bitmap ta thc hin nhng bc sau:
1. M mt hnh nh ln mt phn mm hay cng c x l nh no
chng hn nh Paint trn Window.
2. iu chnh phn gii ca nh gc t c phn gii
640x480. Sau lu li di nh dng Windows Bitmap format
(.BMP)

106

3. Thc thi chng trnh thc thi ImgConv.exe (c sn trong th mc


DE2_control_panel/ImgConv.exe), mt cng c bin i nh cho
Kit DE2 s xut hin nh hnh di:

Hnh 3.14 Trnh bin i nh


4. Nhn chn Open Bitmap v chn file hnh nh c phn gii
640x480 trn.
5. Khi vic x l file hon thnh, nhn chn nt Save Raw Data, mt
file c nh dng Raw_Data_Gray.dat s c to ra v lu tr
trong cng th mc vi th mc cha nh gc. Tt nhin ta c th
t tn khc cho file hnh nh mi bng cch thay i n trong
trng File Name trn ca s hnh trn.
Sau khi c file Raw_Data_Gray.dat, ta c th ti trc tip n ln SRAM
trn Kit DE2 v hin th ln mn hnh VGA nh trnh by phn trn.
Cng c ImgConv trn cng cho php ta to ra Raw_Data_BW.data (v nh
dng .TXT ca n) vi hnh nh en trng. Vic iu chnh mc mu sc c
nh ngha trong BW Threshold di y:
107

Hnh 3.15 Gi tr ngng ca nh


Ta c th iu chnh mu sc cho hnh nh bng cch thay i nhng thng
s trong nhng trng BW Threshold v Band of RGB trn ca s ImvConv.

108

Chng 4.

Hng dn thit k v thc hnh mn hc H thng


s trn Kit DE2

4.1 Hng dn thc hnh


4.1.1

To mt project trn Quartus II

Bc 1.

Start  Programs  Altera  Quartus II 7.2  Quartus

II 7.2 (32 -Bit)

Hnh 4.1 Mn hnh chnh ca Quartus

Bc 2.

Nhn tab File trn mn hnh chnh

109

Hnh 4.2 Tab File

Bc 3.

M mt project mi : File  New Project Wizard

Hnh 4.3 To project


Bc 4.

Nhn Next

110

Hnh 4.4 Ch ng dn v tn project

Bc 5.

Nhp ng dn th mc ca project (c th to trc hoc nu

cha to s c t ng to).
Bc 6.

Nhp tn ca project.

Bc 7.

Nhp top-level ca thit k cho project (nn cho ging tn ca

project).
Bc 8.

Nhn Next

Bc 9.

Nu ng dn th mc ca project cha c to trc :

Hnh 4.5 ng dn cha tn ti

Bc 10.

Nhn Yes
111

Hnh 4.6 Add cc file s dng trong project

Bc 11.

Nhn Next

Hnh 4.7 Chn thit b FPGA

Bc 12.

Chn Family : Cyclone II

112

Bc 13.

Chn Available devices : EP2C35F672C6

FPGA Cyclone II trn Kit DE2).


Bc 14.

Nhn Next

Hnh 4.8 Thit lp EDA tool

Bc 15.

Nhn Next

113

(H ca Chip

Hnh 4.9 Hon thnh vic to project

Bc 16.

Nhn Finish ch v mn hnh chnh.

Hnh 4.10 Mn hnh chnh sau khi to project hon thnh


114

4.1.2

Thit k mt mch in n gin ( cng XOR ) dng Schematic trn Quartus II:

Hnh 4.11 Thit k mt mch s n gin


4.1.2.1 M trnh thit k s dng schematic

Bc 1.

M File  New

Hnh 4.12 Chn cng c thit k

Bc 2.

Chn Block Diagram/Schematic File

115

Hnh 4.13 Ca s thit k mch s

Bc 3.

Save as file : File  Save as

Hnh 4.14 Lu thit k

4.1.2.2 Thit k mch h thng s

Bc 1.

Chn v nhp cng Logic

Graphic Editor cung cp mt s th vin cha nhng linh kin in t, cho


php ngi s dng chn v nhp vo schemtic. Nhp p ln khong trng bn

116

trong ca s Graphic Editor hoc nhp ln biu tng

trong thanh cng c.

Mt ca s nh hnh di xut hin

Hnh 4.15 Chn linh kin

T ca s ny, ta c th tm v chn nhng linh kin hay cng logic m ta


mun nhp vo ca s Graphic Editor bng cch sau khi chn linh kin th ta
nhp nt OK. Th d ta mun nhp mt cng AND 2 ng vo, ta s tm v chn
and2 t Library, sau nhn OK, ta s c mt biu tng cng AND2 xut hin
trn ca s Graphic Editor. S dng chut di chuyn linh kin n v tr mong
mun bng cch nhn chut ln linh kin v ko ri nhp chut t n xung v
tr mi. Nu mun nhp mt cng AND2 ln th hai, ta c th lm nh cch trn
hoc c th copy t biu tng c sn trn ca s bng cch nhp phi chut,
ko r chut to ra mt biu tng th hai. Ta cng c th xoay biu tng ca
linh kin bng vic s dng biu tng
Bc 2.

trn thanh cng c.

Gn ng vo v ng ra cho linh kin:

Sau khi nhp linh kin vo trong ca s Graphic Editor, ta phi gn ng


vo v ng ra cho linh kin trong mch in. Qui trnh cng tng t nh tm v
nhp linh kin, nhng biu tng ng vo hay ng ra s c tm thy trong th
117

vin primitives/pin. Trong hnh di, ta s nhn thy biu tng ca ng vo v


ng ra c gn vo chn ca linh kin.

Hnh 4.16 Cc linh kin c chn


Sau khi gn ng vo v ng ra cho linh kin, ta phi t tn cho chng.
t tn, ta nhp p vo t pin_name ca ng vo hay ng ra. Mt hp thoi nh
hnh sau s xut hin

Hnh 4.17 t tn pin cho thit k

Nhp tn cho chn linh kin vo Pin name(s), ri nhn OK.


118

Bc 3.

Kt ni linh kin

Nhng linh kin trong mch phi c kt ni bng dy in. Nhn chn
biu tng

trn thanh cng c kch hot Orthogonal Node Tool. Di

chuyn con tr n u ca chn linh kin, nhn v gi chut tri v ko cho n


khi ng dy chm vo chn ca linh kin no m mnh mun kt ni ti. Ch ,
du chm en nh th hin cho s kt ni gia hai ng dy dn.
Vi qui trnh tng t, ta s kt ni cho ton b mch in sao cho ng vi
chc nng hot ng m ta mong mun. Nu trong qu trnh kt ni dy, ta kt ni
sai dy dn no , ta c th xa dy dn i bng cch nhn chn dy dn ri
nhn phm Delete (Del) trn bn phm. Sau khi hon thnh kt ni dy, ta nhn
biu tng

kch hot chc nng Select and Smart Drawing Tool. By gi ta

c th sp t li v tr ca mch in sao cho d nhn bng cch chn linh kin


hoc dy dn v di chuyn chng n mt vi tr thch hp hn. Th d, hnh di
y l mt mch in hon chnh:

Hnh 4.18 Thit k hon chnh


Sau khi mch in c hon chnh, ta nh lu li. Mt file thit k s
c lu di nh dng .bdf. Thi d light.bdf
.
119

4.1.2.3 Trnh bin dch

Vi d liu vo l file nh dng .bdf (light.bdf), nhiu cng c trong


phn mm Quartus II c dng phn tch, tng hp mch c thit k
phn trn, ri sau s to ra mt file thc thi dng np ln FPGA. Nhng cng
c c s dng trong qu trnh ny c gi l trnh bin dch. thc thi qu
trnh bin dch, ta thc hin cc bc sau:
Bc 1.
tng

Chn: Processing  Start Compilation hoc nhn chn biu


trn thanh cng c. Sau khi qu trnh bin dch c hon tt,

mt bng bo co c to ra nh hnh di

Hnh 4.19 Ca s trnh bin dch report

Bc 2.

xem li qu trnh bin dch, ta chn : Processing 

Compilation Report hoc nhn chn biu tng


c.
120

trn thanh cng

4.1.2.4 Message window

Phn mm Quartus II s hin th thng tin trong sut qu trnh bin


dch trn ca s Message widow. Nu s mch in c thit k trong phn
Graphic Editor hon ton ng, th mt thng bo The compilation was
successful c hin th. Trong trng hp qu trnh bin dch xut hin li th c
ngha c li xy ra trong qu trnh thit k trn Graphic Editor. Mi thng bo
tng ng vi mt li c tm thy s xut hin trn ca s Message. Nhp p
vo thng bo li ta s bit r hn v li xy ra trn mch in. Tng t,
trnh bin dch cng thng bo mt s cnh bo Warning. Ngoi ra ta cng c
th tm hiu thm thng tin v li cng nh cnh bo bng cch nhn chn vo
thng bo ri nhn phm F1 trn bn phm.
4.1.3

Gn pin

V ta cha thc hin gn pin trn FPGA cho linh kin trong mch in
thit k trn nn khi thc hin bin dch th trnh bin dch Quartus II gn
chn ca linh kin vi pin ca FPGA mt cch ngu nhin. Tuy nhin, gi s trong
thit k cng XOR n gin trn, sau khi thit k c bin dch v np ln
FPGA, ta mun hai ng vo x1, x2 c iu khin bi hai switch SW0 v SW1
cn kt qu ng ra f s c th hin trn led LEDG0 (SW0, SW1, LEDG0 c
ghi trn Kit). Mt khc ta bit switch SW0 c kt ni c nh vi pin N25 ca
FPGA, tng t vy switch SW1 c kt ni c nh vi pin N25 ca FPGA v
led LEDG0 c kt ni c nh vi pin AE22 ca FPGA. thc hin c iu
ta phi gn chn linh kin trn mch (x1, x2, f) vi pin tng ng trn FPGA
(N25, N26, AE22). gn pin ta thc hin cc bc sau
Bc 1.

Chn Assignments > Pins, mt ca s nh hnh di s xut

hin
121

Hnh 4.20 Ca s mapped pin gia thit k v FPGA

Bc 2.

Trong mc Category chn Pin. Nhp p ln mc <<new>>

trong ct To. Mt ca s nh hnh di xut hin

Hnh 4.21 Ca s gn pin


Bc 3.

Nhn chn x1 gn pin trc, tip n nhp p ln mc ngay

bn phi ca x1 trong ct Location, mt ca s nh hnh di s xut


hin

122

Hnh 4.22 Ca s lit k danh sch pin ca FPGA

Bc 4.

Ta nhp chn PIN_N25.

Bc 5.

Tng t, ta gn pin cho chn ng vo x2 ti pin PIN_N26, v

chn ng ra f ti pin PIN_AE22. Sau khi gn pin hon tt, ta s c nh


hnh di

Hnh 4.23 Ca s sau gn pin

Bc 6.

Lu li kt qu gn pin: File  Save

Bc 7.

Ta phi bin dch li thit k trn vi kt qu gn pin ny v

nh ta ni trn, v qu trnh bin dch trn, trnh bin dch Quartus


123

II ch gn pin mt cch ngu nhin nn s khng ng vi yu cu thit


k ca ta, do ta phi gn li pin cho ng vi yu cu ri phi chy li
qu trnh bin dch. Lc ny trnh bin dch Quartus II s s dng nhng
pin m ta gn cho chn ca mch in trong thit k phn tch, tng
hp v to ra mt file thc thi vic np xung cho FPGA.
Ngoi ra ta cng c mt cch khc gn pins cho design, c bit l rt
hu ch trong thit k m c nhiu chn, ta khng th ngi gn pin cho tng chn
c v s tn nhiu thi gian, Quartus II cung cp mt phng php gip ta gn
nhiu pin vo hoc g nhiu pin ra cng mt lc bng mt file c nh dng c
bit dng cho mc ch ny l nh dng .CSV. Format ca file ny nh sau
Nu ta dng file text to file ny, th n gin ta ch cn nhp theo
mu sau

To, Location
x1, PIN_N25
x2, PIN_N26
f, PIN_AE22
Nu ta dng Microsoft Excel, th ta s c format nh sau:

Hnh 4.24 Dng Microsoft Excel to file gn pin


124

Sau khi to file c format nh trn, ta s thc hin vic gn pin nh

sau
Bc 1.

Chn Assignments -> Import Assignments, mt hp thoi

nh hnh di xut hin

Hnh 4.25 Import file gn pin

Bc 2.

Click button , ch ng dn ca file ta va to trn. Ri

nhn OK.
thun tin cho ngi s dng Altera cung cp mt file CSV c tn
DE2_pin_assignments, file ny lit k tt c cc pin ca FPGA, c format nh sau:

125

Hnh 4.26 File gn pin to sn bi Altera

Nu ta mun s dng file c sn ny vo vic gn pin cho thit k ca ta th


mt yu cu bt buc khi ta t tn cho chn linh kin phi trng vi tn trong ct
To ca file ny. Th d, nu ta mun hai chn ng vo ca cng XOR c iu
khin bi hai Switch 0 v Switch 1 trn Kit DE2 th ta phi t tn cho hai chn
ny ln lt l SW[0], SW[1] nh trong ct To ca file ny. Do ta phi tham
kho file ny trc khi t tn cho chn linh kin khi gn pin ta s rt thun tin
l khng phi to file.csv na m ch cn Import file c sn ny vo thi.
Sau khi gn pin xong, ta bin dch li.
Re- compiling design : Processing  Start Compilation
Review Compilation report : Processing  Compilation Report
4.1.4

M phng mch thit k :

Bc 1.

To input waveform : File  New  Other Files  Vector

Waveform File
126

Hnh 4.27 To waveform

Bc 2.

Nhn OK

Hnh 4.28 Ca s to waveform

Bc 3.

Chn thi gian thc hin m phng : Edit  End Time

Bc 4.

Nhp thi gian thc hin m phng.

Bc 5.

Fit windown : View  Fit in Windown

Bc 6.

To waveform cho inputs : Edit  Insert Node or Bus

127

Hnh 4.29 Nhp tn signal ca thit k


Bc 7.

Chn Node Finder

Hnh 4.30 Dng chc nng Node Finder

Bc 8.

Chn Filter : Pins : all

Bc 9.

Nhn button List

Bc 10.

Chn signal bn Nodes found ; nhn >> chuyn sang bn

Selected Nodes
Bc 11.

Nhn OK

128

Hnh 4.31 To input waveform

Bc 12.

Chn mt input signal bng cch nhp chut vo signal .

Bc 13.

Chn biu tng mi tn con tr

Bc 14.

Di chuyn con tr sang mn hnh waveform .

Bc 15.

Nhn v gi chut v ko r (left) trong mt khong thi gian

(gi s ta mun trong khong thi gian t 40ns -> 60 ns , SW0 signal c
gi tr 1, th ta nhn , gi v r chut trong khong thi gian t 40ns ->
60ns.

Hnh 4.32 To mc logic "1"

Bc 16.

Nhn button 1 pha bn tri mn hnh

129

Hnh 4.33 Mc logic "1" c to


Bc 17.

Tng t cho nhng tn hiu inputs khc, khng to waveform

cho outputs ( XXX).


Bc 18.

Save File Waveform : File  Save As

Bc 19.

Thit lp thc hin m phng : Assignments  Setting

Hnh 4.34 Thit lp ch ch simulation

Bc 20.

Chn Simulator Settings

Bc 21.

Chn Simulation mode : Functional / Timing

Bc 22.

Ch ng dn ca input waveform va to.

Bc 23.

Nhn OK
130

Bc 24.

To simulation netlist : Processing  Generate Functional

Simulation Netlist
Bc 25.

Chy m phng : Processing  Start Simulation.

Bc 26.

Quan st waveform ca Output v debug nu c li.

Hnh 4.35 Waveform sau khi chy m phng

4.1.5

Programming mch thit k ln FPGA :

Bc 1.

Kt ni Kit DE2 vi my tnh qua cng USB-Blaster (phi ci

t driver trc ).
Bc 2.

Bt ngun Kit DE2.

C 2 mode cho vic programming : JTAG v Active Serial modes


JTAG mode
Bc 3.

Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN

Bc 4.

Trn mn hnh chnh Quantus II, chn Tools  Programmer

131

Hnh 4.36 Np thi k ln FPGA

Bc 5.

Nhn Hardware Setup , chn USB-Blaster[USB-0] (Ch :

phi ci t driver cho USB-Blater trc).

Hnh 4.37 Thit lp cng giao tip gia kit DE2 v Computer

Bc 6.

Nhn Close

Bc 7.

Chn Mode JTAG

Bc 8.

Nhn Add File , ch ng dn n File .sof (c to ra khi

chy Compilation).
Bc 9.

Check box Program/Configure

132

Hnh 4.38 Chn cu hnh np thit k

Bc 10.

Nhn Start.

Bc 11.

Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

Active Serial Mode :


Bc 12.

Chn Assignments  Devide

Hnh 4.39 Thit k ch np ln FPGA bng AS mode

Bc 13.

Chn Family : Cyclone II

Bc 14.

Chn Available devices : EP2C35F672C6

Bc 15.

Nhn Device & Pin Option


133

Bc 16.

Chn Tab Configuration

Hnh 4.40 Chn loi ROM tng ng

Bc 17.

Chn Configuration device : EPCS64 (h EPPROM trn Kit

DE2 , dng lu chng trnh np cho FPGA mi khi power on).


Bc 18.

Tng t JTAG nhng bc k tip :

Bc 19.

Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN

Bc 20.

Trn mn hnh chnh Quantus II, chn Tools  Programmer

Bc 21.

Chn Hardware Setup : USB-Blaster[USB-0]

Bc 22.

Chn Mode : Active Serial Programming

Bc 23.

Nhn Add File, ch ng dn n File .pof (File c to ra

trong qu trnh chy Compilation).

134

Hnh 4.41 Chn file thit k .pof


Bc 24.

Check box Program/Configure.

Bc 25.

Nhn Start programming chng trnh cho EPPROM.

Bc 26.

Nhn Phm Restart trn Kit DE2,

Bc 27.

Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

4.2 Ni dung thc hnh mn H thng s


4.2.1

Bi thc hnh s 1 Switchs, Lights, Multiplexers

Mc ch ca Lab 1: Hc cch kt ni n gin nhng ng vo v ng ra


ca linh lin n FPGA v thit k mt s mch in n gin s dng nhng linh
kin trn Kit DE2 nh l ng vo v ng ra ca mch thit k. Trong Lab ny, ta s
s dng Switch SW17-SW0 trn Kit DE2 nh l ng vo ca mch v s dng
LED v LED by on nh l ng ra ca mch. lm tt Lab1, sinh vin cn
phi nm trc nh v cch thit k, bin dch v m phng mt mch in n
gin trn Quartus II.
4.2.1.1 Phn 1

Tng bc thc hin:


Bc 1.

To mt project Quartus mi, t tn: user_dir/lab1/lab1_par1

Bc 2.

Thit k mt mch nh sau:


135

Hnh 4.42 Thit k n gin

Bc 3.

Gn pin cho mch trn

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

4.2.1.2 Phn 2

1. Cho mch sau:

Hnh 4.43 Mch s n gin


Bc 1.

Nu hot ng ca mch trn v vit bng s tht cho mch.


136

2. Cho mch sau:

Hnh 4.44 Mch gm 8 MUX 2-1

Bc 2.

Nu hot ng ca mch trn

Bc 3.

To

mt

project

user_dir/lab1/lab1_part2
Bc 4.

Thit k mt mch nh sau:

137

Quartus

mi,

tn:

Hnh 4.45 Mch 8 MUX 2-1 vi SW v LED


Bc 5.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.

4.2.1.3 Phn 3

Cho mch sau:

138

Hnh 4.46 Mch chn knh


Bc 1.

Nu hot ng ca mch trn v vit bng s tht cho mch.

Bc 2.

To

mt

project

Quartus

mi,

tn:

user_dir/lab1/lab1_part3
Bc 3.

Thit k mt mch nh sau:

Hnh 4.47 Mch chn knh 3 input


Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
139

Bc 6.

Np file thc thi ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

4.2.1.4 Phn 4

Cho mch sau:

Hnh 4.48 Mch gii m HEX


Di y l bng s tht ca mch gii m cho Led 7 on trn dng hin
th mt trong 4 k t H, E, L, O.

Hnh 4.49 Bng gii m


140

Bc 1.

Sinh vin hon thnh bng s tht trn. ( Ch : Cc on LED

tch cc mc thp).
Bc 2.

Da vo bng s tht, thit k mch gii m cho LED 7 on

trn.
Bc 3.

To

mt

project

Quartus

mi,

tn:

user_dir/lab1/lab1_part4
Bc 4.

Thit k mch nh hnh trn.

Bc 5.

Bin dch phn tch, tng hp v to ra file .sof

Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.

4.2.1.5 Phn 5

Cho d liu mch in nh sau:

Hnh 4.50 Mch chn knh v hin th

141

Da vo nhng d kin cho hnh trn v kin thc nm c


t Part1 n Part4, hy thit k mch in hot ng theo bng s tht
sau ( Ch : c th thit k bng nhiu cch, c th s dng ht cc
SW hoc s dng mt s SW ty vo cch thit k)

Hnh 4.51 Mode hin th

4.2.2

Bi thc hnh s 2 S v cch hin th

Mc ch lab 2: Thit k mch chuyn t s nh phn sang thp phn v


mch cng s BCD
Hng dn cch ng gi v ti s dng 1 mch thit k
Bc 1.

To 1 file .bdf, v mch cn s dng li trn .

Bc 2.

Chn File  Create / Update  Create symbol file for

current file, to ra file .bsf

142

Bc 3.

Sau khi to ra file .bsf, s dng li mch ny bng cch chn

Symbol Tool

Hnh 4.52 Ca s to Symbol


Nu mch ng gi s dng trn cng project lm vic, ta c th thy
symbol tng ng trong mc Project.
Nu mch ng gi s dng khng cng project lm vic, ta c th ly
symbol bng cch ch ng dn n file .bsf tng ng.
4.2.2.1 Phn 1

S dng 16 Switch v 4 n Led 7 on thit k mch nh hnh Hnh 4.53.


Lu mi Led 7 on ch hin th gi tr t 0 n 9, cc gi tr t 1010 n 1111 s
khng cn xem xt.

143

Hnh 4.53 Mch gii m hin th HEXA


Tng bc thc hin:
Bc 1.

To project Quartus mi, t tn user_dir/lab2/part1

Bc 2.

Thit k mch nh Hnh 4.53

Bc 3.

Gn pin cho mch hnh trn

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

144

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin chun b trc nhng cng vic sau (Khng c bi chun
b khng c vo lp lm th nghim  tnh vng bui )
c v thc hin cc bc t 1 n 5 nh
4.2.2.2 Phn 2

Phn I chuyn t s nh phn 4 bit sang s thp phn dng 1 n led 7


on. Yu cu ca Phn II l s dng 2 led 7 on c th biu din thm cc s
thp phn t 10 n 15.
Mt phn thit k ca mch ny c gi nh hnh Hnh 4.54

Hnh 4.54 Mch hin th t 0 n 15

145

Mch hnh 2 bao gm 1 khi comparator kim tra khi no gi tr ca s


nh phn 4 bit (v3v2v1v0) ln hn 9 v s dng output ca comparator ny iu
khin led 7 on.
Tng bc thc hin:
Bc 1.

To project Quartus mi, t tn user_dir/lab2/part2

Bc 2.

Thit k mch nh hnh Hnh 4.54

Bc 3.

M t hot ng ca mch trn

Bc 4.

Thit k cc khi Comparator , Circuit A

Bc 5.

Gn pin cho mch trn


 Input v3v2v1v0 c gn ti SW[3:0]
 Output 2 Led 7 on c gn ti HEX0 v HEX1

Bc 6.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 7.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 8.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin chun b trc nhng cng vic sau (Khng c bi chun
b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 7
4.2.2.3 Phn 3

1. Cho mch sau

Hnh 4.55 Mch FA


146

Bc 1.

Nu hot ng ca mch trn v vit bng s tht cho mch

2. Cho mch sau

Hnh 4.56 Mch cng FA 4 bit


Trong hnh Hnh 4.56, FA l 1 khi th hin cho mch hnh Hnh 4.55.
Bc 2.

Nu ngha hot ng ca mch ny.

Bc 3.

To project Quartus mi, t tn user_dir/lab2/part3

Bc 4.

Thit k mch nh hnh Hnh 4.55, sau s dng mch ny

thit k mch nh Hnh 4.56


Bc 5.

Gn pin
 Input a3a2a1a0 c gn ti SW[3:0], input b3b2b1b0 c gn
ti SW[7:4], input cin c gn ti SW[8].
 Output s3s2s1s0 v cout ln lt c gn ti LEDG[3:0] v
LEDG[4].
 Kt ni cc SW ra LEDR kim tra gi tr nhp vo.

Bc 6.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 7.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 8.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Sinh vin chun b trc nhng cng vic sau (Khng c bi chun b khng
c vo lp lm th nghim  Tnh vng bui )
147

Thc hin cc bc t 1 n 6
4.2.2.4 Phn 4

Thit k mch cng 2 s BCD


Bc 1.

To project Quartus mi, t tn user_dir/lab2/part4

Bc 2.

Thit k mch cng 2 s BCD vi input ca mch l 2 s BCD

mt ch s A, B v 1 bit cin.
Bc 3.

Gn pin
 S dng SW[3:0] cho A, SW[7:4] cho B va SW[8] cho cin. Kt
ni cc SW ny ra LEDR kim tra kt qu. Gi tr BCD ca A
c hin th trn HEX6, ca B hin th trn HEX4.
 Output l s BCD 2 ch s S1S0.
 S dng cc LEDG hin th kt qu ca 4 bit tng v s d.
Gi tr BCD ca S1S0 c hin th trn HEX1 v HEX0

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Sinh vin chun b trc nhng cng vic sau (Khng c bi chun b khng
c vo lp lm th nghim  tnh vng bui )
Thc hin cc bc t 1 n 5
4.2.2.5 Phn 5

Thit k mch cng 2 s BCD hai ch s A1A0 v B1B0 , tng l s BCD ba


ch s S0S1S2.
Bc 1.

To project Quartus mi, t tn user_dir/lab2/part5

148

Bc 2.

Thit k mch cng 2 s BCD hai ch s vi input ca mch l

2 s BCD hai ch s A1A0 v B1B0.


Bc 3.

Gn pin
 S dng SW[15:8] cho A1A0, SW[7:0] cho B1B0. Kt ni cc
SW ny ra LEDR kim tra kt qu. Gi tr BCD ca A1A0
c hin th trn HEX7 v HEX6, ca B1B0 hin th trn
HEX5 v HEX4.
 Output l s BCD 3 ch s S1S0 S2.
 Gi tr BCD ca S1S0 S2 c hin th trn HEX2, HEX1 v
HEX0

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Sinh vin chun b trc nhng cng vic sau (Khng c bi chun b khng
c vo lp lm th nghim  Tnh vng bui )
Thc hin cc bc t 1 n 5

149

4.2.3

Bi thc hnh s 3 Latch, Flip-flop, Register

Mc ch: Hiu hot ng, thit k Latch, Flip-flop v Register.


4.2.3.1 Phn 1

Thit k mt mch in ht sc n gin nh sau:


Tng bc thc hin:
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part1
Bc 2.

Thit k mt mch nh sau:

Hnh 4.57 Mch latch

Bc 3.

Gn pin cho mch trn vi SW[0] lm xung CLK, SW[1] iu

khin input R, SW[2] iu khin input S, gn output Qa ti LEDR0, Qb


ti LEDR1
Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

150

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )

Hnh 4.58 Gin xung input ca mch latch RS


V gin xung vi inputs Clock, S, R nh hnh trn  output Qa
tng ng.
c v thc hin cc bc 1 n 5 nh.

4.2.3.2 Phn 2

Cho mch sau:

151

Hnh 4.59 mch D latch

Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part2
Bc 2.

Gn pin cho mch trn vi SW[0] lm xung CLK, SW[1] iu

khin input D, gn output Q ti LEDR0.


Bc 3.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 4.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 5.

Np file thc thi ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )

Hnh 4.60 Gin xung input ca D latch


V gin xung vi inputs Clock, D nh hnh trn  output Qa
tng ng.
c v thc hin cc bc 1 n 4 nh.
152

4.2.3.3 Phn 3

Cho mt D flip-flop Master-Slaver sau, vi Master v Slave l hai D latch:

Hnh 4.61 Mch D-Flipflop

Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part3
Bc 2.

Gn pin cho mch trn vi SW[0] lm xung CLK, SW[1] iu

khin input D, gn output Q ti LEDR0.


Bc 3.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 4.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 5.

Np file thc thi ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )

153

Hnh 4.62 Gin xung input D Flipflop


V gin xung vi inputs Clock, D nh hnh trn  output Q
tng ng.
Nu s khc nhau gia D flip-flop Master-Slaver vi D latch, ti sao
ta phi s dng D flip-flop Master-Slaver.
c v thc hin cc bc 1 n 4 nh.

4.2.3.4 Phn 4

Cho mch sau vi mt D-FF tch cc mc cao, mt D-FF tch cc cnh ln,
mt D-FF tch cc cnh xung v mt D-FF tch cc mc thp. Thit k mch to
D-FF tch cc cnh ln v D-FF tch cc cnh xung v D-FF tch cc mc thp (
c th tham kho trn Internet), sau thit k mch nh hnh di:

154

Hnh 4.63 Latch v Flipflop


Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part4
Bc 2.

Gn pin cho mch trn vi SW[0] lm xung CLK, SW[1] iu

khin input D, gn output Qa ti LEDR0, Qb ti LEDR1, Qc ti LEDR2,


Qd ti LEDR3.
Bc 3.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 4.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 5.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )

155

Hnh 4.64 Gin xung input


Vi gin xung input Clock, D nh trn hy v tn hiu xung ng ra
Qa, Qb, Qc v Qd.
c v thc hin cc bc 1 n 4 nh.

4.2.3.5 Phn 5

Thit k mt mch hin th LED 7 on vi yu cu nh sau:


 Hin th s Hexa A : 1357 ln 4 LED HEX[3:0], vi s 1357 c
nhp t t 16 switchs SW[15:0]
 Hin th s Hexa B : 2468 ln 4 LED HEX[7:4], vi s 2468 cng
c nhp t t 16 switchs SW[15:0]
 iu khin SW s A hin th trc, sau iu khin SW
hin th s B trong khi s A vn c gi khng i.
 Mch c th Reset li tt c LED HEX[7:0] tr v 0. V nhp li
gi tr bt k cho A v B.

Gi : Cht gi tr inputs ca s A vo cc mch latchs. Ly nt nhn KEY0


nh l tn hiu CLK v KEY1 l tn hiu RESET bt ng b.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
Thit k s khi ca mch ( trn bi chun b)
Thit k mch chi tit trn QuartusII.
156

To file Vector Waveform (.vwf) v chy m phng kim tra hot


ng ca mch.
Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

4.2.4

Bi thc hnh s 4 B m (Counters)

Mc ch: tm hiu hot ng v thit k b m


4.2.4.1 Phn 1

Tm hiu v b m tun t (hay cn gi l b m khng ng b hoc ni


tip) s dng T flipflop
Tng bc thc hin
Bc 1.

To

mt

project

user_dir/lab4/lab4_part1
157

Quartus

mi,

tn:

Bc 2.

Thit k 3 b m vi yu cu nh sau:

 B m th 1: M = 8 (M l h s m hay cn gi l dung lng b


m), m t 0 n 7
 B m th 2: B m ngc t 7 ti 0
 B m th 3: M = 6, m t 0 n 5
Bc 3.

Gn pin cho tng mch trn


 KEY0 cho Clock v SW1, SW0 cho Enable v Reset input ca
cc flipflop.
 LED 7 on hin th kt qu di dng s thp phn.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Sinh vin thc hin trc cc cng vic sau (khng bi chun b khng c
vo lp lm th nghim  Tnh vng bui )
T bc 1 n bc 5
4.2.4.2 Phn 2

Tm hiu v b m song song (hay cn gi l b m ng b).


Tng bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

user_dir/lab4/lab4_part2
Bc 2.

Thit k cc b m vi yu cu nh sau:

 B m th 1: M = 16, m t 0 n 15 (s dng T_flipflop)


 B m th 2: M = 5, m t 0 n 4 (s dng JK_flipflop)
Bc 3.

Gn pin cho tng mch trn

158

tn:

 KEY0 cho Clock v SW1, SW0 cho Enable v Reset input ca


cc flipflop.
 LED 7 on hin th kt qu di dng s thp phn.
Bc 4.

Bin dch phn tch, tng hp v to ra file .sof

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Sinh vin thc hin trc cc cng vic sau (khng bi chun b khng c
vo lp lm th nghim  Tnh vng bui )
Thc hin cc cng vic t bc 1 n bc 5
Nu nhn xt u khuyt im ca b m tun t v b m song
song
4.2.4.3 Phn 3

S dng xung clock 1Mhz c cung cp (file gi km) thit k mch


nh sau: dng 8 LED 7 on (HEX7 ti HEX0) hin th ch HELLO sao cho c
sau khong thi gian xp x 1s, ch s c di chuyn t phi sang tri nh bng
sau:

159

Hnh 4.65 Bng ni dung hin th


Sinh vin thc hin trc cc cng vic sau (khng bi chun b khng c
vo lp lm th nghim  tnh vng bui )
Thit k mch, gn pin, bin dch, chy m phng trn Quartus

160

4.2.5

Bi thc hnh s 5 Adder, Subtractor, Multiplier of two signed numbers in 2scomplement form

Mc ch: Tm hiu phng php thit k mt s mch s hc nh l mch


cng, mch tr v mch nhn 2 s c du di dng b -2.
4.2.5.1 Phn 1

Thit k mt mch cng 2 s 8 bit c du dng b -2.


Tng bc thc hin:
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab5/lab5_part1
Bc 2.

Da vo mch hnh di, thit k mch cng 2 s 8 bit c du

dng b -2.

161

Hnh 4.66 Mch cng hai s c du b 2

Bc 3.

Gn pin cho mch trn nh sau:


 SW[15:8] => A[7:0]
 SW[7:0] => B[7:0]
 KEY0 l tn hiu xung Clock
 LEDR[7:0] => S[7:0]
 LEDG8 => Overflow ; Overflow = 1 khi S nm ngoi gi tr biu
din ca s c du 8 bit dng b -2.
 HEX[7:6] hin th gi tr hexadecimal ca s A.
 HEX[5:4] hin th gi tr hexadecimal ca s B.
 HEX[1:0] hin th gi tr hexadecimal ca s S.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

162

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

4.2.5.2 Phn 2

Thit k mt mch tr 2 s 8 bit c du dng b -2.


Tng bc thc hin:
Bc 1.

To mt project Quartus mi, t tn: user_dir/lab5/lab5_part2

Bc 2.

Da vo mch hnh di, thit k mch tr 2 s 8 bit c du

dng b -2.

163

Hnh 4.67 Mch cng hai s c du b 2


Bc 3.

Gn pin cho mch trn nh sau:


 SW[15:8] => A[7:0]
 SW[7:0] => B[7:0]
 KEY0 l tn hiu xung Clock
 LEDR[7:0] => S[7:0]
 LEDG8 => Overflow; Overflow = 1 khi S nm ngoi gi tr biu
din ca s c du 8 bit dng b -2.
 HEX[7:6] hin th gi tr hexadecimal ca s A.
 HEX[5:4] hin th gi tr hexadecimal ca s B.
 HEX[1:0] hin th gi tr hexadecimal ca s S.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.


164

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

4.2.5.3 Phn 3

Thit k mt mch nhn 2 s 4 bit c du dng b -2.


Tng bc thc hin:
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab5/lab5_part3
Bc 2.

Da vo mch hnh di, thit k mch nhn 2 s 4 bit c du

dng b -2.

Hnh 4.68 Mch nhn hai s c du b 2

Bc 3.

Gn pin cho mch trn nh sau:


165

 SW[11:8] => A[3:0]


 SW[3:0] => B[3:0]
 KEY0 l tn hiu xung Clock
 LEDR[3:0] => S[3:0]
 LEDG8 => Overflow; Overflow = 1 khi S nm ngoi gi tr biu
din ca s c du 4 bit dng b -2.
 HEX[6] hin th gi tr hexadecimal ca s A.
 HEX[4] hin th gi tr hexadecimal ca s B.
 HEX[0] hin th gi tr hexadecimal ca s S.
Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

166

167

Chng 5.

Hng dn thit k v thc hnh mn Thit k


mch dng Verilog HDL trn Kit DE2

5.1 Hng dn thc hnh


5.1.1

To mt project trn Quartus II

Bc 1.

Start  Programs  Altera  Quartus II 7.2  Quartus

II 7.2 (32 -Bit)

Hnh 5.1 Mn hnh chnh Quartus

Bc 2.

Nhn tab File trn mn hnh chnh

168

Hnh 5.2 Tab File

Bc 3.

M mt project mi : File  New Project Wizard

Hnh 5.3 To project mi

Bc 4.

Nhn Next
169

Hnh 5.4 Nhp ng dn v tn project

Bc 5.

Nhp ng dn th mc ca project ( c th to trc hoc

nu cha to s c t ng to ).
Bc 6.

Nhp tn ca project.

Bc 7.

Nhp top-level ca thit k cho project ( nn cho ging tn ca

project ).
Bc 8.

Nhn Next

Bc 9.

Nu ng dn th mc ca project cha c to trc :

Hnh 5.5 ng dn cha tn ti


170

Bc 10.

Nhn Yes

Hnh 5.6 Add cc file lin quan n project

Bc 11.

Nhn Next

Hnh 5.7 Chn tn FPGA

171

Bc 12.

Chn Family : Cyclone II

Bc 13.

Chn Available devices : EP2C35F672C6

FPGA Cyclone II trn Kit DE2).


Bc 14.

Nhn Next

Hnh 5.8 Thit lp thng s EDA

Bc 15.

Nhn Next

172

(H ca Chip

Hnh 5.9 Project mi c to

Bc 16.

Nhn Finish ch v mn hnh chnh.

Hnh 5.10 Ca s Quartus sau khi project mi c to


173

5.1.2

Thit k mt mch in n gin (cng XOR) dng Verilog trn Quartus II:

Hnh 5.11 Mch s n gin


Bc 1.

M File  New

Hnh 5.12 Chn mi trng thit k Verilog

Bc 2.

Chn Verilog HDL File

174

Hnh 5.13 Ca s thit k Verilog


Bc 3.

Save as file : File  Save as

Hnh 5.14 Lu thit k

Bc 4.

M t thit k bng ngn ng Verilog cho cng XOR vo ca

s Text Editor. Nh phi t tn ca top-level module phi ging tn ca


Project. (Trong th d ny l light).

175

Hnh 5.15 M t thit k

Bc 5.

Save : File  Save

Mt s cch to Verilog khc :


Dng Verilog template :
Edit  Insert Template  Verilog HDL

Hnh 5.16 Chn template Verilog


176

a File vo project (c th a mt hoc nhiu File vo Project,


chng hn nh File cha top-level module v nhng Files cha sublevel module). Cc bc thc hin
Bc 1.

Assignments  Settings

Bc 2.

Chn Category : Files

Hnh 5.17 Add file Verilog lin quan

Bc 3.

Nhn vo button

177

Hnh 5.18 Ch ng dn

Bc 4.

Ch ng dn ca nhng Files verilog .v cn a vo Project.

.
5.1.2.1 Trnh bin dch

Vi d liu vo l file nh dng .v( light.v), nhiu cng c trong phn


mm Quartus II c dng phn tch, tng hp mch c thit k phn
trn, ri sau s to ra mt file thc thi dng np ln FPGA. Nhng cng c
c s dng trong qu trnh ny c gi l trnh bin dch. thc thi qu trnh
bin dch, ta thc hin cc bc sau:
Bc 1.
tng

Chn: Processing  Start Compilation hoc nhn chn biu


trn thanh cng c. Sau khi qu trnh bin dch c hon tt,

mt bng bo co c to ra nh hnh di

178

Hnh 5.19 Ca s sau qu trnh bin dch

Bc 2.

xem li qu trnh bin dch, ta chn : Processing 

Compilation Report hoc nhn chn biu tng

trn thanh cng

c.
5.1.2.2 Message window

Phn mm Quartus II s hin th thng tin trong sut qu trnh bin


dch trn ca s Message widow. Nu s mch in c thit k trong phn
Graphic Editor hon ton ng, th mt thng bo The compilation was
successful c hin th. Trong trng hp qu trnh bin dch xut hin li th c
ngha c li xy ra trong qu trnh thit k trn Graphic Editor. Mi thng bo
tng ng vi mt li c tm thy s xut hin trn ca s Message. Nhp p
vo thng bo li ta s bit r hn v li xy ra trn mch in. Tng t,
trnh bin dch cng thng bo mt s cnh bo Warning. Ngoi ra ta cng c

179

th tm hiu thm thng tin v li cng nh cnh bo bng cch nhn chn vo
thng bo ri nhn phm F1 trn bn phm.
5.1.3

Gn pin

V ta cha thc hin gn pin trn FPGA cho linh kin trong mch in
thit k trn nn khi thc hin bin dch th trnh bin dch Quartus II gn
chn ca linh kin vi pin ca FPGA mt cch ngu nhin. Tuy nhin, gi s trong
thit k cng XOR n gin trn, sau khi thit k c bin dch v np ln
FPGA, ta mun hai ng vo x1, x2 c iu khin bi hai switch SW0 v SW1
cn kt qu ng ra f s c th hin trn led LEDG0 (SW0, SW1, LEDG0 c
ghi trn Kit). Mt khc ta bit switch SW0 c kt ni c nh vi pin N25 ca
FPGA, tng t vy switch SW1 c kt ni c nh vi pin N25 ca FPGA v
led LEDG0 c kt ni c nh vi pin AE22 ca FPGA. thc hin c iu
ta phi gn chn linh kin trn mch (x1, x2, f) vi pin tng ng trn FPGA
(N25, N26, AE22). gn pin ta thc hin cc bc sau
Bc 1.

Chn Assignments > Pins, mt ca s nh hnh di s xut

hin

180

Hnh 5.20 Ca s mapped pin gia thit k v FPGA

Bc 2.

Trong mc Category chn Pin. Nhp p ln mc <<new>>

trong ct To. Mt ca s nh hnh di xut hin

Hnh 5.21 Ca s gn pin


Bc 3.

Nhn chn x1 gn pin trc, tip n nhp p ln mc ngay

bn phi ca x1 trong ct Location, mt ca s nh hnh di s xut


hin

181

Hnh 5.22 Ca s lit k danh sch pin ca FPGA

Bc 4.

Ta nhp chn PIN_N25.

Bc 5.

Tng t, ta gn pin cho chn ng vo x2 ti pin PIN_N26, v

chn ng ra f ti pin PIN_AE22. Sau khi gn pin hon tt, ta s c nh


hnh di

Hnh 5.23 Ca s sau gn pin

Bc 6.

Lu li kt qu gn pin: File  Save

Bc 7.

Ta phi bin dch li thit k trn vi kt qu gn pin ny v

nh ta ni trn, v qu trnh bin dch trn, trnh bin dch Quartus


182

II ch gn pin mt cch ngu nhin nn s khng ng vi yu cu thit


k ca ta, do ta phi gn li pin cho ng vi yu cu ri phi chy li
qu trnh bin dch. Lc ny trnh bin dch Quartus II s s dng nhng
pin m ta gn cho chn ca mch in trong thit k phn tch, tng
hp v to ra mt file thc thi vic np xung cho FPGA.
Ngoi ra ta cng c mt cch khc gn pins cho design, c bit l rt
hu ch trong thit k m c nhiu chn, ta khng th ngi gn pin cho tng chn
c v s tn nhiu thi gian, Quartus II cung cp mt phng php gip ta gn
nhiu pin vo hoc g nhiu pin ra cng mt lc bng mt file c nh dng c
bit dng cho mc ch ny l nh dng .CSV. Format ca file ny nh sau
Nu ta dng file text to file ny, th n gin ta ch cn nhp theo
mu sau

To, Location
x1, PIN_N25
x2, PIN_N26
f, PIN_AE22
Nu ta dng Microsoft Excel, th ta s c format nh sau:

Hnh 5.24 Dng Microsoft Excel to file gn pin


183

Sau khi to file c format nh trn, ta s thc hin vic gn pin nh

sau
Bc 8.

Chn Assignments -> Import Assignments, mt hp thoi

nh hnh di xut hin

Hnh 5.25 Import file gn pin

Bc 9.

Click button , ch ng dn ca file ta va to trn. Ri

nhn OK.
thun tin cho ngi s dng Altera cung cp mt file CSV c tn
DE2_pin_assignments, file ny lit k tt c cc pin ca FPGA, c format nh sau:

184

Hnh 5.26 File gn pin to sn bi Altera

Nu ta mun s dng file c sn ny vo vic gn pin cho thit k ca ta th


mt yu cu bt buc khi ta t tn cho chn linh kin phi trng vi tn trong ct
To ca file ny. Th d, nu ta mun hai chn ng vo ca cng XOR c iu
khin bi hai Switch 0 v Switch 1 trn Kit DE2 th ta phi t tn cho hai chn
ny ln lt l SW[0], SW[1] nh trong ct To ca file ny. Do ta phi tham
kho file ny trc khi t tn cho chn linh kin khi gn pin ta s rt thun tin
l khng phi to file.csv na m ch cn Import file c sn ny vo thi.
Sau khi gn pin xong, ta bin dch li.
Re- compiling design : Processing  Start Compilation
Review Compilation report : Processing  Compilation Report
5.1.4

M phng mch thit k :

Bc 1.

To input waveform : File  New  Other Files  Vector

Waveform File
185

Hnh 5.27 To waveform

Bc 2.

Nhn OK

Hnh 5.28 Ca s to waveform

Bc 3.

Chn thi gian thc hin m phng : Edit  End Time

Bc 4.

Nhp thi gian thc hin m phng.

Bc 5.

Fit windown : View  Fit in Windown

Bc 6.

To waveform cho inputs : Edit  Insert Node or Bus

186

Hnh 5.29 Nhp tn signal ca thit k


Bc 7.

Chn Node Finder

Hnh 5.30 Dng chc nng Node Finder

Bc 8.

Chn Filter : Pins : all

Bc 9.

Nhn button List

Bc 10.

Chn signal bn Nodes found ; nhn >> chuyn sang bn

Selected Nodes
Bc 11.

Nhn OK

187

Hnh 5.31 To input waveform

Bc 12.

Chn mt input signal bng cch nhp chut vo signal .

Bc 13.

Chn biu tng mi tn con tr

Bc 14.

Di chuyn con tr sang mn hnh waveform .

Bc 15.

Nhn v gi chut v ko r (left) trong mt khong thi gian

(gi s ta mun trong khong thi gian t 40ns -> 60 ns , SW0 signal c
gi tr 1, th ta nhn , gi v r chut trong khong thi gian t 40ns ->
60ns.

Hnh 5.32 To mc logic "1"

Bc 16.

Nhn button 1 pha bn tri mn hnh

188

Hnh 5.33 Mc logic "1" c to


Bc 17.

Tng t cho nhng tn hiu inputs khc, khng to waveform

cho outputs ( XXX).


Bc 18.

Save File Waveform : File  Save As

Bc 19.

Thit lp thc hin m phng : Assignments  Setting

Hnh 5.34 Thit lp ch ch simulation

Bc 20.

Chn Simulator Settings

Bc 21.

Chn Simulation mode : Functional / Timing

Bc 22.

Ch ng dn ca input waveform va to.

Bc 23.

Nhn OK
189

Bc 24.

To simulation netlist : Processing  Generate Functional

Simulation Netlist
Bc 25.

Chy m phng : Processing  Start Simulation.

Bc 26.

Quan st waveform ca Output v debug nu c li.

Hnh 5.35 Waveform sau khi chy m phng

5.1.5

Programming mch thit k ln FPGA :

Bc 1.

Kt ni Kit DE2 vi my tnh qua cng USB-Blaster (phi ci

t driver trc ).
Bc 2.

Bt ngun Kit DE2.

C 2 mode cho vic programming : JTAG v Active Serial modes


JTAG mode
Bc 3.

Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN

Bc 4.

Trn mn hnh chnh Quantus II, chn Tools  Programmer

190

Hnh 5.36 Np thi k ln FPGA

Bc 5.

Nhn Hardware Setup , chn USB-Blaster[USB-0] (Ch :

phi ci t driver cho USB-Blater trc).

Hnh 5.37 Thit lp cng giao tip gia kit DE2 v Computer

Bc 6.

Nhn Close

Bc 7.

Chn Mode JTAG

Bc 8.

Nhn Add File , ch ng dn n File .sof (c to ra khi

chy Compilation).
Bc 9.

Check box Program/Configure

191

Hnh 5.38 Chn cu hnh np thit k

Bc 10.

Nhn Start.

Bc 11.

Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

Active Serial Mode :


Bc 3.

Chn Assignments  Devide

Hnh 5.39 Thit k ch np ln FPGA bng AS mode

Bc 4.

Chn Family : Cyclone II

Bc 5.

Chn Available devices : EP2C35F672C6

Bc 6.

Nhn Device & Pin Option


192

Bc 7.

Chn Tab Configuration

Hnh 5.40 Chn loi ROM tng ng

Bc 8.

Chn Configuration device : EPCS64 (h EPPROM trn Kit

DE2 , dng lu chng trnh np cho FPGA mi khi power on).


Bc 9.

Tng t JTAG nhng bc k tip :

Bc 10.

Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN

Bc 11.

Trn mn hnh chnh Quantus II, chn Tools  Programmer

Bc 12.

Chn Hardware Setup : USB-Blaster[USB-0]

Bc 13.

Chn Mode : Active Serial Programming

Bc 14.

Nhn Add File, ch ng dn n File .pof (File c to ra

trong qu trnh chy Compilation).

193

Hnh 5.41 Chn file thit k .pof


Bc 15.

Check box Program/Configure.

Bc 16.

Nhn Start programming chng trnh cho EPPROM.

Bc 17.

Nhn Phm Restart trn Kit DE2.

Bc 18.

Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

5.2 Ni dung thc hnh mn Thit k mch vi Verilog HDL


5.2.1

Bi thc hnh s 1 Thit k mch t hp v mch tun t n gin

Mc ch:
Thc hnh thit k mch t hp dng nhn hai s khng du 4 bits.
Thc hnh thit k mch tun t dng thanh ghi v b m.
5.2.1.1 Phn 1

Thit k mt mch nhn hai s 4 bits


Cc bc thc hin
Bc 1.

To

mt

project

user_dir/lab1/lab1_part1
194

Quartus

mi,

tn:

Bc 2.

M t thit k mt mch nhn hai s 4 bit s dng ngn ng

Verilog.
Bc 3.

Gn pin nh sau
 Dng switches SW11- 8 nhp s A v switches SW3-0
nhp s B. Gi tr ca A v B c hin th trn Led 7 on
HEX6 v HEX4 di dng s Hexa. Kt qu php nhn C=A*B
c hin th trn HEX1 v HEX0 cng di dng Hexa.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
5.2.1.2 Phn 2

M rng mch nhn sang 4 bit sang mch nhn 8 bit. Dng SW15-8 nhp
s A v switches SW7-0 nhp s B. . Gi tr ca A v B c hin th tng
ng trn cc Led 7 on HEX7-6 v HEX5-4 di dng s Hexa. Kt qu php
nhn C=A*B c hin th trn HEX3-0 cng di dng Hexa.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab1/lab1_part2
Bc 2.

M t thit k mt mch nhn hai s 8 bit s dng ngn ng

Verilog.
Bc 3.

Gn pin nh sau

195

 Dng switches SW15-8 nhp s A v switches SW7-0


nhp s B. Gi tr ca A v B c hin th trn Led 7 on
HEX7-6 v HEX5-4 di dng s Hexa. Kt qu php nhn
C=A*B c hin th trn HEX3-0 cng di dng Hexa.
Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

Part III
Ta mun hin th mt gi tr hexadecimal ca mt s A 16 bit trn bn Led 7
on HEX7-4 v hin th s B 16 bit trn bn Led 7 on HEX3-0. Gi tr ca A
v B u c cung cp bi SW15-0. Mun lm c iu ny th trc ht ta
phi nhp gi tr A t SW15-0 v phi lu tr gi tr ny vo thanh ghi trc khi
nhp gi tr mi cho B.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab1/lab1_part3
Bc 2.

M t thit k bng ngn ng Verilog c th thc hin c

chc nng trn.


Bc 3.

Gn pin nh sau

196

 Dng switches SW15- 0 nhp s A va B. Gi tr ca A v B


c hin th trn Led 7 on HEX7-4 v HEX3-0 di dng s
Hexa.
Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
5.2.1.3 Phn 4

S dng ngn ng Verilog m t thit k ca mt mch c chc nng l


hin th ln lt cc s 0 n 9 trn Led 7 on HEX0. Mi s s c hin th
trong khong thi gian l 1 giy. S dng mt b m xc nh khong thi
gian 1 giy . Xung Clock s dng cho b m l 50 MHz t Board DE2.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab1/lab1_part4
Bc 2.

M t thit k bng ngn ng Verilog c th thc hin c

chc nng trn.


Bc 3.

Gn pin nh sau
 S dng Led 7 on HEX0 hin th s.
 CLK_50 gn cho xung clock ca counter.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
197

Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

5.2.2

Bi thc hnh s 2 Thc hnh tm hiu thit k latches, flip-flops v counters.

Mc ch:
Thc hnh v tm hiu phng php thit k latches, flip-flops v
counter.
5.2.2.1 Phn 1

Trong Hnh 5.42 m t mt mch latch RS. Pha di Hnh 5.42 th hin hai
phong cch code Verilog c th dng m t mch latch RS trn. Phn a m t
198

latch bng vic gi v kt ni cc cng logic li vi nhau, cn trong phn b th s


dng biu thc logic to ra latch. Cn nu latch ny c thc thi dng bng
lookup tables 4 ng vo (LUTs) th ch cn mt bng lookup tables l , nh trnh
by trong hnh Hnh 5.43 a.

Hnh 5.42 Mt mch latch RS


// RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /*synthesis keep */;
and (R_g, R, Clk);
and (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule

a. Gi v kt ni cc cng logic to thnh mch RS latch.

199

// RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /*synthesis keep */;
assign R_g = R & Clk;
assign S_g = S & Clk;
assign Qa = !(R_g | Qb);
assign Qb = !(S_g | Qa);
assign Q = Qa;
endmodule
b. Dng cc biu thc logic m t mch latch RS.

V mch latch c th thit k m ch cn s dng mt LUT 4 input nh trong


Hnh 5.43 (tt nhin y ta ang ni complier cho mt FPGA no s s dng
LUT synthesize ra mch ch khng phi l dng cc cng logic ghp li), tuy
nhin vic thc thi ny khng cho php quan st c cc tn hiu bn trong ca n
khi chy m phng, chng hn nh R_g v S_g, bi v chng khng c cung cp
nh l output ca LUT. gi cc tn hiu bn trong ny khi thit k, ta cn phi
s dng hng dn trnh bin dch (compiler directive) trong code m t thit k.
Trong hnh 2, mt hng dn trnh bin dch /*synthesis keep */ c thm vo
hng dn trnh bin dch Quartus II bit rng cn phi s dng nhng cng logic
c lp cho mi tn hiu R_g, S_g, Qa, Qb, nh vy m ta c th quan st c cc
tn hiu bn trong mch latch. Sau qu trnh bin dch code m t Verilog, ta s c
mt mch vi bn LUT 4 input c m t trong hnh Hnh 5.43 b.
200

(a) S dng mt LUT 4 inputs to thnh RS latch

(b) S dng bn LUT 4 inputs to thnh RS latch.


Hnh 5.43 Mch thc hin trn FPGA cho mch RS latch
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab2/lab2_part1
Bc 2.

M t thit k mch RS latch nh trn Hnh 5.42 ( c th s

dng mt trong hai cch a hoc b, u to ra mch ging nhau)


Bc 3.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 4.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer v so snh vi mch trn hnh Hnh 5.43 b.


Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
201

5.2.2.2 Phn 2

Thit k mch D latch nh trn Hnh 4

Hnh 5.44 Mch D latch


Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab2/lab2_part2
Bc 2.

Dng Verilog HDL m t thit k mch D latch theo phong

cch code b. Dng hng dn trnh bin dch /*synthesis keep */ m


bo rng nhng phn t logic c lp c dng thc thi cc tn hiu
R, S_g, R_g, Qa, v Qb.
Bc 3.

Gn pin nh sau
 Dng switches SW0 iu khin tn hiu D v switches SW1
lm tn hiu xung Clock. LEDR0 c gn n Q.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer.
Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.


202

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.

5.2.2.3 Phn 3

Thit k mch master-slave D flip-flop nh trn Hnh 5.45.

Hnh 5.45 Mch master-slave D flipflop


Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab2/lab2_part3
Bc 2.

S dng Verilog HDL m t thit k mch master-slave flip-

flop trn, gi (instantiate) module D latch trn phn 2 thc thi D flipflop ny.
Bc 3.

Gn pin nh sau
 Dng switches SW0 iu khin tn hiu D v switches SW1
lm tn hiu xung Clock. LEDR0 c gn n Q.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer.
203

Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.
5.2.2.4 Phn 4

Thit k mt mch nh trn Hnh 5.46 vi 3 phn t nh khc nhau: mt D


latch, mt D flip-flop kch cnh ln, v mt D flip-flop kch cnh xung.

Hnh 5.46 Mch v dng sng ng vo cho phn 4


Cc bc thc hin
Bc 1.

To

mt

project

user_dir/lab2/lab2_part4
204

Quartus

mi,

tn:

Bc 2.

Dng Verilog HDL m t thit k mch mch trn bng cch

gi (instantiate) ba phn t nh t phn 2 v 3. Trong phn ny, ta khng


s dng hng dn trnh bin dch /*synthesis keep */ nh phn 1 n 3.
on code di th hin mt phong cch khc m t D latch trong
Hnh 5.44, l s dng m hnh hnh vi (behavioral style). Ta cng c
th s dng m hnh hnh vi ny m t mch trong Hnh 5.46.
module D_latch (input D, Clk, output Q);
reg Q;
always @ (D or Clk)
if (Clk)
Q = D;
endmodule
Code s dng m hnh hnh vi m t D latch
Bc 3.

Gn pin nh sau
 Dng switches SW0 iu khin tn hiu D v switches SW1
lm tn hiu xung Clock. LEDR0 c gn n Qa, LEDR1
c gn n Qb, LEDR2 c gn n Qc.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer.
Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.
205

5.2.2.5 Phn 5

Thit k mt mch m ng b 16 bit s dng T flip-flop da trn nh


mch m ng b 4 bit s dng T flip-flop trn Hnh 5.47. B m tng thm 1
ti mi cnh ln xung clock khi m tn hiu Enable c tch cc. B m c
Reset v 0 khi tn hiu Reset tch cc.

Hnh 5.47 Mt b m ng b 4 bit


Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part5
Bc 2.

Dng Verilog HDL m t thit k b m ng b 16 bit dng

2 cch: mt l da trn mch Hnh 5.47, hai l m t mch s dng m


hnh hnh vi (behavioral model).
Bc 3.

Gn pin nh sau
 Dng switches SW0 iu khin tn hiu Enable v switches
SW1 lm tn hiu xung Reset.
 KEY0 lm tn hiu xung Clock.
 Bn led 7 on HEX3-0 hin th gi tr m theo m hexa.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

206

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer. Thit k ny tn mt bao nhiu phn t logic (LEs)?


Tn s ln nht m mch thit k c th hot ng ? So snh khi thit
k theo hai cch trn.
Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.

207

5.2.3

Bi thc hnh s 3 Thit k h thng s dng xung Clock thi gian thc

Mc ch:
Thc hnh thit k v s dng xung Clock thi gian thc
5.2.3.1 Phn 1

Thit k mt mch m ba k s BCD. Hin th ni dung ca b m ln ba


led 7 on HEX2-0. To mt tn hiu iu khin t xung Clock 50 MHz ly t
board DE2, tn hiu iu khin ny dng iu khin tng b m ln 1 sau mt
khong 1 giy. Dng phm nhn KEY0 reset b m v 0.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part1
Bc 2.

M t thit k mt mch thc hin chc nng trn s dng

Verilog
Bc 3.

Gn pin nh sau
 Ng ra b m BCD ni n 3 led 7 on HEX2-0
 Chn Reset_n ni n KEY0

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
208

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Bc 6.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
5.2.3.2 Phn 2

Thit k v thc thi mt mch hot ng nh mt ng h ch thi gian. N


hin th gi (t 0 n 23) trn led 7 on HEX7-6, hin th pht (t 0 n 60) trn
HEX5-4 v giy (t 0 n 60) trn HEX3-2. Dng switches SW15-0 thit lp
gi tr gi, pht.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part2
Bc 2.

M t thit k mt mch thc hin chc nng trn s dng

Verilog
Bc 3.

Gn pin nh sau
 Ng ra ch gi ni n 2 led 7 on HEX7-6
 Ng ra ch pht ni n 2 led 7 on HEX5-4
 Ng ra ch giy ni n 2 led 7 on HEX3-2
 SW15-0 ni n chn thit lp gi tr gi, pht cho ng h.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
209

5.2.4

Bi thc hnh s 4 Thc hnh tm hiu thit k s dng State machine

Mc ch:
Thc hnh v tm hiu thit k h thng s dng State machines.
5.2.4.1 Phn 1

Thit k mt mch s dng lu my trng thi hu hn (FSM) kim


tra xem nu ng vo input w m c gi tr bng 0 hay bng 1 trong bn chu k lin
tc th ng ra z s c bt ln 1.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab4/lab4_part1
Bc 2.

S dng m hnh my trng thi trong Verilog m t thit k

cho mch c chc nng nh trn.


Bc 3.

Gn pin
 SW0 gn n chn input w.
 LEDG0 gn n chn output z
 KEY0 gn n chn xung Clock

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer.
Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.

210

Ch : Sinh vin cn chun b trc nh nhng cng vic sau ( Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
Np file thc thi .sof ln FPGA va quan st hot ng ca mch
c v thc hin cc bc t 1 n 6 nh.
5.2.4.2 Phn 2

Thit k mt mch m modulo-10 hot ng nh sau, ng ra b m c


tr v 0 bi ng vo Reset, hai ng vo w1, w0 dng iu khin vic m. Nu
w1w0 = 00, b m s gi nguyn gi tr, nu w1w0 = 01, b m tng mi ln ln
1, w1w0 = 10, b m tng mi ln ln 2, w1w0 = 11, b m tng mi gim i 1.
Tt c s thay i din ra ti cnh ln xung Clock.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab4/lab4_part2
Bc 2.

Dng m hnh my trng thi State machine trong Verilog HDL

m t thit k mch c chc nng nh trn


Bc 3.

Gn pin nh sau
 Dng switches SW0, SW1 iu khin tn hiu w0, w1.
 KEY0 iu khin xung Clock.
 Ng ra b m c hin th trn Led 7 on HEX0 di dng
s HEX.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer.
Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.


211

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.

5.2.4.3 Phn 3

Trong phn thit k ny gm hai bc:


 Thit k mch hin th t HELLO ln Led 7 on, sau cho
nhng k t ny dch t tri sang phi (t HEX0 n HEX7) trong
mi khong thi gian l mt giy.
 Ci tin thit k trn c th s dng hai input KEY3 v KEY2
iu khin tc dch ca cc k t t tri sang phi. Nu KEY2
c nhn, tc dch chuyn ca cc k t tng ln hai ln. Nu
KEY3 c nhn, tc dch chuyn ca cc k t gim i hai ln.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab3/lab3_part3
Bc 2.

S dng Verilog HDL m t thit k mch thc hin c chc

nng u tin ca mch. M phng v chy th kim tra mch, nu


ng th tip tc s dng m hnh my trng thi trong Verilog ci tin
mch thc hin c chc nng th hai.
Bc 3.

Gn pin nh sau
 Dng HEX0-HEX7 hin k t.
 Dng KEY2, KEY3 lm chn input iu khin tc dch.
 Dng xung Clock_50 to cc khong delay.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

212

Bc 5.

Quan st mch c to ra t m t Verilog trn dng cng c

Technology Viewer.
Bc 6.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 7.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 6 nh.

213

5.2.5

Bi thc hnh s 5 Thc hnh tm hiu phng php thit k onchip Memory trn
FPGA v phng php s dng offchip Memory

Mc ch:
Trong nhng h thng my tnh, lu tr chng trnh v lu tr d
liu n lun cn mt b nh vi dung lng lu tr. Nu mt h
thng c thc thi trn FPGA, th n c th s dng b nh c sn
trn FPGA (onchip memory) do nh sn xut h tr sn hoc ta cng
c th thit k b nh ngay trn FPGA (onchip memory). Tuy nhin,
nu dung lng b nh trn FPGA khng th mt b nh bn ngoi
FPGA (offchip memory) s cn c s dng. Do , trong phn thc
hnh ny ta s tm hiu ba vn sau:
 Tm hiu cch thc hin thc mt memory trn FPGA (onchip
memory)
 Tm hiu cch thc s dng mt offchip memory (SRAM chip trn
kit DE2).
 Chy m phng trn ModelSim
5.2.5.1 Phn 1

Altera cung cp mt th vin c sn LPM cha cc thit k c bn nh l


adders, registers, counters v memories (Quartus II Library of Parameterized
Modules). Ta c th s dng cc m t thit k ny thit k trn FPGA. thit
k mt b nh SRAM trn FPGA ta c th dng module altsyncram LPM do
214

Altera cung cp. Phn ny ta s thit k mt SRAM onchip c dung lng 32


words, mi word l 8 bits.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab5/lab5_part1
Bc 2.

S dng cng c MegaWizard Plug-in Manager trn Quartus

to ra RAM nh yu cu.
 Tools  MegaWizard Plug-in Manager

Hnh 5.48 Dng Tool to Mega Wizard


 Chn option Creat a new custom megafunction variation
215

Hnh 5.49 To mt Mega mi


 Chn RAM: 1-PORT trong danh sch cc megafunction
 Chn device family: Cyclone II
 Chn loi d liu ng ra: Verilog HDL
 Chn ng dn v tn cho file output

216

Hnh 5.50 Chn cc thng s nh hnh v


 Nhn Next
 Nhp cc thng s nh yu cu thit k.

217

Hnh 5.51 Chn thng s nh trn hnh


 Nhn Next
 Chn cc option nh hnh di

218

Hnh 5.52 Gn registers cho inputs


 Nhn Next
 Chp option No, leave it blank, bi v ta khng mun b nh
c d liu sn.

Hnh 5.53 Khng to gi tr ban u cho SRAM


 Nhn Next
219

Hnh 5.54 Simulation library


 Nhn Next
 Chn option to ra file m t thit k.v

220

Hnh 5.55 Chn cc loi d liu cn to ra


 Nhn Next

Hnh 5.56 Add d liu to ra vo project hin hnh


 Nhn Yes

221

 Mt m t thit k verilog cho mt b nh SRAM c to ra.

Hnh 5.57 M t verilog ca SRAM va to ra


Bc 3.

Bin dch phn tch, tng hp v to ra file .sof.

222

Bc 4.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch (ghi d liu vo SRAM, sau c cc d liu


ghi xem SRAM c hot ng ng khng).
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 4 nh.
5.2.5.2 Phn 2

Phn ny ta dng Switches trn kit DE2 ghi d liu vo SRAM to ra


phn 1. Sau dng Leds 7 on hin th d liu c c ra t SRAM
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab5/lab5_part2
Bc 2.

Add file m t thit k to ra trong phn 1 vo project. To

mt top-module instantiate module SRAM.


Bc 3.

Gn pin nh sau
 Dng switches SW[7:0] lm tn hiu d liu ng vo.
 Dng switches SW[15:11] lm tn hiu a ch.
 Dng HEX0, HEX1 hin th tn hiu d liu ng vo.
 Dng HEX2, HEX3 hin th tn hiu a ch.
 Dng HEX4, HEX5 hin th tn hiu ng ra.
 Dng SW[17] lm tn hiu WREN (khi WREN = 1, cho php
ghi, WREN = 0, cho php c)
 Dng KEY0 lm xung CLK.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
223

Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
5.2.5.3 Phn 3

Thay v s dng cc module thit k c sn trong LPM do Altera cung cp,


ta cng c th t m t thit k bi ring mnh s dng ngn ng Verilog. Trong
phn ny ta s t thit k mt b nh SRAM c dung lng 32 words, mi word 8
bits nh phn 1 m khng s dng module c sn. d hiu, ta c th xem b
nh SRAM trn nh l 32 thanh ghi, mi thanh ghi c di 8 bits. Hot ng c
v ghi ca cc thanh ghi ny c iu khin bi tn hiu WREN. Mi thanh ghi
c gn mt a ch xc nh.
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab5/lab5_part3
Bc 2.

S dng Verilog HDL m t thit k b nh SRAM nh trn.

Bc 3.

Gn pin nh sau
 Dng switches SW[7:0] lm tn hiu d liu ng vo.
 Dng switches SW[15:11] lm tn hiu a ch.
 Dng HEX0, HEX1 hin th tn hiu d liu ng vo.
 Dng HEX2, HEX3 hin th tn hiu a ch.
 Dng HEX4, HEX5 hin th tn hiu ng ra.
 Dng SW[17] lm tn hiu WREN (khi WREN = 1, cho php
ghi, WREN = 0, cho php c)
 Dng KEY0 lm xung CLK.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.


224

Bc 5.

Vit testbench v chy m phng dng ModelSim kim tra

hot ng v timing ca SRAM. (Trnh by trong Chng 7. )


Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.
5.2.5.4 Phn 4

Trn Kit DE2 c mt con chip SRAM bt ng b (offchip memory) c


dung lng 256 K 16-bit words (512K 8-bit words). Cc pin giao tip SRAM gm:
 Bus ADDRESS[17:0]
 Bus DATA [15:0], y l bus In/Out
 Chip Enable (/CE) tch cc mc thp.
 Write Enable (/WE): mc thp cho php ghi, khi c tn hiu ny
phi mc cao.
 Output Enable (/OE): mc thp th tn hiu ng ra mi valid.
 Upper Byte (/UB) v Lower Byte (/LB). Nu c UB v LB u tch
cc mc thp th 16 bits ng ra D[15:0] khi c u valid. Nu ch
UB tch cc mc thp th ch 8 bits cao D[15:8] khi c ra s valid,
ngc li nu ch LB tch cc mc thp th ch 8 bits thp D[7:0]
khi c ra s valid
Phn ny ta s tm hiu cch thc s dng offchip SRAM
Cc bc thc hin
Bc 1.

To

mt

project

Quartus

mi,

tn:

user_dir/lab5/lab5_part4
Bc 2.

S dng Verilog HDL m t thit k mt module giao tip gia

offchip SRAM v cc pin cng nh LEDs.


225

Bc 3.

Gn pin nh sau
 Dng switches SW[7:0] lm tn hiu d liu ng vo
DATA[15:0] = {8h00,SW[7:0]}.
 Dng switches SW[15:8] lm tn hiu a ch (vi 8 a ch ny
s gii m ra mt phn dung lng ca SRAM, ADDR[17:0] =
{10h000,SW[15:8]}.
 Dng HEX0-HEX3 hin th tn hiu ng ra.
 Dng KEY[0] lm tn hiu /OE.
 Dng KEY[1] lm tn hiu /WE
 Ni mc logic 0 cho c /LB v /UB.

Bc 4.

Bin dch phn tch, tng hp v to ra file .sof.

Bc 5.

To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.
Bc 6.

Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 5 nh.

END

226

Chng 6.

Hng dn thit k v thc hnh mn Kin trc


my tnh nng cao

6.1 Kin thc tng qut v vi x l Nios II


6.1.1

Gii thiu tng quan Nios II

6.1.1.1 C bn v b x l Nios II v h thng Nios II

B x l NIOS II l mt li x l RISC a nng, cung cp:


- Tp lnh, ng dn d liu v khng gian a ch dng full-32-bit
- 32 thanh ghi a dng
- 32 ngun ngt ngoi
- Nhn v chia 32 32 bng lnh n cho kt qu 32 bit
- Lnh chuyn dng cho tnh ton 64bit v 128bit ca php nhn
- Lnh du chm ng cho nhng thao tc lin quan n chm ng cn
chnh xc n.
- Giao tip vi nhiu thit b ngoi vi dng on-chip v interface ca b
nh v cc ngoi vi dng off-chip
- Khi tr gip g ri c th lm cho b x l bt u, dng, chy tng
bc lnh hay truy vt thng qua mt IDE (intergrated development
environment).
-

n v qun l b nh (MMU) ty chn h tr cc h iu hnh


yu cu MMU.

- n v bo v b nh (MPU) ty chn.
- Mi trng pht trin phn mm da trn chui cng c GNU C/C++
v Eclipse IDE.
- Tch hp vi Altera's SignalTap II Embedded Logic Analyzer, cho
php phn tch thi gian thc cc lnh v d liu cng vi cc tn hiu
khc trong thit k FPGA.
227

- Kin trc tp lnh (ISA) tng thch trn tt c cc h thng x l


Nios II.
- Hiu sut ln n 250 DMIPS
Mt h thng Nios II tng ng vi mt vi iu khin hoc my tnh
trn chip, bao gm mt b x l v kt hp cc thit b ngoi vi, b nh trn mt
chip n. Mt h thng x l Nios II bao gm mt nhn x l Nios II, mt tp hp
nhng thit b ngoi vi dng on-chip, b nh on-chip v cc interface ti b nh
off-chip, tt c u c thc hin trn mt thit b ca Altera. Ging nh mt h
vi iu khin, tt c h thng x l Nios II u s dng mt tp lnh v mt m
hnh lp trnh chung, nht qun.

Hnh 6.1 Mt v d v h thng x l Nios II


228

6.1.1.2

Nhng c trng khc bit ca h thng Nios II vi cc vi iu khin khc

Phn ny gii thiu nhng khi nim ring ca Nios II nhm cung cp nn
tng cc nh thit k phn cng c th iu chnh h thng mt cch linh hot.
6.1.1.2.1 B x l nhn mm kh cu hnh

Nios II l b x l nhn mm kh cu hnh, ngc li vi cc vi iu khin


c nh sn. Trong ni dung ny, cu hnh c ngha l c th thm hoc g b
cc chc nng trn nn tng h thng t c mc tiu v hiu sut hoc l gi
thnh. Nhn mm c ngha l nhn x l khng c nh trong silicon v c th
gn vi bt k h Altera FPGA no.
Kh nng ti cu hnh khng c ngha l phi cu hnh mi mi ln thit k.
Altera cung cp cc thit k h thng Nios II c lm sn m c th s dng
ngay. Nu cc thit k hp vi yu cu h thng ca ngi s dng th khng
cn phi thit k thm. Ngoi ra cc nh thit k phn mm c th dng chng
trnh m phng tp lnh ca Nios II bt u vit v sa li cc ng dng chy
trn Nios II trc khi xc nh cu hnh phn cng cui cng.
6.1.1.2.2 Tp hp cc ngoi vi v nh x a ch linh ng

Tp thit b ngoi vi linh ng l mt trong nhng im khc bit ng ch


gia h thng x l Nios II vi cc vi iu khin c nh. Vi mi trng nhn
mm ca Nios II, c th d dng xy dng h thng x l Nios II theo yu cu vi
cc tp ngoi vi chnh xc ng vi cc ng dng mun hng ti.
V s dng thit b ngoi vi linh hot nn s c nh x a ch linh hot.
Altera cung cp cc cch thc truy cp b nh v cc thit b ngoi vi mt cch
tng qut, khng ph thuc vo v tr a ch. V th cc b ngoi vi v nh x a
ch linh ng khng nh hng ti cc nh pht trin ng dng.
229

C 2 lp thit b ngoi vi: thit b ngoi vi chun v thit b ngoi vi ty


chnh.
Thit b ngoi vi chun: Altera cung cp mt tp hp cc thit b
ngoi vi thng dng, thng dng trong cc vi iu khin nh b m
(timer), giao din cho giao tip ni tip (serial communication
interfaces), xut nhp a dng (general-purpose I/O), b iu khin
SDRAM, v cc giao din b nh khc. Altera v cc n v lin quan
vn ang tip tc pht trin danh sch cc thit b ngoi vi ny.
Thit b ngoi vi ty chnh: Cng c th to ra cc thit b ngoi vi
ty chnh theo yu cu ca ng dng v tch hp chng vo h thng
x l Nios II. i vi cc h thng ch trng vo hiu nng, phi
thng xuyn thc thi mt chc nng ring bit, c trng no th
k thut thng thng s dng l to thit b ngoi vi ty chnh thc
hin chc nng thay v phn mm. Cch tip cn ny em li li
ch v hiu nng: phn cng thc thi nhanh hn phn mm; v b x
l c gii phng thc thi cc tc v song song khc trong khi
thit b ngoi vi ty chnh s thao tc vi d liu.
Lnh ty chnh
Ging nh thit b ngoi vi ty chnh, lnh cng cho php ty chnh theo yu
cu tng hiu nng ca h thng bng cch nng cp b x l vi phn cng ty
chnh. Bn cht nhn mm ca Nios II cho php tch hp cc thnh phn logic ty
chnh vo n v lun l s hc ALU. Tng t nh cc lnh c sn trong Nios II,
lnh ty chnh c th ly gi tr ti a trong 2 thanh ghi ngun v c th ghi li kt
qu vo thanh ghi ch ty .

230

6.1.1.2.3 T ng pht sinh h thng

Cng c thit k SOPC Builder ca Altera hon ton t ng ha qu trnh


cu hnh nhng c trng ca b x l v sinh ra mt thit k phn cng lp trnh
c trn FPGA. SOPC Builder cung cp giao din ha cho php cu hnh h
x l Nios II vi s lng thit b ngoi vi hay b nh khng hn ch. C th to
h thng x l hon chnh m khng cn thc hin bt k mt phc ha hay ngn
ng m t phn cng (HDL) no. SOPC Builder cng c th nhn cc file HDL,
cung cp cch n gin tch hp cc thnh phn logic ty chn vo trong h x
l Nios II.
Sau qu trnh pht sinh h thng c th a thit k vo bo mch v kim tra
li thc thi phn mm trn . Qu trnh pht trin phn mm c thc hin
tng t nh vi cc b x l khng ti cu hnh c.

6.1.1.3 Cc loi nhn x l Nios II

C ba dng nhn c trng ca b x l Nios II. Tt c cc nhn u h tr


kin trc tp lnh ca Nios II.
 Nios II/f Core
 Nios II/s Core
 Nios II/e Core
Nhn Nios II/f:
Nhn Nios II/f (fast) nhanh c thit k cho hiu nng thc thi cao.
Altera thit k nhn Nios II/f cho cc ng dng yu cu cao v hiu sut,
nht l vi cc ng dng c nhiu code v d liu, nh cc h thng hot ng
trong mt h iu hnh cha y tnh nng. Nhn Nios II/f c cu hnh nh sau:
- C b nh m lnh v d liu ring.
231

- Cung cp ty chn MMU h tr cc h iu hnh cn MMU.


- Cung cp ty chn MPU h cc h iu hnh v mi trng thc
thi cn phi bo v b nh nhng khng cn b qun l b nh o.
- C th c 2Gbyte khng gian a ch ngoi khi khng c MMU v
4Gbyte khi c MMU.
- H tr b nh tightly-coupled cho lnh v d liu.
- Thc thi tin on nhnh ng.
- Cung cp ty chn nhn, chia, dch bng phn cng tng tc x l
s hc.
- H tr lnh ty bin.
- Nios II/f h tr khi JTAG debug

Nhn Nios II/s:


Nios II/s (standar) chun c thit k cho dng core kch thc nh, chun.
Altera thit k Nios II/s cho cc ng dng m hiu sut dng trung bnh v
hiu sut khng phi l tiu chun c i hi cao nht. Nhn Nios II/s c cu
hnh nh sau
- C b nh m cho lnh nhng khng c b nh m cho d liu
- C truy xut ln n 2 Gbytes khng gian a ch trng bn ngoi.
- H tr b nh tightly-coupled cho lnh
- Thc hin tin on nhnh tnh
- Cung cp ty chn nhn, chia, dch bng phn cng tng tc x l
s hc
- H tr thm lnh ty bin.
- H tr khi JTAG debug

232

Nhn Nios II/e:


Nios II/e (ecommy) kinh t c thit k t c khch thc core nh
nht c th.
Altera thit k Nios II/e vi mc tiu gim ti nguyn s dng bng mi
cch c th trong khi vn duy tr c kh nng tng thch vi tp lnh Nios II.
Nios II/e core ch bng khong na kch thc ca Nios II/s core, nhng hiu sut
thc thi thc cht thp hn. Nhn Nios II/e c cu hnh nh sau:
- Thc thi ti a mt lnh mi su chu k ng h.
- C th truy xut ln n 2 Gbytes ca a ch trng bn ngoi.
- H tr b sung ca lnh ty bin.
- H tr JTAG debug module.
- Khng c b m lnh hoc m d liu
- Khng thc hin tin on phn nhnh

6.1.2

Kin trc b x l Nios II

6.1.2.1 Gii thiu

Kin trc Nios II gm cc n v chc nng chnh:


- Tp thanh ghi
- n v lun l s hc (ALU)
- Interface cho lnh ty chnh
- B iu khin ngoi l
- B iu khin ngt
- Bus lnh
- Bus d liu
- n v qun l b nh (MMU)
- n v bo v b nh (MPU)
233

- B nh m (d liu v lnh)
- Interface cho b nh tightly-coupled cho lnh v d liu
- JTAG debug module

Hnh 6.2 S khi Nios II processor

6.1.2.2 Tp thanh ghi

Kin trc Nios II h tr mt tp tin thanh ghi phng, cha 32 thanh ghi a
dng 32-bit, v ln n 32 thanh ghi iu khin 32-bit. Kin trc ny h tr ch
gim st (supervisor mode) v ch ngi dng (user mode), cho php bo v
234

cc thanh ghi iu khin t cc ng dng sai. Trong tng lai, kin trc Nios II cho
php b sung nhng thanh ghi chm ng.
6.1.2.3

n v lun l s hc (ALU)

ALU ca Nios II hot ng trn d liu c lu tr trong cc thanh ghi a


dng. Cc thao tc ca ALU nhn mt hoc hai d liu u vo t thanh ghi, v
lu tr kt qu tr li thanh ghi. ALU h tr cc thao tc c ch ra trong Bng
6.1
Bng 6.1 Thao tc h tr bi Nios II ALU

hin thc bt k thao tc no khc, phn mm s tnh ton kt qu bng


cch kt hp cc thao tc c bn trong Bng 6.1.
Ngoi ra, kin trc NIOS II h tr lnh ty chnh theo nh ngha ca ngi
dng, tham kho thm NiosII Custom Instruction User Guide ca Altera.
6.1.2.4

B iu khin ngoi l v b iu khin ngt (Exception and Interrupt Controller)

6.1.2.4.1 B iu khin ngoi l (Exception Controller)

Kin trc Nios II cung cp mt b iu khin ngoi l v hng n gin


x l tt c loi ngoi l. Mi ngoi l, bao gm c ngt phn cng, lm cho b x
l phi chuyn giao thc thi n mt a ch ngoi l. B iu khin ngoi l ti a
235

ch ny xc nh nguyn nhn gy ra ngoi l v thc hin mt th tc x l ngoi


l no .
a ch ngoi l c quy nh trong SOPC Builder ti thi im sinh h
thng.
6.1.2.4.2 B iu khin ngt tch hp (Integral Interrupt Controller)

Kin trc Nios II h tr 32 ngt cng ngoi. B x l c 32 u vo yu cu


ngt (IRQ), t irq0 n irq31. u tin IRQ c xc nh bng phn mm. Kin
trc Nios II h tr dng ngt lng nhau.
Phn mm c th cho php hoc khng cho php bt c ngun ngt no mt
cch ring l thng qua thanh ghi iu khin ienable. Mi bit trong thanh ghi ny
tng ng vi vic cho php hoc khng cho php mt IRQ. Phn mm cng c
th cho php hoc khng cho php ngt ton cc bng cch s dng bit PIE ca
thanh ghi iu khin status. Mt ngt phn cng c to ra khi v ch khi tt c
cc iu kin sau l ng:
Bit PIE ca thanh ghi trng thi l 1
Mt u vo yu cu ngt, irq<n>, c xc nhn
bit tng ng th n ca thanh ghi ienable l 1
6.1.2.5 D liu v lnh

Kin trc ca Nios II h tr cc bus d liu v lnh ring bit, nh kin trc
Harvard. Bus d liu thng qua cng d liu chnh kt ni vi c b nh v ngoi
vi, trong khi bus lnh thng qua cng lnh chnh ch kt ni vi b nh.
Cu trc Nios II truy xut I/O v b nh theo dng: c hai b nh d liu v
thit b ngoi vi u c nh x vo khng gian a ch ca cng d liu chnh.
Kin trc lu tr ca Nios II theo dng little endian, cc t v na t c lu tr
trong b nh vi bytes cao th lu tr a ch cao.
236

6.1.2.6 B nh m (cache)

Kin trc Nios II h tr b nh m lnh v m d liu. B nh m nm


trn chip nh l mt phn khng th thiu ca nhn x l Nios II. B nh m gip
tng thi gian truy cp b nh cho nhng h thng x l Nios II m s dng b
nh ngoi chip tc chm nh SDRAM.Vic qun l v lin kt b nh m
c iu khin bng phn mm. Tp lnh Nios II cung cp mt s lnh cho vic
qun l b nh m
Vic dng b nh cache l ty chn, ty vo ng dng. Mt nhn x l Nios
II c th bao gm mt, hoc hai, hoc khng c b nh cache no c. Hn na,
kch thc ca b nh cache c th c cu hnh theo ngi s dng. Vic a
b nh cache vo s khng nh hng n chc nng ca chng trnh, nhng nh
hng n tc tm np lnh, c hoc ghi d liu ca b x l.

6.1.2.7 B nh tightly-coupled

B nh tightly-coupled m bo truy cp b nh vi tr thp cho cc ng


dng ch trng hiu nng. So vi b nh cache, b nh tightly-coupled cung cp
cc li ch sau:
Hiu nng ging vi b nh cache
Phn mm c th m bo code hoc d liu no ch trng hiu nng
s c t trong b nh tightly-coupled.
Khng xy ra nhng tnh trng nh ti, v hiu ha hay phc hi li
b nh trong qu trnh chy
V mt vt l, cng b nh tightly-coupled l mt cng chnh ring bit trn
nhn x l Nios II, tng t cng lnh hoc cng d liu chnh. Mt nhn Nios II
237

c th khng c, hoc mt, hoc nhiu b nh tightly-coupled. Kin trc Nios II h


tr b nh tightly-coupled cho c truy cp lnh v truy cp d liu.
B nh tightly-coupled chim khng gian a ch thng thng, ging nh
cc thit b b nh khc c kt ni thng qua c cu kt ni h thng. Dy a
ch dnh cho b nh tightly-coupled (nu c) c xc nh ti thi im pht sinh
h thng.
Phn mm truy cp b nh tightly-coupled thng s dng lnh dng load
v store. T kha cnh ca phn mm, khng thy s khc bit gia truy cp b
nh tightly-coupled vi nhng b nh khc.
Hiu qu s dng ca b nh tightly-coupled: Mt h thng c th s dng
b nh tightly-coupled t c hiu sut ti a khi truy cp vo mt phn c
bit no ca code hoc d liu. V d, cc ng dng lin quan n interrupt c
th t on code x l ngoi l vo b nh tightly-coupled gim thiu tr
khi xy ra interrup. Tng t nh vy, vi cc ng dng lin quan n x l tn
hiu s (DSP) c th t mt b m d liu vo b nh tightly-coupled truy
cp d liu nhanh nht c th.
Nu yu cu v b nh ca ng dng nh gn hon ton vo chip, c
th s dng b nh tightly-coupled dnh ring cho m v d liu. Vi cc ng
dng ln hn phi la chn cc phn a vo tightly-coupled sao cho cn bng
gia hiu sut v chi ph.

6.1.2.8 n v qun l b nh (MMU)

Nios II MMU cung cp nhng chc nng sau:


- nh x a ch o thnh a ch vt l
- Bo v b nh

238

- 32-bit a ch o v a ch vt l, nh x 4 GB khng gian a ch o


vo 4 GBytes b nh vt l.
- 4 Kbyte kch thc trang v khung.
- Di 512 MBytes khng gian a ch vt l c sn cho vic truy cp
trc tip.
Khi khi to b x l Nios II, c th chn a MMU vo hay khng, v vi
mt s thng s c sn c th cho php ti u ha MMU cho h thng khi cn.
Lu : n v qun l b nh MMU v n v bo v b nh MPU loi tr
ln nhau. H thng Nios II hoc l cha MMU, hoc l cha MPU, nhng khng
th cha c hai trong cng mt thit k.

6.1.2.9

n v bo v b nh (MPU)

B x l Nios II cung cp MPU cho h iu hnh v mi trng thi gian


thc bo v b nh nhng khng yu cu qun l b nh o.
Nios II MPU cung cp nhng tnh nng v nhim v sau:
- Bo v b nh
- Ln n 32 vng lnh v 32 vng d liu
- Kch thc vng d liu v vng lnh c th thay i
- ln ca b nh c xc nh bng kch thc ca n hoc gii
hn a ch trn cng.
- Cp quyn c v ghi trong vng d liu
- Cp quyn thc thi trong vng lnh
- Cc vng chng cho nhau
Khi khi to b x l Nios II, c th chn a MMU vo hay khng v vi
mt s thng s c sn c th cho php ti u ha MMU cho h thng khi cn.

239

Lu : n v qun l b nh MMU v n v bo v b nh MPU loi tr


ln nhau. H thng Nios II hoc l cha MMU, hoc l cha MPU, nhng khng
th cha c hai trong cng mt thit k.

6.1.2.10 Khi JTAG Debug

Kin trc NIOS II h tr khi JTAG debug nhm iu khin, theo di b x


l t xa thng qua mt my PC no . Nhng cng c debug dng phn mm
chy trn PC kt ni vi khi JTAG debug ca Nios II cung cp nhng tnh nng
v nhim v sau:
- Ti chng trnh ti b nh
- Khi ng v ngng thc thi chng trnh
- Ci t cc breakpoints v watchpoints
- Phn tch cc thanh ghi v b nh
- Truy vt khi chng trnh thc thi

6.1.3

M hnh lp trnh

Chng ny m t m hnh lp trnh Nios II, bao gm cc tnh nng ca b


x l cp hp ng. hiu bit y cc ni dung ca chng ny i hi
phi c kin thc trc v kin trc my tnh, h iu hnh, qun l b nh v b
nh o, qun l tin trnh, x l ngoi l, v tp lnh,
6.1.3.1 Cc ch hot ng Nios II

Cc ch hot ng kim sot cch thc b x l hot ng, qun l b


nh h thng v truy xut ngoi vi. Kin trc Nios II h tr cc ch hot ng
sau:
- Ch gim st (supervisor mode)
240

- Ch ngi dng (user mode)


Supervisor mode:
Supervisor mode khng hn ch hot ng ca b x l. B x l c th
thc hin bt k hot ng no m kin trc Nios II cung cp. Bt k lnh no cng
c th c thc thi, v bt k hot ng nhp xut u c th c khi to, v bt
k vng nh no u c th truy cp c.
Cc h iu hnh v phn mm h thng khc u chy trong supervisor
mode. Trong cc h thng c MMU, ng dng chy trong user mode v h iu
hnh chy trong supervisor mode nhm kim sot s truy cp ca ng dng vo b
nh v cc thit b ngoi vi. Trong cc h thng c MPU, phn mm h thng kim
s sot ch m ng dng chy trong . Trong h thng Nios II m khng c
MMU hoc MPU, tt c cc m ng dng v m h thng u chy trong
supervisor mode.

User mode:
User mode sn sng ch khi trong thit k ca b x l Nios II c MMU
hoc MPU. User mode thng thng ch h tr cc h iu hnh v cc h iu
hnh u chy cc ng dng user mode. Cc kh nng ca b x l trong user
mode l tp con trong supervisor mode, tc ch mt tp con cc lnh trong tp lnh
ca Nios II c th s dng trong user mode.
H iu hnh quyt nh vng b nh no c th truy cp bi cc ng dng
trong user mode. Vic c gng truy cp vo cc v tr nh m cc ng dng trong
user mode khng c php s gy ra mt ngoi l. Code chy trong user mode s
dng li gi h thng yu cu h iu hnh thc hin cc hot ng I/O, qun l
b nh, hay truy cp n cc chc nng h thng khc trong supervisor mode

241

6.1.3.2 Cc thanh ghi a dng

Kin trc Nios II cung cp 32 thanh ghi a dng 32-bit, t r0 n r31, nh


trong Bng 6.2

Bng 6.2 Cc thanh ghi a dng ca NIOS II

242

Ghi ch Bng 6.2:


(1)

Thanh ghi ny c dnh ring cho JTAG debug module.

6.1.3.3 Cc thanh ghi iu khin

Cc thanh ghi iu khin cho bit trng thi v thay i hnh vi ca b x


l. Cch thc truy cp ca chng khc vi thanh ghi a dng. Cc lnh c bit
rdctl v wrctl l cc lnh duy nht dng c, ghi vo thanh ghi iu khin v
chng ch hot ng c trong ch gim st (supervisor mode).
Lu : Khi ghi ln mt thanh ghi iu khin, tt c cc bit khng c nh
ngha phi mang gi tr 0.
Kin trc Nios II h tr ln n 32 thanh ghi iu khin. Bng 6.3 cho bit
chi tit v cc thanh ghi iu khin.

243

Bng 6.3 Cc bit v tn ca thanh ghi iu khin

Ghi ch cho Bng 6.3:


(1) S dng ch khi c MMU. Nu khng s tr thnh thanh ghi lu tr.
244

(2) S dng ch khi c MPU. Nu khng s tr thnh thanh ghi lu tr.


Mt vi thanh ghi iu khin thng dng
 Thanh ghi status
Gi tr ca thanh ghi status s iu khin trng thi ca b x l NIOS II.
Tt c cc bit trng thi s tr v 0 khi b x l khi ng li. Mt s bit c
dng ring v ch thch hp cho mt s tnh nng ca b x l. Bng 6.4 cho thy
cch b tr ca thanh ghi ny.

Bng 6.4 Cho bit chi tit cc trng c nh ngha trong thanh ghi status

245

Ghi ch:
(1) EH v U cng l bit 1 th khng c php v c th s cho ra kt qu
sai.
 Thanh ghi estatus
Thanh ghi estatus lm nhim v lu gi mt bn sao ca thanh ghi status
trong sut qu trnh x l ngoi l dng non-break. Bng 6.5 cho thy cch b tr
ca thanh ghi estatus.
246

Bng 6.5 Cc trng ca thanh ghi iu khin estatus

Tn cc trng trong estatus ging cc trng trong status ngoi tr vic


thm tin t E.
B x l ngoi l c th kim tra estatus xc nh trng thi trc ngoi
l ca b x l. Khi mt ngoi l c x l xong, lnh eret thc hin lm cho
b x l sao chp ni dung t estatus sang status, qua khi phc gi tr ca
status trc khi ngoi l xy ra.
c thm phn Tin trnh x l ngoi l bit thm chi tit
 Thanh ghi bstatus
Thanh ghi bstatus gi bn sao lu ca thanh ghi status trong qu trnh x l
ngoi l dng break. Bng 6.6 cho thy cch b tr ca bstatus

Bng 6.6 Cc trng ca thanh ghi iu khin bstatus

Tn cc trng trong bstatus ging cc trng trong status ngoi tr vic


thm tin tB.
Khi mt break xut hin, gi tr ca status c sao lu vo bstatus. Bng
cch s dng bstatus, debugger c th phc hi li gi tr trc khi ngt ca status.
Lnh bret thc hin lm cho b x l sao chp gi tr t bstatus vo li status.
 Thanh ghi ienable

247

Thanh ghi ienable dng iu khin cc ngt cng ngoi. Mi bit ca


ienable tng ng vi mt u vo interrupt, t irq0 n irq31. Ni cch khc nu
bit n ca ienable c gi tr 1 th interrupt th n c php, nu gi tr 0 c ngha l
khng c php.
 Thanh ghi ipending
Thanh ghi ipending cho bit tn hiu interrupt no ang tc ng vo b x
l. Ni cch khc, nu bit th n c gi tr 1 th interrupt th n c khng nh
ang tc ng. Lu , thao tc ghi ti thanh ghi ipending khng c tc dng
 Thanh ghi cupid
Thanh ghi cupid nm gi mt hng s dng phn bit cc b x l trong h
thng a x l, hay cn gi l nm gi cc ID ca cc b x l. Gi tr cupid c
xc nh thi im pht sinh h thng v c m bo l mi b x l trong h
thng c mt ID duy nht. Lu , thao tc ghi ti thanh ghi cupid khng c tc
dng.

6.1.3.4 Tin trnh x l ngoi l

Ngoi l l qu trnh chuyn quyn iu khin ra khi lung thc thi bnh
thng ca chng trnh, c to ra bi mt s kin no , bn trong hay bn
ngoi b x l m i hi phi c ch ngay lp tc. X l ngoi l l ng ph
vi mt ngoi l v sau a h thng tr li trng thi trc khi ngoi l xy ra.
Cc ngoi l trong Nios II thuc mt trong cc loi sau:
- Ngoi l khi ng li (Reset exceptions)
- Ngoi l break (Break exceptions)
- Ngoi l ngt (Interrupt exceptions)
- Ngoi l lin quan n lnh (Instruction-related exceptions)

248

Ngoi l khi ng li (Reset exceptions)


Khi mt tn hiu reset b x l c a vo, b x l Nios II thc hin cc
bc sau:
- Xa thanh ghi status thnh 0x0. Vic xo thanh ghi status s v hiu
ha cc interrupt cng. Nu c MMU hoc MPU, xa thanh ghi status
s buc b x l chuyn sang supervisor mode.
- Lm mt hiu lc dng cache lnh tng ng vi vector reset. Vic
ny c thc hin nhm m bo rng lnh np cho code reset n t
vng nh khng cache
- Bt u thc thi b iu khin reset, c cp pht ti vector reset.
Lu ni dung ca nhng vng nh m l khng xc nh sau khi reset.
Do b iu khin reset phi ngay lp tc khi to li vng cache lnh. Tip
theo, hoc l b x l reset hoc l mt hm tip theo no phi tin hnh khi
to li vng cache d liu.
Ngoi l break (Break exceptions)
Ngoi l dng break l qu trnh chuyn quyn iu khin ra khi lung thc
thi bnh thng ca chng trnh cho mc ch debug. Cng c g ri mm c th
ly quyn kim sot ca b vi x l Nios II thng qua khi JTAG debug.
X l break ngha l bng cch s dng cng c g ri bng phn mm ci
t tnh nng g li v chn on, nh cc im ngt (breakpoint) v im nhn
(watchpoint). X l break l mt dng ca x l ngoi l, nhng c ch ca break
th c lp vi qu trnh x l ngoi l thng thng.
B x l ri vo trng thi x l break trong cc iu kin sau y:
- B x l thc thi lnh break m thng c xem nh mt break
mm
- JTAG debug module xc nhn mt ngt cng.
249

Mt break xy ra, b x l phi thc hin cc bc sau :


- Lu tr ni dung thanh ghi status vo thanh ghi bstatus.
- Xa trng status.PIE thnh 0, v hiu ha cc ngt ngoi.
- Ghi a ch lnh theo sau break vo thanh ghi ba (r30).
- Xa trng status.U thnh 0, buc b x l vo ch supervisor
mode khi h thng cha MMU hoc MPU.
- t trng status.EH thnh 1, ch ra b x l ang nm gi ngoi l
khi h thng c cha MMU.
- Chuyn quyn thc thi cho b x l break. a ch ca b x l break
c lu tr trong vector break, c xc nh ti thi im pht sinh
h thng.
Thanh ghi bstatus v cc thanh ghi a dng bt (r25), ba (r30) c
dnh cho debug. Lu l vic code c th s dng c cc thanh ghi ny, nhng
debug c th lm cho cc gi tr trong cc thanh ghi ny b ghi . B x l break
c th s dng bt (r25) gip lu cc thanh ghi thm vo.
Sau khi x l mt break, b x l break gii phng quyn iu khin b x
l tr v lung thc thi ban u bng cch thc hin lnh bret. Lnh bret ny phc
hi li gi tr ca thanh ghi status bng cch sao chp ni dung thanh ghi bstatus v
status v tr v chng trnh thc thi ban u ti a ch c lu trong thanh ghi
ba (r30). Ngoi thanh ghi bt, tt c cc thanh ghi u c m bo tr li gi tr
trc khi break xy ra.
Ngoi l ngt (Interrupt exceptions)
Ti nguyn bn ngoi nh thit b ngoi vi c th to mt interrupt cng
bng cch tc ng n mt trong 32 u vo interrupt ca b x l, tnh t irq0
qua irq31. Mt ngt cng c to ra khi v ch khi c ba iu kin sau l ng:
- Bit PIE ca SR bng mt.
250

- Mt u vo interrupt c tc ng ln 1 (irqn)
- Bit th n tng ng ca thanh ghi ienable bng 1.
Trong thi gian x l ngt cng, b x l xa bit PIE v 0, khng cho php
thm cc interrupt, sau thc hin cc bc khc x l ngt.
Gi tr ca thanh ghi iu khin ipending ch ra interrupt no ang ch gii
quyt. Hnh 3-1 cho thy mi quan h gia ipending, ienable, PIE, v s pht sinh
ca mt interrupt.
Nios II c mt on chng trnh con dng xc nh xem trong s nhng
ngt ang ch gii quyt, ngt no c u tin cao nht, v sau chuyn quyn
iu khin cho on chng trnh x l ngt (cn gi l ISR _ interrupt service
routine).

251

Hnh 6.3 Mch m t phn cng cc thanh ghi phc v ngt


Ngoi l lin quan lnh (Instruction-related exceptions)
Nhng ngoi l lin quan n lnh xy ra sut trong qu trnh thc thi lnh
Nios II. Cc trng hp xy ra ngoi l dng ny:
- Lnh trap: Khi mt chng trnh cp pht lnh trap, n sinh ra mt
trap exception mm. Mt chng trnh pht sinh trap khi chng trnh
yu cu phc v bi h iu hnh. B x l ngoi l tng qut cho h
iu hnh s xc nh nguyn nhn cho trap v phn ng li mt cch
thch hp.
252

- Lnh break: Lnh break c coi l gy ra mt ngoi l break mm


- Lnh cha hin thc (unimplemented): Khi b x l pht mt lnh
hp l m cha c hin thc trong phn cng, mt ngoi l cho
lnh cha c hin thc s pht sinh. B x l ngoi l tng qut s
xc nh lnh no to ra ngoi l. Nu lnh khng c hin thc
trong phn cng, quyn iu khin c chuyn cho mt th tc x l
ngoi l, th tc ny c th chn la m phng lnh bng phn
mm.
- Lnh khng hp l: Lnh khng hp l l cc lnh c trng opcode
hoc opcode m rng khng xc nh. B x l Nios II c th kim
tra bit cc lnh khng hp l v to ra ngoi l khi gp chng. Khi
h thng c cha MMU hoc MPU th vic kim tra cc lnh khng
hp l lun thc hin. Khi h thng khng c MMU hoc MPU, vic
c kim tra cc lnh bt hp l hay khng l ty .
- Lnh dnh ring ch supervisor mode: Khi h thng cha MMU
hoc MPU v b x l ang trong ch user mode (status.U = 1),
vic thc thi lnh dnh ring cho supervisor mode s gy ra mt ngoi
l. Cc lnh dnh ring cho supervisor mode l initd, initi, eret, bret,
rdctl, v wrctl.
- a ch lnh dnh ring ch supervisor mode: Khi h thng cha
MMU v b x l ang trong ch user mode (status.U = 1), vic c
gng truy cp vo mt vng a ch lnh dnh ring cho ch
supervisor mode s gy ra mt ngoi l. Ngoi l ny c hin thc
ch trong b x l Nios II c MMU.
- a ch d liu dnh ring ch supervisor mode: Khi h thng c
cha MMU v b x l ang trong ch user mode (status.U = 1),
253

vic c gng truy cp vo mt vng a ch d liu dnh ring cho


supervisor mode s gy ra mt ngoi l. Cc lnh c th gy ra ngoi
l dng ny tt c cc lnh dng load, dng store v flushda. Ngoi l
ny c hin thc ch trong b x l Nios II c cha MMU.
Ngoi ra cn cc ngoi l khc nh:
- a ch d liu sai v tr
- a ch ch sai v tr
- Li chia
- Vi phm vng MPU
-
Phn trn din t cc loi ngoi l c nh ngha bi kin trc Nios II. Tuy
nhin, c th s c mt s ngoi l khc khng c trong danh sch trn. V th b
x l ngoi l phi cung cp mt c ch x l an ton (nh pht ra mt cnh bo)
trong trng hp n khng th xc nh c nguyn nhn gy ngoi l.

6.1.3.5 Truy xut b nh v ngoi vi

a ch Nios II l 32 bit, cho php truy xut ln n 4 Gb khng gian a ch.


H thng x l core Nios II khng c MMU gii hn a ch n 31 bit hoc thp
hn, c MMU h tr y 32 bit a ch.
Thit b ngoi vi, b nh d liu v b nh chng trnh c a vo trong
cng mt khng gian a ch. a ch c cp cho b nh v thit b ngoi vi
c xc nh ti thi im pht sinh h thng. c hoc vit ti mt a ch m
khng phi l vng c cp pht cho b nh hoc thit b ngoi vi s a ra mt
kt qu khng xc nh.
Bus d liu ca b x l rng 32 bits. Cc lnh c th dng c/ghi d liu
theo byte, na t (16-bit), hoc mt t (32-bit).
254

Kin trc Nios II l little endian.


Kin trc Nios II h tr a ch theo dng thanh ghi+gi tr tc thi.
Nios II cha vng cache lnh v cache d liu. Vic qun l cache c
hin thc trong phn mm bng cch s dng nhng lnh dnh ring cho cache
nh lnh yu cu khi to cache, lm sch cache khi cn thit hay b qua khng
cache,
Nios II cung cp mt vi cch b qua cache nh sau :
Khi khng c MMU, bit th 31 ca a ch c dng iu khin
vic b cache.
Khu MMU hin hnh, cache c iu khin bi MMU.
Mt vi lnh b qua cache nh ldwio v stwio.

6.1.3.6 Tp lnh Nios II

Phn ny gii thiu cc lnh ca Nios II, c phn nhm theo tng dng
hot ng ca chng
6.1.3.6.1 Nhm lnh chuyn d liu

Kin trc Nios II l kin trc load-store. Lnh load (ly d liu) v store (lu
tr d liu) nm gi tt c cc hot ng di chuyn d liu gia cc thanh ghi, b
nh v cc thit b ngoi vi. Bng 6.7 lit k cc lnh dng load v store (32 bit)

255

Bng 6.7 Nhm lnh chuyn d liu

6.1.3.6.2 Nhm lnh s hc v logic

Nhm lnh logic h tr cho cc hot ng: and, or, xor, v nor. Nhm lnh s
hc h tr thao tc: cng, tr, nhn, chia. Tham kho
256

Bng 6.8.

Bng 6.8 Lnh logic v s hc

257

6.1.3.6.3 Nhm cc lnh di chuyn d liu

Nhm lnh ny thc hin cc thao tc chp gi tr ca mt thanh ghi hoc


mt s tc thi ti mt thanh ghi khc. Tham kho Bng 6.9

258

Bng 6.9 Cc lnh di chuyn

6.1.3.6.4 Nhm lnh so snh

Nhm lnh ny thc hin vic so snh hai thanh ghi hoc thanh ghi vi mt
gi tr tc thi; kt qu l 1(nu ng) hoc 0 (nu sai) c ghi ra thanh ghi kt
qu. Tham kho Bng 6.10

259

Bng 6.10 Cc lnh so snh

6.1.3.6.5 Nhm lnh dch v xoay

Nhm lnh ny thc hin cc php ton dch v xoay. S bit xoay hoc
dch c ch r trong mt thanh ghi hoc mt s tc thi. Tham kho Bng 6.11

260

Bng 6.11 Lnh dch v xoay

6.1.3.6.6 Nhm lnh iu khin chng trnh

Kin trc Nios II h tr nhm lnh nhy v gi hm khng iu kin c


lit k trong Bng 6.12

261

Bng 6.12 Nhm lnh nhy v gi hm khng iu kin

Kin trc Nios II h tr nhm lnh nhy c iu kin c lit k trong


Bng 6.13. Nhm lnh ny so snh cc gi tr cha trong thanh ghi v nhy nu kt
qu so snh l ng

262

Bng 6.13 Nhm lnh nhy c iu kin

263

6.1.3.6.7 Nhm cc lnh iu khin khc

Bng 6.14 Nhm lnh iu khin khc

6.1.3.7 Cc kiu d liu

Cc kiu d liu ca Nios II trnh by trong


Bng 6.15
Bng 6.15 Cc kiu d liu Nios II
264

6.1.3.8 Stacks trong Nios II

Kin trc stack trong Nios II pht trin theo hng xung, hai con tr cn
quan tm khi lm vic vi stack l con tr stack (stack pointer) v con tr khung
(frame pointer). Stack pointer ch ti khe (slot) c dng cui cng. Frame
pointer tr n frame pointer c lu gn nh ca stack.
Frame pointer c cung cp h tr cho cng vic debug. Nu khng cn
debug, frame pointer c th b ra khi code. Dng ty chn fomit-frame-pointer
cho trnh bin dch, thanh ghi fp s c xem nh thanh ghi tm.
Trnh bin dch chu trch nhim lu tr nhng thanh ghi m cn c lu
trong mt hm. Nu c nhng thanh ghi nh vy, chng s c lu trong stack, t
265

a ch cao n thp theo th t sau: ra, fp, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12,
r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, gp, v sp. Khng gian
stack khng c cp cho cc thanh ghi m khng c lu. Hnh 6.4 trnh by
mt v d hm a() gi hm b(), v stack c th hin trc li gi v sau dn
nhp ca cu trc khung hin ti. Trong trng hp ny, hm a() gi hm b(), v
stack c th hin trc v ngay sau li gi hm.

Hnh 6.4 Cu trc ca Stack Pointer


6.1.3.9

Chi tit t lnh Nios II

C 3 loi dng t lnh trong Nios II: loi I, loi R, loi J.

266

6.1.3.9.1 T lnh loi I

c tnh ca dng t lnh loi I l gi tr tc thi c nhng trong t lnh.


T lnh dng I cha cc trng:
Trng OP: 6-bit opcode lnh
Trng A v B: 5-bit cha ch s thanh ghi A v B
Trng IMM16: 16-bit d liu tc thi
Trong hu ht trng hp, trng A v IMM16 l u vo ca lnh, v
trng B l thanh ghi cha kt qu. Lnh loi I bao gm nhng php ton s hc
v logic nh addi v andi; php ton r nhnh; cc hot ng np v lu v lnh
qun l cache.
nh dng lnh loi I nh sau:

Hnh 6.5 nh dng t lnh loi I

6.1.3.9.2 T lnh loi R

c tnh ca dng t lnh loi R l tt c nhng i s v kt qu l thanh


ghi. Loi lnh R cha cc trng:
Trng OP: 6-bit opcode
Trng A, B, C: 5-bit ch s ca cc thanh ghi A, B, C
Trng OPX: 11-bit opcode m rng
Trong hu ht trng hp, trng A v B l cc u vo ca lnh, v trng
C l thanh ghi kt qu. Mt vi lnh loi R a vo mt gi tr tc thi trong
trng OPX.

267

Lnh loi R bao gm cc php ton s hc v logic nh add v nor; php


ton so snh nh cmpeq v cmplt; lnh ty chnh; v nhng php ton khc m ch
thao tc trn thanh ghi.
nh dng lnh loi R nh sau:

Hnh 6.6 nh dng t lnh loi R


6.1.3.9.3 T lnh loi J

Lnh loi J cha :


Trng OP: 6-bit opcode
Trng IMMED26: 26-bit d liu tc thi
Lnh loi J ch thao tc trn s tc thi, nh nh call v jmpi, chuyn quyn
thc thi n bt c u trong phm vi 256 MByte
nh dng lnh loi J nh sau:

Hnh 6.7 nh dng t lnh loi J

268

Bng 6.16 M ha trng OP ca cc t lnh

269

Bng 6.17 M ha trng OPX ca cc t lnh loi R

6.1.3.10 Lnh gi

Nhng lnh gi c s dng trong code nh nhng lnh assemply thng


thng. Mi lnh gi c th c tn khc, nhng thc cht l s dng mt lnh
assemply ng lng ngoi tr lnh movie. Movia c hin thc vi hai lnh
tng ng. Lnh gi ch c gi tr cho lp trnh, trong m my, n ch c th
hin bng cc lnh tng ng thc cht ca n.

270

Bng 6.18 Danh sch cc lnh v lnh tng ng

6.1.3.11 Cc Macros

Assembler ca Nios II cung cp cc macro rt trch na-word t nhng


nhn v t nhng gi tr tc thi 32-bit. Nhng macro tr v gi tr c du 16-bit
hoc gi tr khng du 16-bit ty thuc vo ni no chng c s dng. Khi s
271

dng vi mt lnh i hi mt gi tr tc thi c du 16-bit, nhng macro s tr v


mt gi tr t -32768 n 32767. Khi s dng vi mt lnh cn gi tr tc thi
khng du 16-bit, nhng macro ny s tr v mt gi tr t 0 n 65535.

Bng 6.19 Danh sch cc macro hin hnh

272

6.2 Hng dn thc hnh trn vi x l Nios II


6.2.1

Nios II System :

Nios II system l mt users system c thit k trn Cyclone II FPGA bng


mt cng c trn Quartus II, l SOPC Builder. Tt nhin v mt l thuyt th
users c th t to mt system trn FPGA nhng iu s tn thi gian v cng
sc.
Nios II system vi Nios II processor ng vai tr trung tm. V mt ngha
no th Nios II processor ging nh Chip vi iu khin 8951 m chng ta
c hc trong mn Vi x l.
Di y l mt th d v mt Nios II system.

Hnh 6.8 Nios system


Di y l mt Nios II system n gin hn, chng ta cng s dng Nios II
system ny lm th d minh ha cho ton b hng dn ny.
273

Hnh 6.9 Nios system n gin


Nhng khi trong vng mu xanh lin kt vi nhau to nn mt system.
Ta s thit k tng module trn chip FPGA. Phng php thng thng l ta
s thit k tng module dng Verilog hay VHDL hoc schematic, ri lin kt
chng li thnh mt system. Nhng nh ta trnh by, iu ny s tn rt nhiu
thi gian v cng sc, c bit i vi nhng ngi mi hc. Tuy nhin Quartus II
c support cho chng ta mt cng c vi nhng modules c build sn. l
SOPC Builder. Nhim v ca chng ta n gin l chn ra nhng module no cn
thit cho thit k ca mnh lin kt chng li.
6.2.2

M mt project mi

Tng t nh m mt project bnh thng ( c trnh by trong phn cc


phn nn chng ta s khng trnh by li). Gi s ta chn ng dn th mc cha
274

project l : D:\sopc_builder_tutorial ; tn project : lights; tn top-level ca project :


lights (nh khi chng ta to verilog cho top-level th bt buc phi trng tn vi tn
chn y ).

Hnh 6.10 To project


Sau khi to xong project, ta tip tc thc hin cc bc sau
Bc 1.

Chn Tool  SOPC Builder

Bc 2.

Nhp tn system chng ta mun gi , gi s nios_system.

Bc 3.

Chn Verilog ( ta s tm hiu thit k bng Verilog trc ,

VHDL s tng t).

Hnh 6.11 t tn cho Nios system


Bc 4.

Nhn OK

275

Hnh 6.12 Ca s SOPC

Bc 5.

Chn Device Family : Cyclone II

Bc 6.

Trn Tab System Contens, chn Nios II processor.

Bc 7.

Nhn Add

Hnh 6.13 Chn processor

276

Bc 8.

Chn Nios II/e (simplest and economical).

Bc 9.

Nhn Finish

Hnh 6.14 Quay v SOPC Builder

Bc 10.

To mt memory on Chip : Chn Memories and Memory

Controllers  On- Chip  On-Chip Memory ( RAM or ROM )


Bc 11.

Nhn Add

277

Hnh 6.15 Chn On-Chip memory

Bc 12.

Chn Memory Width 32 bits, Memory size 4 Kbytes.

Bc 13.

Nhn Finish

278

Hnh 6.16 Quay v SOPC Builder

Bc 14.

To Input Parallel I/O Interface : Peripherals 

Microcontroller Peripherals  PIO (Parallel I/O) ; Nhn Add

Hnh 6.17 Chn PIO


279

Bc 15.

Chn Width of Port : 8 bits

Bc 16.

Direction : Input ports only

Bc 17.

Nhn Finish

Hnh 6.18 Quay v SOPC Builder

Bc 18.

Tng t to Output Parallel I/O Interface : Peripherals 

Microcontroller Peripherals  PIO (Parallel I/O) ; Nhn Add


Bc 19.

Chn Width of Port : 8 bits

Bc 20.

Direction : Output ports only

Bc 21.

Nhn Finish

Bc 22.

Ta cn phi to mt JTAG UART Interface to giao tip

gia host computer vi Nios II system : Chn Interface Protocols 


Serial  JTAG UART ; Nhn Add
280

Hnh 6.19 Chn JTAG UART

Bc 23.

Nhn Finish.

Hnh 6.20 Quay v SOPC Builder


281

Bc 24.

Ta co th thay i tn ca Module bng cch nhp chut phi

vo Default Module Name v thay i tn chng.


Bc 25.

Chn System  Auto-Assign Base Addresses

Hnh 6.21 Thay i c tnh cho Processor


Mt processor s c tn hiu Reset. Vic reset processor c thc hin bi
vector reset, vector reset l a ch ca memory m processor s tm n thc
hin lnh k tip khi reset xy ra. Tng t cho vic interrupt cng s c vector
exception, vector exception l a ch ca memory m processor s nhy ti khi
mt interrupt xy ra. Hai vectors ny c khai bo nh sau :
Bc 26.

Nhn chut phi ln Module Name cpu, chn Edit.

282

Hnh 6.22 Thay i Exception Vector

Bc 27.

Chn onchip_mem cho c 2 vector : Reset Vector v

Exception Vector. Nhn Finish


Bc 28.

Sau khi chn v khai bo y nhng modules cn thit

cho system ca chng ta, chng ta c th to system : Chn System


Generation Tab

Hnh 6.23 To verilog files cho nios system


283

Bc 29.

Turn-off Simulation Create simulator project files

Bc 30.

Nhn Generate

Bc 31.

Khi mt message Success : System Generation Completed.

Nhn Exit. Nios II system ca chng ta c to.


Bc 32.

Sau khi Nios II system to xong, chng ta m th mc cha

project m lc u chng ta khai bo, chng ta s thy mt s file.v


c to. chnh l nhng module m ta s dng SOPC Builder
to ra vi top-level module l nios_system.v v mt file nios_system.ptf
(dng cho qu trnh download chng trnh assembler ln system trn
FPGA).
Bc 33.

Bc tip theo l chng ta tch hp n trn FPGA dng

QuartusII (tng t nh hng dn trong phn thc hnh mn hc


Verilog).
Bc 34.

To mt file lights.v cha module mang tn lights (tn top-

module ny phi ging vi tn top-module m ta khai bo trong lc


to project).

Hnh 6.24 Top-level module


284

Bc 35.

Add file lights.v cng nh nhng file.v (nios_system) m

c to bi SOPC Builder vo project trn Quartus II (phn ny trnh


by trong phn hng dn thc hnh mn hc Verilog ).
Bc 36.

Sau assign pins cho nhng signals SW[0:7], KEY,

CLOCK_50, LEDG (phn ny trnh by trong phn hng dn thc


hnh mn hc Verilog).
Bc 37.

Compiling design (phn ny trnh by trong phn hng dn

thc hnh mn hc Verilog). File lights_time_limited.sof c to ra.


Bc 38.

Tip theo l programming v configure project ln FPGA.

(phn ny trnh by trong phn hng dn thc hnh mn hc


Verilog) :
Bc 39.

Tools  Programmer

Hnh 6.25 Programmer

Bc 40.

Nhn OK

285

Hnh 6.26 Ca s programmer

Bc 41.

Add File, ch ng dn n file lights_time_limited.sof.

Bc 42.

Nhn Start

Hnh 6.27 Gi ca s ny trong sut qu trnh np FPGA


Bc 43.

Gi Status ny trong sut qu trnh chy Altera Monitor

Program (trnh by di).


Nh vy chng ta thit k xong mt system trn FPGA. System ny c
mt processor l NiosII processor ( tng i ging nh vi iu khin C8951 m
chng ta c hc trong mn Vi iu khin), nhng y ta lm vic trn Vi
x l.
thit k mt ng dng trn system ny ta s s dng Assembler languge
hoc C language.
286

Gi ta s thit k mt ng dng n gin , l dng 8 Switches iu


khin 8 Leds tng ng. Cc bc thc hin:
Bc 1.

To mt lights.s dng ngn ng assembler nh sau :

Hnh 6.28 Chng trnh assemble n gin

Bc 2.

S dng mt phn mm khc ca Altera l Altera Monitor

Program (phi ci t trc software ny) compiling, assembling, v


downloading chng trnh ln Nios system c thit k trn FPGA
trn Kit DE2.
Bc 3.

M phn mm Altera Monitor Program :

287

Hnh 6.29 Ca s Altera Monitor Program

Bc 4.

Chn Configuration  Configure System

Hnh 6.30 Thit lp cu hnh

Bc 5.

Chn Cable : USB-Blaster[USB-0]

Bc 6.

Ch ng dn ca file nios_system.ptf ( c to khi

generate nios system bi SOPC builder).


288

Bc 7.

Nhn OK

Bc 8.

Chn Configuration -> Configure Program

Hnh 6.31 Chn file chng trnh

Bc 9.

Chn Program Type : Assembly (v chng ta ang mun

download mt chng trnh vit bng Assembly language).


Bc 10.

Nhn Add, ch ng dn ti file lights.s (File cha chng

trnh vit bng Assembly language).


Bc 11.

Nhn OK

Bc 12.

Chn Actions  Compile & Load

Bc 13.

Chn Actions  Continue thc thi chng trnh trn Kit

DE2. (chng trnh s c thc thi cho n khi c mt lnh yu cu


processor ngng, chng hn nh breakpoint hay Action  Stop).
Processor s ngng lnh k tip. Khi chng trnh ngng thc thi th tt
c ca s debugging s c update gi tr.

289

Hnh 6.32 Ca s Debug

Bc 14.

iu khin ng m Switch[0:7] v quan st Leds[0:7].

Ta cng c th vit chng trnh bng ngn ng C np cho nios system.


Ta vit mt file.c cha chng trnh c vit bng C :

290

Hnh 6.33 Chng trnh dng C

Cng thc hin tng t nhng bc trn , ch khc o ch khi chn Program
Type thay v chn Assembly thi ta chn C
Quan st kt qu, ta thy n cng cho kt qu tng t .
Chng ta c th dng Altera Monitor Program debug chng trnh:
 Ta c th thc thi chng trnh tng bng vic thc thi tng lnh
mt theo tun t.
 Ta c th dng vic thc thi mt chng trnh ti mt v tr lnh
no bng vic to ra mt breakpoint.
 Ta c th thay i gi tr ca Register.
 Ta c th thay i gi tr ca memory.
 Thc thi chng trnh tng bng vic thc thi tng lnh mt theo
tun t:
Action  Restart
Action  Single step

291

 Dng vic thc thi mt chng trnh ti mt v tr lnh no :


Altera Monitor Program h tr to im breakpoint cho 4 trng hp:
- Khi chng trnh thc thi n mt a ch no m ta mun dng.
- Khi c mt thc hin read data ti mt a ch no m ta mun
dng.
- Khi c mt thc hin write data vo mt a ch no m ta mun
dng.
- Vi x l truy cp vo mt a ch no trong memory m ta mun
dng.
to im breakpoint cho chng trnh, ta chuyn sang ca s Breakpoints
v thc hin cc bc sau

Hnh 6.34 To Breakpoints


Bc 1.

Nhn chut phi vo header no m ta mun to breakpoint,

y ta c 5 header (Instruction breakpoint, Read watchpoint, Write


watchpoint, Access watchpoint, Run until )

292

Bc 2.

Nhn Add v nhp a ch m ta mun thc hin vic dng

chng trnh.
Bc 3.

Ta c th thit lp iu kin cho im breakpoint xy ra

bng cch: double click vo cell bn di ct Condition.

Hnh 6.35 Thit lp iu kin to Breakpoints

Bc 4.

Nhp iu kin cho im breakpoint, nhn OK.

Bc 5.

Sau khi to breakpoint, thc thi li chng trnh. Khi gp ng

iu kin m ta to cho breakpoint thi chng trnh s dng li ti


lnh k tip.
 Thay i gi tr ca Register:
Bc 1.

Chuyn sang ca s Disassembly

Bc 2.

Ta thy c ca s Register (hin th gi tr ca tng Registers

trong processor).

293

Hnh 6.36 Thanh ghi Registers


Pc register: program counter register (cha gi tr a ch ca lnh hin
hnh).
Bc 3.

Thay i gi tr register bng cch double-click vo gi tr ca

register cn thay i v nhp gi tr cn i.


Bc 4.

Thc thi li chng trnh kim tra xem chng trnh c thc

thi theo ng gi tr thay i trong register khng.


 Thay i gi tr ca memory (cha data v m my ca chng
trnh)
Bc 1.

Chuyn sang ca s Memory

294

Hnh 6.37 Vng nh ca On-Chip memory

Bc 2.

Double-click vo gi tr ca a ch no cn thay i thay

i.

Hnh 6.38 Thay i ni dung nh

Bc 3.

Nhp gi tr cn thay i.

Bc 4.

Thc thi li chng trnh v quan st xem chng trnh c thc

thi ng vi gi tr c thay i trong memory hay khng.

295

6.3 Ni dung thc hnh mn Kin trc my tnh nng cao


6.3.1

Bi thc hnh s 1 Thit k v s dng mt h thng my tnh n gin

Mc ch:
Xy dng mt h thng vi x l n gin
Lm quen cch s dng cng c debug Altera Monitor Program.
6.3.1.1 Phn 1

Dng SOPC Builder to mt Nios system nh hnh di :

Hnh 6.39 SOPC Builder


Cc bc thc hin:
Bc 1.

M mt project QuartusII c tn : nios_system_lab1

Bc 2.

Chn target chip : Cyclone II EP2C35F672C6

Bc 3.

Dng SOPC Builder to mt Nios system c tn nios_sytem,

c cha nhng module sau :


 Nios II/e processor with JTAG Debug Module Level 1.
296

 On-Chip Memory RAM mode vi dung lng 32 Kbytes, mi


byte 32 bits.
Bc 4.

Generate system.

Bc 5.

To mt top design.v (verilog) gi ti nios_system.

Bc 6.

Gn pins cho top design.v (verilog). (Tn module phi ging

tn module defined khi to project).


 clk PIN_N2 ( 50 MHz clock)
 reset_n PIN_G26.
Bc 7.

Compile project

Bc 8.

Program

configure

nios

system

ln

Cyclone

II

EP2C35F672C6 trn FPGA.


Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 7 nh.
Sau khi ta to c mt system (c processor), ng dng system ny
th ta phi vit mt chng trnh thc thi bng Assemble language hoc C
language.  Part II.
6.3.1.2 Phn 2

Vit v kim tra mt chng trnh ng dng trn h thng NiosII c


to phn 1.
Cc bc thc hin:
Bc 1.

Vit mt chng trnh bng Assemble nh sau :

.include "nios_macros.s"
.text
.equ TEST_NUM, 0x90abcdef
297

.global _start
_start:
movia r7, TEST_NUM
mov r4, r7
STRING_COUNTER:
mov r2, r0
STRING_COUNTER_LOOP:
beq r4, r0, END_STRING_COUNTER
srli r5, r4, 1
and r4, r4, r5
addi r2, r2, 1
br STRING_COUNTER_LOOP
END_STRING_COUNTER:
mov r16, r2
END:
br END
.end
Bc 2.

Nu ngha v gii thut ca chng trnh trn.

Bc 3.

Vit m my (machine instruction) cho nhng lnh trn.

Bc 4.

M Altera Monitor Program software.

Bc 5.

Configure nios system v chng trnh Assemble trn vo

Altera Monitor Program software.


Bc 6.

Compile v load data.

Bc 7.

Cho thc thi tng bc . Quan st v ghi li s thay i gi tr

ca register pc, zero, r2, r4, r5, r7, r16 qua tng bc thc thi.
Bc 8.

Gii thch hin tng thay i .


298

Bc 9.

To breakpoint cho chng trnh vi iu kin sau :

- Instruction breakpoint address : 801c (a ch cha lnh : addi r2, r2,


0x1) v gn condition : r2 == 3
- Thc thi li chng trnh. (Nh restart li trc khi continue ).
Quan st v ghi li v gii thch s thay i gi tr ca register pc,
zero, r2, r4, r5, r7, r16 khi breakpoint xy ra.
Bc 10.

Thay i gi tr register :

- Pc register : 8008 (a ch cha lnh : add r4, r7, zero ).


- R7 = abcdef90
- Thc thi li tng bc chng trnh. (Khng restart lai). Quan st
v ghi li v gii thch s thay i gi tr ca register pc, zero, r2, r4,
r5, r7, r16 qua tng bc thc thi.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
c v thc hin cc bc t 1 n 3 nh.
Trnh by cc yu cu cn li trong bi bo co.

6.3.1.3 Phn 3

Tm hiu v s thay i gi tr trong onchip memory.


Cc bc thc hin
Bc 1.

Reload li chng trnh (Action Load )

Bc 2.

Thc thi li chng trnh (Action  Continue).

Bc 3.

Dng thc thi chng trnh ti cui chng trnh (Action 

Stop).
Bc 4.

Vit m my cho hai lnh sau:


299

- and r3, r7, r16


- sra r7, r7, r3
Bc 5.

Thay i gi tr trong memory ti a ch 8000 (a ch cha

lnh : orhi r7, zero, 0x90ab) v 8004 (a ch cha lnh : ori r7, r7,
0xcdef) bi hai gi tr m my trn.
Bc 6.

Thay i gi tr ca pc register thnh 8000

Bc 7.

Chy thc thi tng bc. (Khng restart li chng trnh).

Quan st v ghi li v gii thch s thay i gi tr ca register pc, zero,


r2, r4, r5, r7, r16 qua tng bc thc thi.
Bc 8.

Lp li cc bc trn cho hai lnh sau :

- srl r7, r7, r3.


- sra r7, r7, r3
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
Vit m my cho cc lnh trn nh.

6.3.1.4 Phn 4

Vit chng trnh assemble trn di dng mt chng trnh con


(subrountine). V chng trnh con ny s c gi (call) bi chng trnh chnh.
(Chun b trc nh)
Chng trnh con s dng r4 nhn input data t chng trnh
chnh.
Chng trnh con s dng r2 lm gi tr tr v.

300

6.3.2

Bi thc hnh s 2 iu khin nhp xut d liu t Vi x l

Mc ch:
Tm hiu cch to Processor vi kh nng Input/Output v cch s dng
nhng SWs/KEYs/LEDs nhp xut d liu vi Processor.
6.3.2.1 Phn 1

To Nios System bao gm Nios II/s prcessor, onchip_memory v 3 PIOs


dng cho vic nhp v xut d liu.
Tng bc thc hin:
Bc 1.

To

mt

project

Quartus

mi,

tn:

/lab2/nios_system_lab2
Bc 2.

M SOPC Builder to mt Nios System vi tn nios_system

theo yu cu:
 Nios II/s processor vi JTAG Debug Module Level 1, la chn
nhng option sau:
 Embedded Multipliers for Hardware Multiply
 Hardware Divide
 On-chip memory RAM mode v size l 32 Kbytes
 Mt PIO input 8 bits (t tn cho module ny l : new_number,
tng ng vi SW [7:0])
 Mt PIO output 8 bits (t tn cho module ny l : green_LEDs,
tng ng vi LEDG [7:0])
 Mt PIO output 16 bits (t tn cho module ny l : red_LEDs,
tng ng vi LEDR [15:0])

301

Ch :
SOPC Builder s t ng t tn 3 PIO va to ra l pio_0, pio_1, pio_2. Ta
nn i tn cho d hiu v gn vi ngha ca chng, nh new_number,
green_LEDs v red_LEDs.
Bc 3.

To mt top module cho nios_system_lab2.v cho system va

to.(Nh t tn pin c th s dng file DE2_pin_assignments cho


bc assign pin).
nios_system NiosII (CLOCK_50, KEY[0], LEDG, SW, LEDR);
Bc 4.

Compile system to ra file nios_system_lab2.sof v

nios_system_lab2.ptf
Bc 5.

Np xung FPGA

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Yu cu sinh vin chun b v thc hin cc bc 1 v 2 nh trn
lp c nhiu thi gian nghin cu trn Kit DE2. (nn t tn project
v tn nios system v tn module theo quy c trn thng nht).
Tm hiu v tr li cc cu hi sau :
 V symbol cho 4 module : RAMv 3 PIOs. (nu ngha ca
tng pin trong module).
 V s khi v phng thc hot ng ca Nios system va
to trn.

6.3.2.2 Phn 2

302

Vit chng trnh cng tch ly mt s 8 bits c nhp vo bng 8 Switchs


trn DE2. Dng 8 n LEDG biu din s tng ng vi s trn SW nhp vo,
dng 16 LEDR biu din kt qu tng tnh c. Chng trnh nh sau:

Hnh 6.40 Based address ca cc components

.include "nios_macros.s"
.equ

NEW_NUMBER, 0x11000

.equ

GREEN_LEDS,

0x11010

.equ

RED_LEDS ,

0x11020

.text

.global _start
_start:
add

r17, r0, r0

movia r8,

NEW_NUMBER

movia r9,

GREEN_LEDS

movia r10, RED_LEDS


MAIN_LOOP:
ldwio

r16, 0(r8)

stwio

r16, 0(r9)

add

r17, r17, r16

stwio

r17, 0(r10)
303

br

MAIN_LOOP

.end
Bc 1.

Dng Altera Monitor configure, compile v load chng

trnh trn cho Nios system m c to trn FPFA trong phn 1.

Bc 2.

Thay i gi tr ca SW[0] ln 1 (SW[7:1] vn gi 0) , cho

thc thi tng bc. Quan st v ghi li hin tng trn LEDG[7:0] v
LEDR[15:0]. Cho chng trnh thc thi n khi gi tr ca LEDR bng 5
th bt tip SW[1] ln 1 (khng restart li chng trnh), tip tc cho
thc thi tng bc n khi gi tr LEDR bng 14 th dng. Quan st v
ghi li hin tng trn LEDG[7:0] v LEDR[15:0]. Gii thch hin tng.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Nu ngha tng instruction ca chng trnh trn.
Nu ngha ca chng trnh trn.
Nu gii thut ca chng trnh trn.

6.3.2.3 Phn 3

Mc ch ca phn ny l to mt c hiu bo cho nios processor bit khi


c s thay i gi tr ca input. Khi c ny khng c bt ln th d ta c thay i
gi tr ca input ( SW[7:0]), gi tr ny cng s khng tc ng vo chng trnh,
gi tr ouput s khng thay i. Chi khi no c ny c bt th gi tr input dng
trong vic thc thi tnh ton ca chng trnh mi c update v ouput ca
304

chng trnh s tip tc c cng vi input va c update. V gi tr output s


c hin th va trn LEDR va trn 7-segments LEDs.
thc hin c mc ch ny ta cn phi to mt c bo hiu cho Nios
system. Cc bc thc hin nh sau :

Bc 1.

Thot khi Altera Monitor Program. Quay v SOPC Builder

(Bc 2, phn 1), thm vo h thng mt component input I/O


Bc 2.

Chn Tab : System Contents  Peripherals Microcontroller

Peripherals  PIO ( Parallel I/O).


Bc 3.

Click Add.

Hnh 6.41 Thit lp thng s cho PIO

Bc 4.

Chn Width : 1bits

Bc 5.

Chn : Input ports only

Bc 6.

Chuyn sang Tab : Input Options

305

Hnh 6.42 Thit lp thng s ng b cho Input Port

Bc 7.

Chn : Synchronously capture -> Falling Edge

Bc 8.

Finish

Hnh 6.43 i thng s trn ca s SOPC Builder

Bc 9.

i tn module thnh flag

Bc 10.

Connect flag

Bc 11.

Chn clk

Bc 12.

Re-generate nios system.

Bc 13.

Quay v QuartusII

Bc 14.

To li mt top module cho nios_system_lab2.v nh sau

module nios_system_lab2 (
// Inputs
306

CLOCK_50,
KEY,
SW,
// Outputs
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3
);

// Inputs
input

CLOCK_50;

input

[3:0] KEY;

input

[17:0]

SW;

output

[17:0]

LEDR;

output

[8:0] LEDG;

output

[6:0] HEX0;

output

[6:0] HEX1;

output

[6:0] HEX2;

output

[6:0] HEX3;

// Outputs

******************************************************
*
307

wire

[15:0]

SUM;

// Output Assignments
assign LEDR[15:0] = SUM;

******************************************************
*
nios_system the_nios_system (
// Inputs
.clk

(CLOCK_50),

.reset_n

(KEY[0]),

.in_port_to_the_new_number
.in_port_to_the_flag

(SW[7:0]),
(KEY[1]),

// Outputs
.out_port_from_the_green_LEDs

(LEDG[7:0]),

.out_port_from_the_red_LEDs

(SUM)

);

Hexadecimal_To_Seven_Segment Digit0 (
// Inputs
.hex_number

(SUM[3:0]),

// Outputs
.seven_seg_display(HEX0)
);
Hexadecimal_To_Seven_Segment Digit1 (
// Inputs
308

.hex_number

(SUM[7:4]),

// Outputs
.seven_seg_display(HEX1)
);
Hexadecimal_To_Seven_Segment Digit2 (
// Inputs
.hex_number

(SUM[11:8]),

// Outputs
.seven_seg_display(HEX2)
);

Hexadecimal_To_Seven_Segment Digit3 (
// Inputs
.hex_number

(SUM[15:12]),

// Outputs
.seven_seg_display(HEX3)
);
endmodule

******* Module:

Hexadecimal_To_Seven_Segment

module Hexadecimal_To_Seven_Segment (
// Inputs
hex_number,
// Outputs
seven_seg_display
);
309

// Inputs
input

[3:0] hex_number;

// Outputs
output

[6:0] seven_seg_display;

assign seven_seg_display =
({7{(hex_number == 4'h0)}} & 7'b1000000) |
({7{(hex_number == 4'h1)}} & 7'b1111001) |
({7{(hex_number == 4'h2)}} & 7'b0100100) |
({7{(hex_number == 4'h3)}} & 7'b0110000) |
({7{(hex_number == 4'h4)}} & 7'b0011001) |
({7{(hex_number == 4'h5)}} & 7'b0010010) |
({7{(hex_number == 4'h6)}} & 7'b0000010) |
({7{(hex_number == 4'h7)}} & 7'b1111000) |
({7{(hex_number == 4'h8)}} & 7'b0000000) |
({7{(hex_number == 4'h9)}} & 7'b0010000) |
({7{(hex_number == 4'hA)}} & 7'b0001000) |
({7{(hex_number == 4'hB)}} & 7'b0000011) |
({7{(hex_number == 4'hC)}} & 7'b1000110) |
({7{(hex_number == 4'hD)}} & 7'b0100001) |
({7{(hex_number == 4'hE)}} & 7'b0000110) |
({7{(hex_number == 4'hF)}} & 7'b0001110);

endmodule

310

Bc 15.

Add li tt c cc files.v (nios system va c to li) cng

vi top module cho nios_system_lab2.v trn trc khi re-compile.


Bc 16.

Compile system to ra file nios_system_lab2.sof v

nios_system_lab2.ptf
Bc 17.

Np xung FPGA

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Yu cu sinh vin chun b v thc hin cc bc 1 v 2 nh trn
lp c nhiu thi gian nghin cu trn Kit DE2. (nn t tn project
v tn nios system v tn module theo quy c trn thng nht).
Tm hiu v tr li cc cu hi sau :
 Gii thch ngha ca module nios_system_lab2.v trn.

6.3.2.4 Phn 4

Vit chng trnh cng tch ly mt s 8 bits c nhp vo bng 8 Switchs


trn DE2. Dng 8 n LEDG biu din s tng ng vi s trn SW nhp vo,
dng 16 LEDR v 4 LED 7-segments biu din kt qu tng tnh c. Chng
trnh nh sau:

Hnh 6.44 Mapping gia Based address trn SOPC vi address trong program

.include "nios_macros.s"
311

.equ NEW_NUMBER,

0x11000

.equ GREEN_LEDS,

0x11010

.equ RED_LEDS,

0x11020

.equ STATUS_FLAG,

0x11030

.text

.global _start
_start:
add

r17, r0, r0

movia r8, NEW_NUMBER


movia r9, GREEN_LEDS
movia r10, RED_LEDS
movia r11, STATUS_FLAG

MAIN_LOOP:
ldwio r16, 0(r8)
stwio r16, 0(r9)
ldwio r18, 12(r11)
beq

r18, r0, MAIN_LOOP

stwio r0, 12(r11)


add

r17, r17, r16

stwio r17, 0(r10)


br

MAIN_LOOP

.end

312

Bc 1.

Dng Altera Monitor configure, compile v load chng

trnh trn cho Nios system m c to trong phn 3 ln FPFA .


Bc 2.

Thay i gi tr ca SW[0] ln 1 (SW[7:1] vn gi 0) , cho

thc thi tng bc. Quan st v ghi li hin tng trn LEDG [7:0] v
LEDR[15:0] v 7 segment LEDs.
Bc 3.

Nhn KEY[1], sau tip tc cho thc thi tng bc, quan st

v ghi li hin tng trn LEDG[7:0] v LEDR[15:0] v 7 segment


LEDs.
Bc 4.

Thay i gi tr SW[1] ln 1 (vn gi SW[0] = 1 ). sau

tip tc cho thc thi tng bc, quan st v ghi li hin tng trn
LEDG[7:0] v LEDR[15:0] v 7 segment LEDs.
Bc 5.

Nhn KEY[1], sau tip tc cho thc thi tng bc, quan st

v ghi li hin tng trn LEDG[7:0] v LEDR[15:0] v 7 segment


LEDs.
Bc 6.

Nhn KEY[1], sau tip tc cho thc thi tng bc, quan st

v ghi li hin tng trn LEDG[7:0] v LEDR[15:0] v 7 segment


LEDs.

6.3.3

Bi thc hnh s 3 Tm hiu cch thc hot ng v s dng Subroutine v Stack


ca Vi x l NiosII

Mc ch:

313

Tm hiu v cch to subroutines v subrountine linkage cho Nios system v


nhng cch thc truyn param v ngha ca mt s thanh ghi nh stack pointer
(sp), ra.
6.3.3.1 Phn 1

To Nios System bao gm Nios II/s prcessor, onchip_memory v mt JTAG


UART module s dng tng tc vi host computer.
Tng bc thc hin:
Bc 1.

To

mt

project

Quartus

mi,

tn:

/lab3/nios_system_lab3
Bc 2.

M SOPC Builder to mt Nios System vi tn nios_system

theo yu cu:
 Nios II/s processor vi JTAG Debug Module Level 1.
 On-chip memory RAM mode v size l 32 Kbytes.
Bc 3.

To mt top module cho nios_system_lab3.v cho system va

to v gi tt c cc module.v ca nios_system c to ra bi
SOPC_Builder.
nios_system NiosII (CLK, RESET);
Bc 4.

Assign pin :
 CLK PIN_N2
 RESET PIN_G26.

Bc 5.

Compile system to ra file nios_system_lab3.sof v

nios_system_lab3.ptf

Bc 6.

Np xung FPGA

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
314

Yu cu sinh vin chun b v thc hin cc bc 1 v 2 nh trn


lp c nhiu thi gian nghin cu trn Kit DE2. (nn t tn project
v tn nios system v tn module theo quy c trn thng nht).
Tm hiu v tr li cc cu hi sau :
 V s khi v phng thc hot ng ca Nios system va
to trn.

6.3.3.2 Phn 2

Cho mt list nhng s dng (cha trong mt file, nhng s dng c


cch nhau bi du phy(,) , s u tin cha s nhng s dng trong file, khng
k chnh n) . Nhng s ny s c a vo vng nh trong memory on-chip.
Vit chng trnh Assemble dng sort nhng s dng (khng k s u tin)
theo chiu tng dn, nhng gi tr sau khi sort s store li trong vng nh m
cha trc .
Chng trnh tham kho:

.include "nios_macros.s"
.text
.global _start
315

_start:
movia r8, SIZE
movia r9, LIST
BEGIN_SORT:
ldwio r20, 0(r8)
RESTART_SORT:
mov r18, r0
movi r19, 1
mov r10, r9
SORT_LOOP:
ldwio r16, 0(r10)
ldwio r17, 4(r10)
blt

r16, r17, SKIP_SWAP

SWAP:
stwio r17, 0(r10)
stwio r16, 4(r10)
movi r18, 1
SKIP_SWAP:
addi r19, r19, 1
addi r10, r10, 4
bne

r19, r20, SORT_LOOP

bne

r18, r0, RESTART_SORT

br

END

END:

.org 0x01000

SIZE = 0x01000 + 0x08000 = 0x09000

LIST_FILE:

LIST= 0x09004, 0x09008, 0x0900C,


 Khi ghi gi tr trong file cha nhng
316

s cn sort vo trong memory on-chip


th phi chn a ch bt u ghi l
0x09000

SIZE:
.word 0
LIST:
.end

Hnh 6.45 Based address


Bc 1.

Dng Altera Monitor configure, compile v load chng

trnh trn cho Nios system m c to trong Phn 1 ln FPFA.


Bc 2.

Load

file

cha

gi

tr

cn

sort,

ni

dung

file:

8,23,5,3,8,17,4,20,33 (phn t u tin 8 ch s phn t cn sort. Load


file nh sau:
Bc 3.

Chn Tab memory trn Altera Monitor Program, nhn chut

phi:

Hnh 6.46 Load ni dung cho b nh


317

Bc 4.

Chn Load file into memory

Hnh 6.47 Ni dung c load vo b nh

Bc 5.

Select file : nhp ng dn ca file cha data.

Bc 6.

V trong file data, nhng s c ngn cch bi du phy(,) 

Dilimiter character : ,
Bc 7.

V nhng s ny s c lu trong memory di dng s nh

phn 32 bits, nn mt s s cn 4 bytes lu tr  Value size (bytes):


4
Nh ta cp trn s u tin s c lu ti nh 0x9000.
Bc 8.

Cho thc thi (Continue).

Bc 9.

Stop thc thi, quan st gi tr c sort trong memory. Nhn

xt v gii thch hin tng.


Bc 10.

Cho thc thi tng bc. Quan st v rt ra gii thut ca

chng trnh.
Note : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Nu ngha tng instruction ca chng trnh trn.
318

Nu gii thut ca chng trnh trn.

6.3.3.3 Phn 3

Kho st cch to mt sub-rountine cho chng trnh trn assemble, cng


nh ngha ca nhng thanh ghi stack pointer (sp), frame pointer (fp).
Cng ging nh yu cu trong phn Phn 2, vit mt chng trnh Assemble
sort data theo chiu tng dn. Tuy nhin trong chng trnh ny ta s dng mt
subrountine SORT thc hin vic sort data. Trong chng trnh chnh ta s dng
thanh ghi r2 cha s phn t cn sort, thanh ghi r3 cha a ch ca phn t
u tin. Hai thanh ghi ny s c dng truyn data n subroutine. Trong
subroutine chng ta s s dng mt s thanh ghi, ni dung ca thanh ghi trc khi
s dng cho subroutine phi c lu d li, sau khi subrountine thc hin xong
thi gi tr nhng thanh ghi trn phi c tr v gi tr trc khi n c s dng
trong subroutine.
Chng trnh tham kho:

.include "nios_macros.s"
.equ STACK,

0xa000

.text
/* Main Program */
.global _start
_start:
movia

sp, STACK

mov

fp, sp

movia

r8, SIZE
319

movia

r9, LIST

ldwio

r2, 0(r8)

mov

r3, r9

call

SORT

br

END

END:

/* SORT - Subroutine */
SORT:
subi

sp, sp, 28

stw

ra, 0(sp)

stw

fp, 4(sp)

stw

r8, 8(sp)

stw

r16, 12(sp)

stw

r17, 16(sp)

stw

r18, 20(sp)

stw

r19, 24(sp)

addi

fp, sp, 28

BEGIN_SORT:
RESTART_SORT:
mov

r18, r0

movi

r19, 1

mov

r8, r3

SORT_LOOP:
ldwio

r16, 0(r8)
320

ldwio

r17, 4(r8)

blt

r16, r17, SKIP_SWAP

stwio

r17, 0(r8)

stwio

r16, 4(r8)

movi

r18, 1

SWAP:

SKIP_SWAP:
addi

r19, r19, 1

addi

r8, r8, 4

bne

r19, r2, SORT_LOOP

bne

r18, r0, RESTART_SORT

END_SORT:
ldw

ra, 0(sp)

ldw

fp, 4(sp)

ldw

r8, 8(sp)

ldw

r16, 12(sp)

ldw

r17, 16(sp)

ldw

r18, 20(sp)

ldw

r19, 24(sp)

addi

sp, sp, 28

ret

.org 0x01000
321

LIST_FILE:
SIZE:
.word 0
LIST:
.end
Bc 1.

Dng Altera Monitor configure, compile v load chng

trnh trn cho Nios system m c to trong Phn 1 ln FPFA


Bc 2.

Load file cha gi tr cn sort : (Ging Phn 2)

Bc 3.

Cho thc thi (Continue).

Bc 4.

Stop thc thi, quan st gi tr c sort trong memory. Nhn

xt v gii thch hin tng.


Bc 5.

Quan st gi tr trong vng stack pointer v nhn xt.

Bc 6.

Cho thc thi tng bc. Quan st v rt ra gii thut ca

chng trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Nu cu trc ca mt subroutine cng nh cch gi subroutine t
chng trnh chnh (C th tham kho t NiosII processor Reference
Handbook).
Nu ngha ca stack, stack pointer register, frame pointer register
(Tham kho NiosII processor Reference Handbook).
Nu ngha tng instruction ca chng trnh trn.
Nu gii thut ca chng trnh trn.

6.3.3.4 Phn 4

322

Sa li chng trnh trong phn 3, thay v gi tr s phn t v gi tr a ch


ca phn t u tin c truyn vo subroutine t chng trnh chnh thng qua
register r2, r3. Ta s sa li ta s khng dng r2, r3 m ta s s dng stack
truyn data t chng trnh chnh n subroutine.

Bc 1.

Sinh vin chun b trc nh phn chng trnh.

Bc 2.

Dng Altera Monitor configure, compile v load chng

trnh trn cho Nios system m c to trong Phn 1 ln FPFA .


Bc 3.

Thc thi tng t cc bc ( 3 7) nh trong Phn 3.

Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c


bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Chun b bc 1 nh.
6.3.3.5 Phn 5

Kho st chc nng ca thanh ghi ra.


Vit mt chng trnh tnh giai tha ca mt s bt k :
 n! = n(n-1)(n-2).x 2 x 1 ; trong chng trnh chnh s gi n
mt subroutine, trong subroutine ny s gi n subroutine khc
(mc ch kho st chc nng ca thanh ghi ra).
 Dng SW[2:0] nhp gi tr n.
 Dng LED 7-Segment (HEX3  HEX0) hin th kt qu n!
Cc bc thc hin:
Bc 1.

To Nios system nh sau:

323

Hnh 6.48 Nios System

Bc 2.

Da vo phn 3 ca bi thc hnh 2, to mt module top-level

cho nios system trn c th nhp s vo bng SW[2:0] v xut s va


nhp vo ra LEDG[2:0], v xut kt qu ra LED 7 segments (HEX3 
HEX0]).

Chng trnh tham kho


.include "nios_macros.s"
.equ INPUT_NUM,

0x11000

.equ OUTPUT_NUM,

0x11010

.equ GREEN_LEDS,

0x11020

.equ STACK,

0xa000

.text
/* Main Program */
.global _start
_start:
add

r4, r0, r0

movia r10, INPUT_NUM


movia r11, OUTPUT_NUM
324

movia r16, GREEN_LEDS


ldwio r2, 0(r10)
stwio r2, 0(r16)
movia sp, STACK
mov

fp, sp

subi sp, sp, 4


stw
call

r2, 0(sp)
FACTOR

END:
br

END

/* FACTOR - Subroutine */
FACTOR:
subi sp, sp, 12
stw

ra, 0(sp)

stw

fp, 4(sp)

stw

r17, 8(sp)

addi fp, sp, 12


ldw

r17, 0(fp)

bne

r17, r0, NON_ZERO

movi r4, 1
br

END_FACTOR

NON_ZERO:
subi r17, r17, 1
subi sp, sp, 4
stw
call

r17, 0(sp)
FACTOR
325

addi sp, sp, 4


addi r17, r17, 1
mul

r4, r4, r17

stwio r4, 0(r11)


END_FACTOR:
ldw

ra, 0(sp)

ldw

fp, 4(sp)

ldw

r17, 8(sp)

addi sp, sp, 12


ret
.end
Bc 3.

Dng Altera Monitor configure, compile v load chng

trnh trn cho Nios system m c to trn FPFA (bc 2, Part5).


Bc 4.

Dng SW[2:0] nhp mt s cn tnh giai tha. Thc thi

(Continue) kim tra kt qu trn LED 7 Segment (HEX3  HEX0).


Bc 5.

Chy thc thi tng bc, quan st v gii thch gii thut

chng trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau : (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Chun b bc 2 nh.
Tm hiu gii thut chng trnh assemble trn.

326

6.3.4

Bi thc hnh s 4 Tm hiu cch thc hot ng v s dng Polling v Interrupt


ca Vi x l NiosII

Mc ch:
Tm hiu cch gi v nhn data ti/t thit b xut nhp.
C 2 phng thc c s dng bit trng thi data:
Pooling: Processor truy xut nhng thit b lin tc xem trng thi
ca data.
327

Interrupts: Khi nhng thit b c th nhn data hoc data sn sng


dng, chng s t interrupt ti processor.
Mt phng php thng thng chuyn data gia processor v thit b
xut nhp l Universal Asynchronous Receiver Transmitter (UART). Mt UART
interface (circuit) c t gia processor v thit b xut nhp. Ti 1 thi im, n
c th nhn hoc gi data l k t 8-bit. Vic chuyn d liu gia UART v
processor c thc hin song song. Tuy nhin, vic chuyn d liu gia UART
v thit b xut nhp c thc hin tun t tng bit.
Altera SOPC Builder c th hin thc 1 interface ca dng UART cho Nios
II system, c gi l JTAG UART. JTAG UART interface dng kt ni gia
Nios II processor v host computer.

Hnh 6.49 S khi ca JTAG UART

Xem chng 5 ca Altera Embedded Peripherals Handbook hiu r chc


nng ca thanh ghi Data, thanh ghi Control, Write FIFO, Read FIFO.

328

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Tm hiu thanh ghi Data, Control.
Tm hiu Write FIFO, Read FIFO

6.3.4.1 Phn 1

S dng SOPC Builder to 1 system gm Nios II/e processor, mt


JTAG UART, mt On-chip memory v mt Interval Timer.
Tng bc thc hin:
Bc 1.

To

mt

project

Quartus

mi,

tn:

./lab4/nios_system_lab4
Bc 2.

M SOPC Builder to mt Nios System vi tn

nios_system theo yu cu:


 Nios II/e processor vi JTAG Debug Module Level 1
 On-chip memory RAM vi size l 32 Kbytes.
 JTAG UART (s dng default setting): Interface Protocols 
Serial  JTAG UART; Nhn Add

329

Hnh 6.50 Chn v thit lp thng s cho JTAG UART


 Interval Time: Peripherals  Microcontroller Peripherals 
Interval Timer; Nhn Add
Khi add Interval Time cn ch nhng ty chn sau:
 Ti Hardware Options, Preset Configurations, chn Simple periodic
interrupt
 Ti Timeout Period, thit lp Fixed Period vi 500 msec

330

Hnh 6.51 Chn v thit lp thng s cho timer

Lu li nh hnh sau:

Edit
thnh 1

Error

Hnh 6.52 Chn interrupt request

Bc 3.

Generate nios_system.
331

Bc 4.

To mt top module cho nios_system_lab4.v cho system va

to
Bc 5.

Assign pin
 CLK PIN_N2
 RESET PIN_G26.

Bc 6.

Compile system to ra file nios_system_lab4.sof v

nios_system_lab4.ptf
Bc 7.

Np xung FPGA

Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c


bi chun b khng c vo lp lm th nghim Tnh vng bui ).
Yu cu sinh vin chun b v thc hin cc bc 1 v 2 nh trn
lp c nhiu thi gian nghin cu trn Kit DE2. ( nn t tn project
v tn nios system v tn module theo quy c trn thng nht).
Tm hiu v tr li cc cu hi sau :
 V s khi v phng thc hot ng ca Nios system va
to trn.

6.3.4.2 Phn 2

JTAG UART c th gi k t ASCII ti terminal window ca Altera


Debug Client. Khi vng WSPACE trong thanh ghi Control ca JTAG UART c
gi tr khc 0, JTAG UART chp nhn 1 k t mi c vit ra Altera Debug
Client. Nh vy, vit 1 k t ra Debug Client, ta phi c lin tc (Polling)
thanh ghi Control cho ti khi no vng WSPACE khc 0.

332

Hnh 6.53 JTAG UART Core Register Map

Hnh 6.54 Data Register Bits

Hnh 6.55 Control Register Bits

Cc bc thc hin
Bc 1.

S dng Nios II assembly, vit chng trnh s dng thanh ghi

Control v Data ca JTAG UART vit k t Z ra terminal window


ca Altera Debug Client.
333

Tham kho on code sau:


M SOPC Builder, a ch ny
.include "nios_macros.s"

phi ging Base Address ca

.equ UART, 0x00009000

.global _start
_start:
movia r4, UART
movi r3, 'Z'

CHECK:
ldwio r2, 4(r4)
srli r2, r2, 16
beq r2, r0, CHECK
stbio r3, 0(r4)
br CHECK
END:
br END

.end

Bc 2.

S dng Altera Debug Client compile v load chng trnh

trn.
Bc 3.

Chy chng trnh, s dng single step (Nu s dng ch

Continue, k t s gi ra terminal window nhanh ti khng th theo di


c).
334

Bc 4.

Theo di v gii thch ngha chng trnh.

Bc 5.

Sa li on code trn sao cho k t ch c in ra terminal sau

khong thi gian xp x na giy.


Gi :
 Input Clock Requency: 50 MHz
 Lnh ca mi loi Nios II/e, Nios II/s hay Nios II/f thc hin cn
s chu k khc nhau. Tham kho:

Hnh 6.56 S chu k cho mi lnh

335

Hnh 6.57 S chu k cho mi lnh

336

Hnh 6.58 S chu k cho mi lnh


Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Vit code cho phn 4
Recompile, load v chy li chng trnh.
Gii thch ngha chng trnh phn code mu v phn code to na
giy.

337

6.3.4.3 Phn 3

JTAG UART khng ch c th vit k t ASCII ra terminal window ca


Debug Client m cn c th nhn k t t terminal window.
Bit RVALID_bit 15 ca thanh ghi Data ch ra khi no vng Data trong thanh
ghi Data l 1 k t hp l. Nu nhiu k t ch i c c, vng RAVAIL s
c gi tr khc 0.
Cc bc thc hin
Bc 1.

Vit chng trnh c mi k t m c nhn bi JTAG

UART t host computer v hin th k t ny trong terminal window ca


Debug Client. S dng polling (1 vng lp lin tc) bit khi no c k
t mi t JTAG UART
Bc 2.

Code tham kho:

.include "nios_macros.s"
.equ UART_BASE,

0x8820

.equ TIMER,

0x8800

.global _start
_start:
movia r8, UART_BASE

GET_CHAR_LOOP:
ldwio r17, 0(r8)
338

andi

r20, r17, 0x8000

beq

r20, r0, GET_CHAR_LOOP

andi

r16, r17, 0x00ff

PUT_CHAR_LOOP:
ldwio r17, 4(r8)
andhi r17, r17, 0xffff
beq

r17, r0, PUT_CHAR_LOOP

stwio r16, 0(r8)

br

GET_CHAR_LOOP

br

END

END:

.end
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Gii thch ngha cho on code mu trn
Compile, load v chy chng trnh trn.
Quan st v gii thch ngha gii thut, v lu gii thut.

6.3.4.4 Phn 4

T Phn 1 ti Phn 3 ta lm quen vi polling, Phn 4 hng dn nh th


no s dng interrupts.
Khi to 1 interrupt-service routine c k t c nhn bi JTAG UART
t host computer, ta t interrupt-service routine ti a ch 0x20 (Tht s l Base
339

Address ca memory + 0x20, a ch ny l mc nh cho exception handler do


SOPC Builder chn). Exception tr v a ch trong thanh ghi ea phi c gim 4
cho nhng external interrupts.

Exception

Vector

located

0x20

Hnh 6.59 Exception Vector


y l mu chung khi vit 1 interrupt-service routine

.include nios macros.s


.text
.org 0x20

/* Place the interrupt service routine */


/* at the appropriate address */

ISR:
rdctl et, ctl4

/* Check if an external */

beq et, r0, SKIP EA DEC


340

/* interrupt has occurred */

subi ea, ea, 4

/* If yes, decrement ea to

execute */
/* interrupted instruction */
SKIP EA DEC:
... the interrupt-service routine
END ISR:
eret

/* Return from exception */

.global start
_start:

/* Program start location */

... enable interrupts code

... the main program code

LOOP:
br LOOP

/* Endless loop */

.end
Ch ti ngha nhng thanh ghi iu khin: (xem Nios II Processor
Reference Handbook)
 Thanh ghi ctl3: Trong Part I, JTAG UART c t ti interrupt
level 0. iu ny c ngha l bit 0 ca ctl3 phi c gn gi tr 1
interrupt ca JTAG UART hot ng.
 Thanh ghi ctl0: Bit 0 ca thanh ghi ctl0 c gn gi tr 1 cho php
external interrupt.
341

 Thanh ghi iu khin ca JTAG UART: RE = 1


Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim Tnh vng bui ).
V lu gii thut ca interrupt-service routine tng qut trn.

Yu cu Phn 4:
 To 1 interrupt-service routine c 1 k t t JTAG UART.
Trong interrupt-service routine, s dng dng polling hin th k
t nhn c t host computer.
 Code tham kho:
.include "nios_macros.s"
.equ UART_BASE,

0x9020

.equ TIMER,

0x9000

.equ STACK,

0x8000

.text
/********************************************
.global _start
_start:
br

PROGRAM_START

/********************************************
.org 0x0020
ISR:
subi sp, sp, 24
stw

et, 20(sp)
342

rdctl et, ctl4


beq

et, r0, SKIP_EA_DEC

subi ea, ea, 4


SKIP_EA_DEC:
stw

ea, 0(sp)

stw

ra, 4(sp)

stw

fp, 8(sp)

stw

r21, 12(sp)

stw

r22, 16(sp)

addi fp, sp, 24


rdctl et, ctl4
bne

et, r0, CHECK_LEVEL_0

NOT_EI:
br

END_ISR

CHECK_LEVEL_0:
movi r21, 1
and

r22, et, r21

beq

r22, r0, CHECK_LEVEL_1

call

JTAG_UART_ISR

br

END_ISR

CHECK_LEVEL_1:
br

END_ISR

END_ISR:
ldw

ea, 0(sp)

ldw

ra, 4(sp)

ldw

fp, 8(sp)
343

ldw

r21, 12(sp)

ldw

r22, 16(sp)

ldw

et, 20(sp)

addi sp, sp, 24

eret

/*******************************************
PROGRAM_START:
movia sp, STACK
mov fp, sp
movia r8, UART_BASE
movi r23, 1
stw

r23, 4(r8)

wrctl ctl3, r23


wrctl ctl0, r23
END:
br

END

.end
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Vit

sub_routine:

JTAG_UART_ISR

JTAG_UART_PUT_CHAR
 JTAG_UART_ISR kim tra nu UART c data mi v lu data
mi vo memory, sau gi JTAG_UART_PUT_CHAR.
344

 JTAG_UART_PUT_CHAR s ly k t t memory v hin th


ln terminal window ca Altera Debug Client.
Compile, load v chy chng trnh.

6.3.4.5 Phn 5

Vit chng trnh s dng interrupts c k t nhn t host


computer v hin th k t nhn c sau 500 msec.
Trong Phn 2 ta s dng 1 delay loop to khong thi gian xp
x 500 msec. Phn 5, chng ta s s dng Interval Timer. Sau mi 500 msec,
Interval Timer s interrupt processor.

Cho
Hnh 6.60 Thanh ghi ca Timer

php

Interrupt

Timer khi bng 1

Ti liu tham kho Interval Timer: Chng 12 Altera Embedded


Peripherals Hand-Book
Yu cu Phn 5:
Tham kho on code sau:

345

.include "nios_macros.s"
.equ UART_BASE,

0x9020

.equ TIMER,

0x9000

.equ STACK,

0x8000

.text

.global _start
_start:
br

PROGRAM_START

/********************************************************
*/
.org 0x0020
ISR:
subi sp, sp, 24
stw

et, 20(sp)
rdctl et, ctl4
beq

et, r0, SKIP_EA_DEC

subi ea, ea, 4

SKIP_EA_DEC:
stw

ea, 0(sp)
stw

ra, 4(sp)

stw

fp, 8(sp)

stw

r21, 12(sp)

stw

r22, 16(sp)
346

addi fp, sp, 24


rdctl et, ctl4
bne

et, r0, CHECK_LEVEL_0

br

END_ISR

NOT_EI:

CHECK_LEVEL_0:
movi r21, 1
and

r22, et, r21

beq

r22, r0, CHECK_LEVEL_1

call

JTAG_UART_ISR

br

END_ISR

CHECK_LEVEL_1:
slli

r21, r21, 1

and

r22, et, r21

beq

r22, r0, CHECK_LEVEL_2

call

INTERVAL_TIMER_ISR

br

END_ISR

CHECK_LEVEL_2:
br

END_ISR

ldw

ea, 0(sp)

END_ISR:

ldw

ra, 4(sp)
347

ldw

fp, 8(sp)
ldw

r21, 12(sp)

ldw

r22, 16(sp)

ldw

et, 20(sp)

addi sp, sp, 24

eret
/*********************************/
/* INTERVAL_TIMER_ISR sub routine */
/********************************/
INTERVAL_TIMER_ISR:
subi sp, sp, 12
stw

ra, 0(sp)

stw

fp, 4(sp)

stw

r10, 8(sp)

addi fp, sp, 12

movia r10, TIMER


stw

r0, 0(r10)

call

JTAG_UART_PUT_CHAR

END_INTERVAL_TIMER_ISR:
ldw

ra, 0(sp)

ldw

fp, 4(sp)

ldw

r10, 8(sp)

addi sp, sp, 12


ret
348

/****************************/
PROGRAM_START:
movia sp, STACK
mov fp, sp
movia r8, UART_BASE
movia r10, TIMER
movi r18, 1
stwio r18, 4(r8)
sthio r18, 4(r10)
movi r18, 3
wrctl ctl3, r18
movi r18, 1
wrctl ctl0, r18
END:
br

END

THE_CHAR:
.ascii

"Z"

.end
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui ).
Nu ngha on code trn.
Ch : sinh vin vit cc sub_routine sau:
 JTAG_UART_ISR: kim tra nu UART c data mi v lu data
mi vo memory.
 JTAG_UART_PUT_CHAR: ly k t t memory v hin th ln
terminal window ca Altera Debug Client.
349

Compile, load v chy chng trnh.


Quan st hin tng v gii thch, nu ngha gii thut chng trnh.

6.3.5

Bi thc hnh s 5 Tm hiu cch thc giao tip Bus

Mc ch
Tm hiu v cch thc giao tip thng qua bus. Trong nhng thit k c
to bi SOPC-Builder, cc thit b ngoi vi giao tip vi Nios processor thng qua
nhng Peripheral Interface Module ( c to ra bi SOPC-Builder ) v Avalon
Switch Fabric. Tuy nhin, ta c th s dng bus truyn/nhn d liu gia cc thit
b ngoi vi vi Nios processor m khng cn dng nhng Peripheral Interface
Module c to bi SPOC-Builder. thc hin c iu ny, ta s s dng
mt module Avalon to External Bus Bridge. Vi vic s dng module ny, giao
tip gia Nios processor vi mt External Slave Interface ta ch cn to mt
Peripheral Interface Module (by manual) n gin thc hin vic kt ni.
c th to c mt Peripheral Interface Module (by manual), trc ht
ta phi hiu ngha ca nhng tn hiu connect gia Avalon to External Bus
Bridge vi External Slave Peripheral.

350

Hnh 6.61 M hnh Nios System dng Avalon to External Bus Bridge
 Address : a ch ca Data c c ra hoc a ch m Data cn
ghi vo trong Virtual Memory of Avalon to External Bus Bridge.
 WriteData : Data bus c ghi vo External Slave Peripheral t
Memory of Avalon to External Bus Bridge khi WR\ = 0. Ta c
th chn rng ca Data bus : 8bits , 16 bits, 32 bits, 64 bits,
128bits.
 BusEnable : y l c bo hiu khi tt c nhng signals khc
valid, Data c th c Read or Write.
 ByteEnable : Cho php users chn Bytes khi truy xut Data.
 RW\ : Khi c ny ln 1, n cho php Read Data t External Slave
Peripheral vo Virtual Memory

of Avalon to External Bus

Bridge; khi c ny c gi tr 0, n cho php Write Data t


Virtual Memory of Avalon to External Bus Bridge ra External
Slave Peripheral.
 IRQ : External Slave Peripheral pht ra tn hiu yu cu ngt n
Nios processor.

351

 Acknowledge : External Slave Peripheral bo cho Nios processor


bit vic Read/Write Data c hon thnh.
 ReadData : Data bus c c ra t External Slave Peripheral
ghi vo Virtual Memory of Avalon to External Bus Bridge khi
RW\ = 1. Ta c th chn rng ca Data bus : 8bits , 16 bits, 32
bits, 64 bits, 128bits.

Hnh 6.62 Gin xung hot ng ca SRAM


6.3.5.1 Phn 1

Thit k mt h thng nh sau:

352

Hnh 6.63 Giao tip LED 7 on


Tng bc thc hin:
Bc 1.

To mt project Quartus mi, t tn:

Bc 2.

M SOPC Builder to mt Nios System vi tn nios_system

/lab5/Lab5_Part1

theo yu cu:
 Nios II/s processor vi JTAG Debug Module Level 1.
 On-chip memory RAM mode v size l 32 Kbytes.
 JTAG_UART- use default setting.
 Avalon to External Bus Bridge, thm module ny cn thc
hin cc bc sau:
i.

Download module ny t: ftp://ftp.altera.com/up/pub/University


Program IP Cores/avalon to external bus bridge.zip ), t trong th
mc cha project.

ii.

Trn SOPC Builder window, chn File  Refresh Component List

iii.

Chn Avalon Components  University Program DE2 Board 


Avalon to External Bus Bridge.

iv.

Chn Width data: 16 bits; Address range : 512 Kbytes.

353

v.

Connect Avalon to External Bus Bridge n NiosIIs data_master


port, khng connect n NiosIIs instruction_master.

Hnh 6.64 Connection gia cc components

Bc 3.

Chn System  Auto-Assign Base Addresses.

Bc 4.

Generate System.

Bc 5.

Add 3 modules Lab5_Part1, Peripheral_on_External_Bus,

Seven_Segment_Display (gi km theo file ni dung bi thc hnh 5


ny) vo project.
Bc 6.

Assign pins.

Bc 7.

Compile system.

Bc 8.

Program and Configure the Cyclone II FPGA.

Bc 9.

Vit mt chng trnh assemble thc hin vic ghi 4 gi tr :

0x0123; 0x4567; 0x89ab ; 0xcdef vo Virtual Memory of Avalon to


External Bus Bridge vi a ch u tin l 0x0000.
354

Bc 10.

Dng Altera Monitor Program download v thc thi chng

trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
Tm hiu v gii thch hot ng ca 3 modules (gi km theo file ni
dung bi thc hnh 5 ny).
Chun b trc nh chng trnh assemble thc hin vic ghi 4 gi
tr : 0x0123; 0x4567; 0x89ab ; 0xcdef vo Virtual Memory of
Avalon to External Bus Bridge vi a ch u tin l 0x0000.

6.3.5.2 Phn 2:

Thit k mt h thng nh sau:

Hnh 6.65 Giao tip vi RAM


Bc 1.

To mt project Quartus mi, t tn:

Bc 2.

Lm ging Phn 1

355

/lab5/Lab5_Part2

Bc 3.

Add 2 modules Lab5_Part2, SRAM_Controller (gi km theo

file ni dung bi thc hnh 5 ny) vo project.


Bc 4.

Vit mt chng trnh Assemble thc hin ghi 4 gi tr :

0x0123; 0x4567; 0x89ab ; 0xcdef vo SRAM vi a ch u tin l


0x0000, sau c ngc tr li 4 gi tr vo nhng thanh ghi ca
processor.
Bc 5.

Dng Altera Monitor Program download v thc thi chng

trnh.
Note : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
Tm hiu v gii thch hot ng ca 2 modules Lab5_Part2,
SRAM_Controller (gi km theo ni dung bi thc hnh 5 ny).
Chun b trc nh chng trnh assemble thc hin vic ghi 4 gi
tr : 0x0123; 0x4567; 0x89ab ; 0xcdef vo SRAM vi a ch u tin
l 0x0000 , sau c ngc tr li 4 gi tr vo nhng thanh ghi
ca processor.

6.3.5.3 Phn 3:

Thit k mt h thng gm hai External Slave Peripheral nhng ch s dng


mt Avalon to External Bus Bridge nh sau:

356

Hnh 6.66 Giao tip vi RAM v LED 7 on

Bc 1.

To mt project Quartus mi, t tn:

Bc 2.

Lm ging Phn 1

Bc 3.

Sa 5 modules s dng trong Part1 v Part2 tha mn h

/lab5/Lab5_Part3

thng nh trn (gi km theo ni dung bi thc hnh 5 ny) vo project.


Bc 4.

Vit mt chng trnh Assemble thc hin ghi 4 gi tr :

0x0123; 0x4567; 0x89ab ; 0xcdef vo SRAM vi a ch u tin l


0x0000, sau c 4 gi tr vo nhng Seven Segment Display.
Bc 5.

Dng Altera Monitor Program download v thc thi chng

trnh.
Ch : Sinh vin cn chun b trc nh nhng cng vic sau (Khng c
bi chun b khng c vo lp lm th nghim  Tnh vng bui )
357

Sa 5 modules s dng trong Phn 1 v Phn 2 tha mn h


thng nh trn (gi km theo ni dung bi thc hnh 5 ny) vo
project.
Chun b trc nh chng trnh assemble thc hin vic ghi 4 gi
tr : 0x0123; 0x4567; 0x89ab ; 0xcdef vo SRAM vi a ch u tin
l 0x0000 , sau c 4 gi tr vo nhng Seven Segment Display.

358

Chng 7.

M phng m t thit k bng ModelSim

7.1 Gii thiu


Phn ny s trnh by cc cc bc chy m phng pre-synthesis v postsynthesis cho mt m t thit k Verilog s dng cng c ModelSim.
Thng qua phn ny, sinh vin s hiu s khc nhau gia hai kiu m phng
trn cng nh l do khi no phi chy m phng pre-synthesis hoc post-synthesis.
im khc nhau c bn gia chy m phng pre-synthesis v post-synthesis
:
Khi chy m phng pre-synthesis th delay timing ca thit k s
khng c phn tch trong qu trnh chy m phng v do delay
timing gia cc node bn trong thit k s bng 0. V vy thi gian
chy m phng loi ny s tn t thi gian, hiu qu trong vic kim
tra v debug v chc nng (function) ca thit k.
Khi chy m phng post-synthesis th delay timing ca thit k s
c ly sau qu trnh synthesis v c dng phn tch trong qu
trnh chy m phng v do delay timing gia cc node bn trong
thit k s c ly t file SDF (Standard Delay Format). Do phi
phn tch delay timing cng nh Verilog netlist sau qu trnh
synthesis ln nn thi gian chy m phng loi ny s tn rt nhiu
thi gian, c bit trong nhng thit k h thng ln, thi gian chy
m phng c th ln n hng gi ng h nn s khng hiu qu
trong vic kim tra chc nng (function) ca thit k, nhng n s
cung cp thng tin kh chnh xc v nh thi cho thit k, iu ny s
gip ngi thit k trong qu trnh kim tra v debug v timing ca
thit k.

359

Hai u im ca chy m phng dng ModelSim so vi chy m phng trn


Quartus l:
Khng th chy m phn pre-synthesis trn Quartus.
Khng th chy m phng dng testbench trn Quartus. Hn ch ny
c th khng nhn ra khi to input cho mt thit k n gin vi t
inputs vi dng sng n gin. Tuy nhin, i vi mt thit k h
thng ln th m phng dng Quartus l hon ton khng kh thi v ta
khng th to dng sng manually nh trn Quartus, m ta phi vit
testbench to dng sng cho inputs.

7.2 M phng pre-synthesis


thc hin m phng cho mt thit k trc khi synthesis, ta thc hin cc
bc sau.
Bc 1.

M phn mm ModelSim

Hnh 7.1 Ca s ModelSim


360

Bc 2.

Nhn Jumpstart bt u lm vic vi ModelSim

Hnh 7.2 Ca s to project mi


Bc 3.

in thng tin v tn project, ng dn cng nh tn Library

cho project mi. Ta c th t tn cho project cng nh ng dn ca


project ty .

Hnh 7.3 Ca s in thng tin cho project


361

Bc 4.

Nhn OK, mt ca s mi hin ra, chn Create New File

Hnh 7.4 To new file


Bc 5.

Nhp ng dn v tn cho file mi cn to, gi s y ta

ang mun thit k mt D-Flipflop, ta t tn file l ModelSimTest.v, v


t file ny vo trong th mc va to project

Hnh 7.5 in thng tin cho new file


Bc 6.

Nhn OK, quay tr v ca s trong bc 4, nhn Close

362

Hnh 7.6 Ca s sau khi to project


Bc 7.

Double click vo D_Flipflop.v bn mn hnh Workspace, mt

ca s dng cho vic m t thit k dng Verilog xut hin

Hnh 7.7 Ca s dng cho m t thit k


Bc 8.

Dng ngn ng Verilog m t thit k, y ta ang thc hin

v d l m t thit k mt D-Flipflop
363

Hnh 7.8 M t thit k D-Flipflop


Bc 9.

To Testbench nh ngha dng sng cho cc tn hiu input

ca thit k. Ta m tip mt ca s khc cng dng Verilog thit k


bng cch chn tab File  New  Source  Verilog

Hnh 7.9 To new file


364

Bc 10.

Mt ca s mi dng Verilog m t thit k khc xut hin,

ta m t testbench cho thit k nh sau

Hnh 7.10 M t Testbench cho thit k


Bc 11.

Lu testbench cho thit k vi tn Testbench.v

Hnh 7.11 Lu m t testbench


365

Bc 12.

Add file Testbench.v va to vo project, chn tab Project 

Add to Project  Existing File

Hnh 7.12 Add file Testbench vo project


Bc 13.

Ch ng dn n file Testbench

Hnh 7.13 Ch ng dn n file Testbench


Bc 14.

Ca s Workspace xut hin nh sau

Hnh 7.14 Ca s Workspace sau thit k


Bc 15.

Compile m t thit k, chn tab Compile  Compile All

366

Hnh 7.15 Compile thit k


Bc 16.

Nu m t thit k khng c li th s c thng bo sau

Hnh 7.16 Compile thnh cng


Bc 17.

Sau khi ta m t thit k v m t testbench cho thit kt thnh

cng ta s thc hin cc bc chy m phng, chn tab Simulate  Start


Simulation

367

Hnh 7.17 Thit lp m phng


Bc 18.

Mt ca s nh hnh di xut hin, ta chn tab Design 

work  Testbench. Nhn OK.

Hnh 7.18 Chn thit k cn m phng


Bc 19.

Mt ca s nh sau xut hin, Click phi chut ln Testbench

 Add  To Wave  All items in region

368

Hnh 7.19 Chn tn hiu dng sng cn quan st


Bc 20.

Ca s dng sng c m ra

369

Hnh 7.20 Ca s dng sng


Bc 21.

Chn khong thi gian chy m phng

Hnh 7.21 Thit lp thi gian chy m phng


Bc 22.

Nhn nt chy m phng

Hnh 7.22 Chy m phng


Bc 23.

Sau khi chy xong, mt thng bo hi xut hin

370

Hnh 7.23 Nhn "No"


Bc 24.

Chn No, dng sng sau khi m phng xut hin, nhn nt

Zoom Full thy ton b dng sng

Hnh 7.24 Dng sng sau m phng

Bc 25.

Quan st ta thy, tn hiu ng ra khng c delay timing so vi

cc tn hiu ng vo. Bi v y l m phng pre-synthesis nn trong qu


trnh chy m phng, thng tin v nh thi cho cc node bn trong thit
k khng c cung cp, do delay timing gia cc node ny l bng 0.
Bc 26.

Quan st dng sng v debug function nu c sai.

371

7.3 M phng post-synthesis


thc hin m phng post-systhesis mt m t thit k dng verilog, ta
thc hin gm hai qu trnh, d hiu ta s thc hin cc bc vi mt m t
thit k mt mch D-flipflop.
7.3.1

Dng Quartus to Verilog netlist cho vic m phng post-synthesis

Bc 1.

To Quartus project, tn project c t l : ModelSimTest

(phn ny c trnh by chi tit trong phn 5.1.1)


Bc 2.

S dng Verilog m t thit k module D-flipflop nh sau:

(phn ny c trnh by chi tit trong phn 5.1.2)

Hnh 7.25 M t thit k D-Flipflop

Bc 3.

Thit lp thng s cho qu trnh systhesis v compilation

372

Hnh 7.26 Thit lp thng s cho qu trnh synthesis


Bc 4.

Chn EDA Tool Settings  Simulation, chn cc option v

in thng tin nh sau

373

Hnh 7.27 Thit lp thng s


Bc 5.

Bin

dch

(compilation)

thit

k,

mt

th

mc

simulation/modelsim (v ta ch ng dn cho Output directory trong


bc 4) c to ra ngay ti th mc cha project

374

Hnh 7.28 Th mc sau qu trnh synthesis


Bc 6.

Trong th mc ny ta thy hai file quan trng s s dng cho

vic chy m phng post-synthesis c to ra

Hnh 7.29 Hai file quan trng c to ra

7.3.2

Dng ModelSim chy m phng post-synthesis

Bc 1.

M phn mm ModelSim
375

Hnh 7.30 Ca s ModelSim


Bc 2.

Nhn Jumpstart bt u lm vic vi ModelSim

Hnh 7.31 To project mi

376

Bc 3.

in thng tin v tn project, ng dn cng nh tn Library

cho project mi, y ta cn ch v ta to file netlist.vo v file SDF


.sdo trong th mc simulation/modelsim nh trnh by trong phn
7.3.1, nn cho thun tin ta ch ng dn cho project ModelSim mi
ny nm trong th mc simulation/modelsim lun, tuy nhin ta c th
to ng dn bt k cho project mi ny, sau ta ch cn copy hai file
netlist.vo v file SDF .sdo vo th mc va to l c.

Hnh 7.32 in thng tin cho project mi


Bc 4.

Nhn OK

377

Hnh 7.33 Add file thit k c sn


Bc 5.

Chn Add Existing File, ch ng dn n file netlist.vo

Hnh 7.34 Ch ng dn n file Verilog netlist


Bc 6.

Nhn OK, quay v ca s trong bc 4, chn Create New File

Hnh 7.35 To file m t thit k mi


378

Bc 7.

Nhp ng dn v tn cho file mi cn to, ta t tn file l

Testbech, v t file ny vo trong th mc simulation/modelsim

Hnh 7.36 in thng tin cho new file


Bc 8.

Nhn OK, quay tr v ca s trong bc 4, nhn Close

Hnh 7.37 Ca s m t thit k c m ra


Bc 9.

Nhp double-click vo Testbench.v, mt ca s c xut hin,

cho php ta dng ngn ng Verilog m t Testbench cho thit k. Gi


s Testbench c m t nh sau

379

Hnh 7.38 M t Testbench cho thit k


Bc 10.

Lu file Testbench, chy compile cho thit k

Hnh 7.39 Compile thit k


Bc 11.

Nu khng c li g, th s c thng bo sau

380

Hnh 7.40 M t thit k thnh cng


Bc 12.

Thit lp chy m phng

Hnh 7.41 Thit lp m phng


Bc 13.

Ca s thit lp c m ra

381

Hnh 7.42 Ca s thit lp m phng


Bc 14.

Chn Tab Libraries, nhn Add, ch ng dn cho library nh

hnh di. Ch , do khi to Quartus project, ta ch n chip FPGA l


CycloneII, nn trong bc ny ta cng phi ch n ng dn th mc
cha library ca CycloneII. Trong library ny cha cc standard
components, m nhng standard component ny c gi trong file
netlist.vo

382

Hnh 7.43 Ch Libraries cho thit k


Bc 15.

Ta thy c Tab SDF, tuy nhin ta khng cn thit lp ng

dn ch n file SDF .sdo ny do file ny c t trong cng th mc


vi file netlist.vo, nu ta m file netlist.vo ln, ta c th thy trong file
ny gi n file .sdo ri.

383

Hnh 7.44 File SDF c gi trong Verilog netlist

Bc 16.

Chn Tab Design  Work  Testbench  OK

384

Hnh 7.45 Chn thit k cn chy m phng


Bc 17.

Ca s chy m phng c to ra

Hnh 7.46 Ca s waveform m ra


Bc 18.

Click chut phi ln Testbench, chn Add  To Wave  All

items in region

385

Hnh 7.47 Chn tn hiu cn xem waveform

Bc 19.

Ca s dng sng c m ra

386

Hnh 7.48 Ca s dng sng m phng


Bc 20.

Chn khong thi gian chy m phng

Hnh 7.49 Thit lp thi gian chy m phng


Bc 21.

Nhn nt chy m phng

Hnh 7.50 Chy m phng


Bc 22.

Sau khi chy xong, mt thng bo hi xut hin

387

Hnh 7.51 Nhn "No"


Bc 23.

Chn No, dng sng sau khi m phng xut hin, nhn nt

Zoom Full thy ton b dng sng

Hnh 7.52 Dng sng sau m phng


Bc 24.

Quan st ta thy, tn hiu ng ra c delay timing so vi cc tn

hiu ng vo. Delay timing ny do file SDF .sdo to ra. M timing trong
file SDF c to ra da trn cng ngh thit k ca FPGA CycloneII.
Bc 25.

Quan st dng sng v debug function v timing nu c sai.

388

7.3.3

M li project v waveform chy m phng

Phn ny tp trung trnh by cc bc m li waveform c to ra


khi chy m phng ri m khng cn chy li m phng ln na. V sao ta cn
quan tm n iu ny. Nu mt thit k nh nh D-flipflop nh trn chng hn th
netlist c to ra nh v dng sng chy m phng cng n gin, thi gian dng
sng cng ngn do thi gian i qu trnh chy m phng l khng ng k.
Tuy nhin, nu mt thit k h thng ln, netlist s rt ln, dng sng cng di v
phc tp, nn thi gian i cho mt ln chy m phng rt lu, c th ln n hng
gi ng h. Nh vy, chng hn ta mt 5 gi chy m phng ln u xong,
ngy hm sau ta mun xem li waveform, ta khng th li phi mt 5 gi ng h
chy li m phng ln na. Chnh v th ta cn m li waveform chy ri theo
cc bc nh sau:
Bc 1.

M li project

389

Hnh 7.53 M li project


Bc 2.

Ch ng dn project cn m

Hnh 7.54 Ch ng dn project cn m


Bc 3.

Nhp cc lnh sau du nhc ModelSim>

390

Hnh 7.55 Ca s Transcript


 ModelSim> vsim view vsim.wlf , nhn Enter

Hnh 7.56 Nhp dng lnh nh trn


 ModelSim> view wave , nhn Enter

Hnh 7.57 Nhp dng lnh nh trn


 ModelSim> add wave * , nhn Enter

391

Hnh 7.58 Nhp dng lnh nh trn


Bc 4.

Dng sng m phng xut hin, nhn nt Zoom Full thy

ton b dng sng


Bc 5.

Quan st dng sng v debug function cng nh timing.

392