`include "reg_sipo.

v" `timescale 1ns/100ps module reg_sipo_tb; reg reg reg reg reg reg data_in; load; shift; rl; reset_n; clk;

wire [7:0]data_out; wire [7:0]data; reg_sipo a1 (data_in, load, shift, rl, reset_n, clk, data_out, data );

always #10 clk=~clk; initial begin reset_n=0; clk=0; load=0; data_in=0; rl=1; shift=0; #10 reset_n=1; rl=0; load=1; data_in=1; shift=0; #20 reset_n=1; rl=0; load=0; shift=1; data_in=1; #60 reset_n=1; rl=0; load=0; shift=1; data_in=0; #60 reset_n=1; rl=0;

load=0; shift=1; data_in=1; #40 $stop; $finish; end endmodule