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// 2X4 DECODER USING GATE / DATA / BEHAVIORAL

module DEC24(x,y,en);
input [1:0] x;
output [3:0] y;
input en;
and g1 (y[3],en,x[1],x[0]);
and g2 (y[2],en,x[1],~x[0]);
and g3 (y[1],en,~x[1],x[0]);
and g4 (y[0],en,~x[1],~x[0]);
endmodule
module DECODER24_GATE(x,y,en);
input [1:0] x;
output [3:0] y;
input en;
and g1 (y[3],en,x[1],x[0]);
and g2 (y[2],en,x[1],~x[0]);
and g3 (y[1],en,~x[1],x[0]);
and g4 (y[0],en,~x[1],~x[0]);
endmodule
module DECODER24_DATAFLOW(x,y,en);
input [1:0] x;
output [3:0] y;
input en;
assign y[3] = en&x[1]&x[0];
assign y[2] = en&x[1]&~x[0];
assign y[1] = en&~x[1]&x[0];
assign y[0] = en&~x[1]&~x[0];
endmodule

module DECODER24_Behavioral(x,y,en);
input [1:0] x;
output reg [3:0] y;
input en;
always @ ( x or en)
begin
if(en == 1)
case (x)
2'b00 : {y[3],y[2],y[1],y[0]} = 4'b0001;
2'b01 : {y[3],y[2],y[1],y[0]} = 4'b0010;
2'b10 : {y[3],y[2],y[1],y[0]} = 4'b0100;
2'b11 : {y[3],y[2],y[1],y[0]} = 4'b1000;
default : {y[3],y[2],y[1],y[0]} = 4'bxxxx;
endcase

if (en == 0)
{y[3],y[2],y[1],y[0]} = 4'b0000;
end
endmodule
// 4x2 ENCODER USING GATE / DATA / BEHAVIORAL
module ENC42(x,y,en);
input [3:0] x;
input en;
output [1:0] y;
wire w1;
or (w1,x[3],x[1]);
and (y[1],w1,en);
and (y[0],~x[1],~x[0],en);
endmodule
module ENCODER42_GATE(x,y,en);
input [3:0] x;
input en;
output [1:0] y;
wire w1;
or (w1,x[3],x[1]);
and (y[1],w1,en);
and (y[0],~x[1],~x[0],en);
endmodule
module ENCODER42_DATAFLOW(x,y,en);
input [3:0] x;
input en;
output [1:0] y;
assign y[1]=(x[3]|x[1])&en;
assign y[0]=~x[1]&~x[0]&en;
endmodule
module ENCODER42_Behavioral(x,y,en);
input [3:0] x;
input en;
output reg [1:0] y;
always @ (x)
begin
if (en == 1)
case (x)
4'b0000 : {y[1],y[0]} = 2'bxx;
4'b0001 : {y[1],y[0]} = 2'b00;
4'b0010 : {y[1],y[0]} = 2'b01;

4'b0100 : {y[1],y[0]} = 2'b10;


4'b1000 : {y[1],y[0]} = 2'b11;
endcase
end
endmodule
// FULL SUBTRACTOR USING GATE / DATA / BEHAVIORAL
module FS(a,b,bin,bout,diff);
input a,b,bin;
output bout,diff;
xor g1 (w1,a,b);
xor g2 (diff,w1,bin);
and g3 (w2,b,~a);
and g4 (w3,~w1,bin);
or g5 (bout,w2,w3);
endmodule
module FS_GATE(a,b,bin,bout,diff);
input a,b,bin;
output bout,diff;
xor g1 (w1,a,b);
xor g2 (diff,w1,bin);
and g3 (w2,b,~a);
and g4 (w3,~w1,bin);
or g5 (bout,w2,w3);
endmodule

module FS_DATAFLOW(a,b,bin,bout,diff);
input a,b,bin;
output bout,diff;
assign bout = (b&~a)|(~(a^b)&bin);
assign diff = a^b^bin;
endmodule
module FS_Behavioral(a,b,bin,bout,diff);
input a,b,bin;
output reg bout,diff;
always @ (a or b or bin)
begin
case ({a,b,bin})
3'b000 : {diff,bout} = 2'b00;
3'b001 : {diff,bout} = 2'b11;
3'b010 : {diff,bout} = 2'b11;
3'b011 : {diff,bout} = 2'b01;

3'b100 : {diff,bout} = 2'b10;


3'b101 : {diff,bout} = 2'b00;
3'b110 : {diff,bout} = 2'b00;
3'b111 : {diff,bout} = 2'b11;
endcase
end
endmodule
// 1x4 DEMUX USING GATE/DATA/BEHAVIORAL
module DEMUX14(x,y,s,enb);
input x;
output [3:0] y;
input [1:0] s;
input enb;
and (y[3],~s[1],~s[0],~enb,x);
and (y[2],~s[1],s[0],~enb,x);
and (y[1],s[1],~s[0],~enb,x);
and (y[0],s[1],s[0],~enb,x);
endmodule
module DEMUX14_GATE(x,y,s,enb);
input x;
output [3:0] y;
input [1:0] s;
input enb;
and (y[3],~s[1],~s[0],~enb,x);
and (y[2],~s[1],s[0],~enb,x);
and (y[1],s[1],~s[0],~enb,x);
and (y[0],s[1],s[0],~enb,x);
endmodule
module DEMUX14_DATAFLOW(x,y,s,enb);
input x;
output [3:0] y;
input [1:0] s;
input enb;
assign y[3]=x&~s[1]&~s[0]&~enb;
assign y[2]=x&~s[1]&s[0]&~enb;
assign y[1]=x&s[1]&~s[0]&~enb;
assign y[0]=x&s[1]&s[0]&~enb;
endmodule
module DEMUX14_Behavioral(x,y,s,enb);
input x;
output reg [3:0] y;

input [1:0] s;
input enb;
always @ (x or s or enb)
begin
if(enb == 0)
case (s)
2'b00 : y[3] = x;
2'b01 : y[2] = x;
2'b10 : y[1] = x;
2'b11 : y[0] = x;
endcase
end
endmodule
// FULL ADDER GATE / DATA / BEHAVIORAL
module FA(a,b,c,s,carry);
input a,b,c;
output s,carry;
xor g1 (w1,a,b);
xor g2 (s,c,w1);
and g3 (w2,c,w1);
and g4 (w3,a,b);
or g5 (carry,w2,w3);
endmodule
module FA_GATE(a,b,c,s,carry);
input a,b,c;
output s,carry;
xor g1 (w1,a,b);
xor g2 (s,c,w1);
and g3 (w2,c,w1);
and g4 (w3,a,b);
or g5 (carry,w2,w3);
endmodule
module FA_DATAFLOW(a,b,c,s,carry);
input a,b,c;
output s,carry;
assign s = a^b^c;
assign carry = ((a^b)&c)|(a&b);
endmodule
module FA_Behavioral(a,b,c,s,carry);
input a,b,c;
output reg s,carry;
always @ (a or b or c)

begin
case ({a,b,c})
3'b000 : {s,carry} = 2'b00;
3'b001 : {s,carry} = 2'b10;
3'b010 : {s,carry} = 2'b10;
3'b011 : {s,carry} = 2'b01;
3'b100 : {s,carry} = 2'b10;
3'b101 : {s,carry} = 2'b01;
3'b110 : {s,carry} = 2'b01;
3'b111 : {s,carry} = 2'b11;
endcase
end
endmodule
// FLIP FLOPS
module DFF(d,clk,q);
input d,clk;
output reg q;
always @ (posedge clk)
q=d;
endmodule
module DLA(d,clk,q);
input d,clk;
output reg q;
always @ (d or clk)
begin
if(clk) q=d;
end
endmodule
module DSYNC(d,clk,q,rst);
input d,clk,rst;
output reg q;
always @ (posedge clk)
begin
if(!rst) q=1'b0;
else q=d;
end
endmodule
module DASYNC(d,clk,q,rst);
input d,clk,rst;
output reg q;
always @ (posedge clk or negedge rst)

begin
if(!rst)q=1'b0;
else q=d;
end
endmodule
module SR(s,r,clk,q);
input s,r,clk;
output reg q;
reg qbar;
always @ (posedge clk)
begin
if (s==0 && r==1)
q=0;
else if (s==1 && r==0)
q=1;
else if (s==1 && r==1)
q=0;
end
endmodule
module TFF(t,clk,rst,q);
input t,clk,rst;
output q; reg temp;
always @ (posedge clk or negedge rst)
begin
if(!rst) temp=1'b0;
else if (t) temp = temp;
end
assign q=temp;
endmodule
module JK(j,k,clk,rst,q);
input j,k,clk,rst;
output q;
reg qn;
always @ (posedge clk or negedge rst)
begin
if(j == 1 && k == 0)
qn = 1;
else if(j == 0 && k == 1)
qn = 0;
else if(j== 1 && k == 1)
qn = ~qn;
end

assign q=qn;
endmodule
// HALF ADDER - GATE / DATA / BEHAVIORAL
module HA (s,c,x,y);
output s,c;
input x,y;
wire s,c,x,y;
xor G1 (s,x,y);
and G2 (c,x,y);
endmodule

module HA_GATE (s,c,x,y);


output s,c;
input x,y;
wire s,c,x,y;
xor G1 (s,x,y);
and G2 (c,x,y);
endmodule
module HA_DATAFLOW (s,c,x,y);
input x,y;
output s,c;
assign s= x^y;
assign c= x&y;
endmodule
module HA_Behavioral (s,c,x,y);
input x,y;
output reg s,c;
always @ (x or y)
begin
case ({x,y})
2'b00 : {s,c} = 2'b00;
2'b01 : {s,c} = 2'b10;
2'b10 : {s,c} = 2'b10;
2'b11 : {s,c} = 2'b01;
endcase
end
endmodule
// 4 X 2 PRIORITY ENCODER USING GATE / DATA FLOW / BEHAVIORAL
module PE4X2 (in,out);
input [3:0] in;
output [1:0] out;

wire w1,w2;
xor (out[1],in[3],~w1);
xor (out[0],in[3],~w2);
nand (w1,~in[3],in[2]);
nand (w2,~in[3],w1,in[1]);
endmodule
module PE_GATE_4X2 (in,out);
input [3:0] in;
output [1:0] out;
wire w1,w2;
xor (out[1],in[3],~w1);
xor (out[0],in[3],~w2);
nand (w1,~in[3],in[2]);
nand (w2,~in[3],w1,in[1]);
endmodule
module PE_DATAFLOW_4X2 (in,out);
input [3:0] in;
output [1:0] out;
assign out[1] = in[3]^(~(~(~in[3]&in[2])));
assign out[0] = in[3]^(~(~(~in[3]&in[1]&(~(~in[3]&in[2])))));
endmodule
module PE_BEHAVIORAL_4X2 (in,out);
input [3:0] in;
output reg [1:0] out;
always @ (in)
begin
case (in)
4'b0000 : {out[1],out[0]} = 2'bxx;
4'b0001 : {out[1],out[0]} = 2'b00;
4'b001x : {out[1],out[0]} = 2'b01;
4'b01xx : {out[1],out[0]} = 2'b10;
4'b1xxx : {out[1],out[0]} = 2'b11;
4'bxxxx : {out[1],out[0]} = 2'bxx;
default : {out[1],out[0]} = 2'bxx;
endcase
end
endmodule
// 4X1 MULTIPLEXER GATE / DATA / BEHAVIORAL
module MUX41(a,enb,s,y);
input [3:0] a;
input enb;
input [1:0] s;

output y;
wire w1,w2,w3,w4;
and (w1,a[3],~s[1],~s[0],~enb);
and (w2,a[2],~s[1],s[0],~enb);
and (w3,a[1],s[1],~s[0],~enb);
and (w4,a[0],s[1],s[0],~enb);
or (y,w1,w2,w3,w4);
endmodule
module MUX41_GATE(a,enb,s,y);
input [3:0] a;
input enb;
input [1:0] s;
output y;
wire w1,w2,w3,w4;
and (w1,a[3],~s[1],~s[0],~enb);
and (w2,a[2],~s[1],s[0],~enb);
and (w3,a[1],s[1],~s[0],~enb);
and (w4,a[0],s[1],s[0],~enb);
or (y,w1,w2,w3,w4);
endmodule
module MUX41_DATAFLOW(a,enb,s,y);
input [3:0] a;
input enb;
input [1:0] s;
output y;
wire w1,w2,w3,w4;
assign w1= a[3]&~s[1]&~s[0]&~enb;
assign w2= a[2]&~s[1]&s[0]&~enb;
assign w3= a[1]&s[1]&~s[0]&~enb;
assign w4= a[0]&s[1]&s[0]&~enb;
assign y= w1|w2|w3|w4;
endmodule
module MUX41_Behavioral(a,enb,s,y);
input [3:0] a;
input enb;
input [1:0] s;
output reg y;
wire w1,w2,w3,w4;
always @ (a or s or enb)
begin
if (enb == 0)
case (s)
2'b00 : y=a[3];

2'b01 : y=a[2];
2'b10 : y=a[1];
2'b11 : y=a[0];
endcase
end
endmodule
// HALF SUBTRACTOR GATE / DATA / BEHAVIORAL
module HS(x,y,diff,borrow);
input x,y;
output diff,borrow;
xor g1 (diff,x,y);
and g2 (borrow,~x,y);
endmodule
module HS_GATE(x,y,diff,borrow);
input x,y;
output diff,borrow;
xor g1 (diff,x,y);
and g2 (borrow,~x,y);
endmodule
module HS_DATAFLOW(x,y,diff,borrow);
input x,y;
output diff,borrow;
assign diff = x^y;
assign borrow=~x&y;
endmodule
module HS_Behavioral(x,y,diff,borrow);
input x,y;
output reg diff,borrow;
always @ (x or y)
begin
case ({x,y})
2'b00 : {diff,borrow} = 2'b00;
2'b01 : {diff,borrow} = 2'b11;
2'b10 : {diff,borrow} = 2'b10;
2'b11 : {diff,borrow} = 2'b00;
endcase
end
endmodule
/// FINITE STATE MACHINES 30/8/2012

module dec_111 (d,clk,rst,op);


input d,clk,rst;
output op;
reg [1:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=2'b00;
else cst=nst;
end
always @ (d or cst)
begin
case (cst)
2'd0: if(d) nst=2'd1; else nst=2'd0;
2'd1: if(d) nst=2'd2; else nst=2'd0;
2'd2: if(d) nst=2'd3; else nst=2'd0;
2'd3: if(d) nst=2'd3; else nst=2'd0;
default : nst=2'd0;
endcase
end
assign op=(cst==2'd3)?1'b1:1'b0;
endmodule
module dec_101 (d,clk,rst,op);
input d,clk,rst;
output op;
reg [1:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=2'b00;
else cst=nst;
end
always @ (d or cst)
begin
case (cst)
2'd0: if(d) nst=2'd1; else nst=2'd0;
2'd1: if(d) nst=2'd1; else nst=2'd2;
2'd2: if(d) nst=2'd3; else nst=2'd0;
2'd3: if(d) nst=2'd1; else nst=2'd2;
default : nst=2'd0;
endcase
end
assign op=(cst==2'd3)?1'b1:1'b0;
endmodule
module dec_101_110 (d,clk,rst,op);
input d,clk,rst;

output op;
reg [2:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=3'b000;
else cst=nst;
end
always @ (d or cst)
begin
case (cst)
/* STATE : IF (INPUT) JUMP TO NST ELSE ANOTHER STATE */
3'd0: if(d) nst=3'd1; else nst=3'd0;
3'd1: if(d) nst=3'd2; else nst=3'd5;
3'd2: if(d) nst=3'd2; else nst=3'd3;
3'd3: if(d) nst=3'd0; else nst=3'd0;
3'd4: if(d) nst=3'd2; else nst=3'd5;
3'd5: if(d) nst=3'd4; else nst=3'd0;
default : nst=3'd0;
endcase
end
assign op=(cst==3'd3 | cst==3'd4)?1'b1:1'b0;
endmodule
module MOD7_FSM (d,clk,rst,op);
input d,clk,rst;
output op;
reg [2:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=3'b000;
else cst=nst;
end
always @ (d or cst)
begin
case (cst)
/* STATE : IF (INPUT) JUMP TO NST ELSE ANOTHER STATE */
3'd0: if(d) nst=3'd1; else nst=3'd0;
3'd1: if(d) nst=3'd2; else nst=3'd1;
3'd2: if(d) nst=3'd3; else nst=3'd2;
3'd3: if(d) nst=3'd4; else nst=3'd3;
3'd4: if(d) nst=3'd5; else nst=3'd4;
3'd5: if(d) nst=3'd6; else nst=3'd5;
3'd6: if(d) nst=3'd0; else nst=3'd6;
3'd7: if(d) nst=3'd0; else nst=3'd0;
default : nst=3'd0;
endcase

end
assign op=cst;
endmodule
module seq_142306 (clk,rst,cen,q,d);
input clk,rst,cen,d;
output [2:0] q;
reg [2:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=3'b000;
else cst=nst;
end
always @(cen or cst)
case (cst)
3'd1: if(d) nst=3'd4; else nst=3'd1;
3'd4: if(d) nst=3'd2; else nst=3'd4;
3'd2: if(d) nst=3'd3; else nst=3'd2;
3'd3: if(d) nst=3'd0; else nst=3'd3;
3'd0: if(d) nst=3'd6; else nst=3'd0;
3'd6: if(d) nst=3'd1; else nst=3'd6;
default : nst=3'd0;
endcase
assign q=cst;
endmodule

module ring4 (clk,rst,q);


input clk,rst;
output [3:0] q;
reg [3:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=4'd0;
else cst=nst;
end
always @ (cst)
case (cst)
4'b1000 : nst=4'b0100;
4'b0100 : nst=4'b0010;
4'b0010 : nst=4'b0001;
4'b0001 : nst=4'b1000;
default : nst=4'b1000;
endcase
assign q=cst;
endmodule

module jhonson_counter (clk,rst,q);


input clk,rst;
output [3:0] q;
reg [3:0] cst,nst;
always @ (posedge clk or negedge rst)
begin
if(!rst) cst=4'd0;
else cst=rst;
end
always @ (cst)
case (cst)
4'b1000 : nst=4'b1100;
4'b1100 : nst=4'b1110;
4'b1110 : nst=4'b1111;
4'b1111 : nst=4'b0111;
4'b0111 : nst=4'b0011;
4'b0011 : nst=4'b0001;
4'b0001 : nst=4'b0000;
4'b0000 : nst=4'b1000;
default : nst=4'b1000;
endcase
assign q=cst;
endmodule