Utilizando todos los conceptos descritos hasta el momento podemos disear enVHDL u na memoria RAM sncrona genrica con

un puerto de lectura y otro de escritura,una seal deenable, otra dewritey otra deread : libraryieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; useieee.std_logic_unsigned.all; -- El paquete debe contener la funcin que pasa de std_logic_vector a -- natural, para poder acceder al array entity SRAM is generic ( w: integer:=4; -- ancho de palabra d: integer:=4; -- n de palabras a: integer:=2); -- ancho direccin port( Clock:instd_logic; Enable:instd_logic; Read:instd_logic; Write:instd_logic; Read_Addr:instd_logic_vector(a-1downto0); Write_Addr:instd_logic_vector(a-1downto0); Data_in:instd_logic_vector(w-1downto0); Data_out:outstd_logic_vector(w-1downto0) ); end SRAM; architecture behav of SRAM is -- Utilizamos un array para guardar los valores de la memoria type ram_type is array(0tod-1)ofstd_logic_vector(w-1downto0); signal tmp_ram: ram_type; begin -- Lectura process (Clock, Read) begin if(Clock'event and Clock='1')then if Enable='1'then if Read='1'then Data_out <= tmp_ram(std2n(Read_Addr)); else Data_out <= (Data_out'range=> 'Z'); -- Todos los bits de Data_out se ponen a 'Z' end if; end if; end if; end process; -- Escritura process (Clock, Write) begin if (Clock'event andClock='1') then if Enable='1'then if Write='1'then tmp_ram (std2n(Write_Addr)) <= Data_in; end if; end if; end if;

end process; end behav;